Hardware optimization method for test item

Abstract

The invention relates to the technical field of data storage, and discloses a hardware optimization method for a test item, and the method comprises an upper computer which is a PC end; the SOC module is a system-on-chip, the SOC module is a control core of the whole test system, and communication of the test system is achieved; the MCU control module performs asynchronous serial communication with an upper computer through a UART (Universal Asynchronous Receiver / Transmitter) interface, performs high-speed data exchange with the master control SOC module through an SPI (Serial Peripheral Interface) interface, completes communication between the upper computer and the SOC module through the MCU control module, and controls power on and power off of the SOC module at the same time; and the DDR end of the MCU control module is connected with the DDR module, and the MCU control module is used for carrying out current test on the DDR module. According to the invention, the test coverage rate, the signal integrity and the test efficiency are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, in particular to a hardware optimization method of test project. BACKGROUND

[0002] With the continuous improvement of mobile processor performance, the POP (Package-on-Package) packaging technology of MTK platform combined with LPDDR5X memory has become the mainstream solution of high-end mobile devices, and the addition of 496 ball BGA packaging structure requires higher requirements for test hardware. However, the traditional test method cannot meet the test requirements of current high-speed and high-density packaging. SUMMARY

[0003] The present application provides a hardware optimization method of test project, which can solve the technical problem that the traditional test method cannot meet the test requirements of current high-speed and high-density packaging.

[0004] To solve the above technical problems, one technical solution adopted by the present application is to provide a hardware optimization method of test project, which comprises: The host computer is a PC end; The SOC module is a system-level chip, and the SOC module is the control core of the entire test system, realizing communication of the test system; The MCU control module realizes asynchronous serial communication with the host computer through the UART interface, and realizes high-speed data exchange with the master SOC module through the SPI interface, and the communication between the host computer and the SOC module is completed through the MCU control module, and the on-off of the SOC module is controlled; The DDR module is connected with the DDR end of the MCU control module, and the current test of the DDR module is realized by the MCU control module.

[0005] The present application has the following advantages: through hierarchical design, each interface adaptation module has characteristics, and through retry and verification mechanism, accurate transmission of full-link instructions and data is realized, forming a communication closed loop without loss and disorder, improving test coverage, signal integrity and test efficiency, etc. The technical field of; accurately configure the SOC and DDR voltage in the domain, dynamically adjust the voltage balance performance and power consumption through DVFS as needed, strictly control the power-on sequence and slope, and execute the standard power-off sequence to ensure power supply safety; high-precision monitoring of DDR multi-state current, real-time verification of power supply parameters, structured processing of test data and generation of comparison report, providing accurate and readable basis for test evaluation; hardware-level rapid protection, software-level fault tolerance, and multi-module collaborative feedback, greatly reducing the risk of failure. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1It is a structural schematic diagram of a hardware optimization method of a test item of an embodiment of the present application.

[0007] Main element symbol explanation: 1, host computer, 2, SOC module, 3, MCU control module, 4, DDR module. DETAILED DESCRIPTION

[0008] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0009] The terms "comprising" and "having" and any variations thereof in the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to the process, method, product or device.

[0010] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily mutually exclusive of other embodiments, or alternative embodiments. It is explicitly and implicitly understood that the embodiments described herein can be combined with other embodiments.

[0011] Figure 1 It is a structural schematic diagram of a hardware optimization method of a test item of an embodiment of the present application. As shown in Figure 1 The method comprises: The host computer 1 is a PC end; The SOC module 2 is a system-level chip, which is the control core of the entire test system and realizes communication of the test system; The MCU control module 3 performs asynchronous serial communication with the host computer 1 (PC end) through the UART interface, and simultaneously performs high-speed data exchange with the master control SOC module 2 (U1001F) through the SPI interface. The communication between the host computer 1 and the SOC module 2 is completed through the MCU control module 3, and the on-off of the SOC module 2 is controlled through the MCU control module 3. The DDR (dynamic random access memory) module, the DDR end of the MCU control module 3 is connected with the DDR module 4, and the current test of the DDR module 4 is performed by the MCU control module 3.

[0012] The host computer 1 (PC end) as the "man-machine interaction entrance" and "data processing center" of the test system realizes test process control, data visualization and result analysis. The test task is completed through customized test software (such as a special program developed based on LabVIEW and Python), which supports the operator to configure test parameters (such as the test voltage range of the DDR module 4, the current sampling frequency, and the working timing of the SOC module 2), select test types (such as DDR current stability test and SOC communication link verification), and generate executable test task instructions. The host computer 1 provides a graphical user interface (GUI), receives the state data uploaded by the underlying module in real time (such as the power supply state of the SOC module 2 and the real-time current value of the DDR module 4), and displays it in the form of dynamic curves, data tables, and state indicator lights. The host computer 1 supports emergency operations (such as pausing the test and triggering the SOC power-off) to deal with abnormal scenarios. After the test is completed, the host computer 1 automatically analyzes the raw data (such as the current curve of the DDR in each working mode and the communication error rate of the SOC), calculates the key indicators (such as the average power consumption and current fluctuation range of the DDR), and generates a standardized test report (including data charts and fault positioning conclusions). It supports historical data storage and query to facilitate the tracing of test records.

[0013] The SOC module 2 (system chip U1001F) as the "hardware control brain" of the system realizes the cooperative work and communication link of the underlying module. The test logic execution receives the host computer 1 instructions converted by the MCU control module 3, analyzes them into specific hardware operation signals (such as timing signals to control the DDR module 4 to enter "standby / read / write / high-speed transmission" mode and configuration signals of its own communication interface), and drives the underlying hardware to complete the test action. The SOC module 2 integrates an SPI interface controller (matching the high-speed communication of the MCU control module 3) and a DDR controller (matching the storage interaction of the DDR module 4), which receives instructions from the MCU control module 3 and feeds back its own state on one hand, and establishes a data interaction link with the DDR module 4 to transfer control signals and temporary data required for testing on the other hand. The SOC module 2 has a built-in simple fault detection unit that can monitor its own power supply voltage and the integrity of the connection with the DDR module 4 (such as whether the data bus is disconnected), and immediately sends a fault signal to the MCU control module 3 through the SPI interface to trigger an upper-layer alarm if an abnormality is found.

[0014] The circuit design of the master SOC module 2 (U1001F) adopts a BGA496 package with a ball pitch of 0.65 mm. Power management: contains 12 independent power domains, the core voltage is 0.8V±3%, and the memory interface voltage is 1.2V±2%. The power network uses a multi-layer PCB design, and uses a π-type filter (10μH inductance + 2×100μF capacitor) to suppress noise and ensure that the voltage ripple is less than 2%. Clock system: a 40MHz crystal oscillator is used as the main clock source, and a 2666MHz DDR clock signal is generated through a PLL. The clock signal uses a differential pair design (CK_t / c), and the phase deviation is controlled within 5ps to reduce timing jitter. Heat dissipation design: 256 thermal vias (diameter 0.3mm) are arranged at the bottom of the SOC module 2, connected with the 2oz copper thick outer heat dissipation pad, to ensure that the junction temperature does not exceed 85°C under full load. Responsible for executing DDR algorithm function test, stress test and system initialization, and managing address / command signals through Fly-by topology.

[0015] The MCU control module 3 acts as an "intermediate bridge between the host computer 1 and the SOC module 2", and solves the communication protocol compatibility problem between different modules, and guarantees the safety of system power supply. Dual-interface communication and protocol conversion: UART asynchronous communication with the host computer 1: adopts standard UART protocol (supports baud rate 9600~115200bps, no parity / 1-bit stop bit), realizes low-rate and high-reliability instruction and state transmission (such as "start test" instruction issued by the host computer 1, "SOC power supply normal" state uploaded by the MCU control module 3); SPI high-speed communication with SOC: adopts SPI master-slave mode (MCU control module 3 as master, SOC as slave), clock frequency up to 10Mbps, meets the demand of fast transmission of large amount of data (such as real-time current sampling data of DDR module 4, test log of SOC); protocol conversion: automatically converts UART instruction frame of the host computer 1 (such as "0x01-start DDR test") into SPI instruction format recognizable by SOC, and vice versa, converts SPI feedback data of SOC (such as "0x80-DDR current 1.2A") into UART data for uploading, realizes cross-protocol compatibility; accurate control of SOC power supply: integrates power management unit (PMU), outputs high and low level signals through GPIO pin to control the power supply switch of the SOC module 2: power-on process: after receiving the "start SOC module 2" instruction of the host computer 1, supplies power to the SOC according to the preset time sequence (core voltage 3.3V first, then IO voltage 1.8V), and after the SOC module 2 initialization is completed and the "ready" signal is fed back, the test instruction is forwarded again; power-off process: when the test is completed or the "emergency power-off" instruction is received, first notify the SOC module 2 to save temporary data through SPI, and then cut off the power supply to avoid data loss or hardware damage caused by sudden power-off of the SOC module 2.

[0016] MCU control module 3 communicates with the host computer 1 (PC end) through the UART interface for asynchronous serial communication, with a transmission rate of 115200bps, a data format of 8-bit data, no parity bit, and 1-bit stop bit, to ensure real-time display of test status and results; at the same time, it communicates with the main control SOC module 2 (U1001F) through the SPI interface for high-speed data exchange, with a clock frequency of 10MHz and support for full-duplex mode. The MCU integrates a PMIC (power management integrated circuit), which configures the output voltage sequence through an I2C bus. For example, the SOC core power supply can be provided by a TPS65086182 chip with a power supply of 0.8V / 3A, and the DDR power supply can be provided by a TPS51200DRCR chip with a driving capacity of 1.2V / 6A, to realize accurate timing control (such as power-on / off period).

[0017] The MCU control module 3 has an integrated INA219 high-precision current sensor with a sampling resistance of 10 megaohms, supporting a 0-3.2A measurement range and a resolution of 100uA (microampere). It can monitor the read / write current, standby current, and sleep current of the DDR in real time, with a data update rate of 1kSPS, and upload the data to the host computer 1 through an ADC converter. The design of the MCU control module 3 ensures the safety and repeatability of the test process, such as automatically powering off after each test to avoid the risk of live operation.

[0018] The DDR module 4 (dynamic random access memory) as the test object has current characteristic testing: hardware connection is directly connected to the DDR test port of the MCU control module 3 through a dedicated DDR interface (including data bus, address bus, and control bus), and the MCU control module 3 sends a "switching working mode" control signal to the DDR module 4 through the interface and collects the power supply end current; the test scenario supports current testing under different working modes - standby mode (only maintaining data storage, low current), Active mode (preparing for read / write operation, medium current), and Burst read / write mode (high-speed continuous data transmission, highest current); the MCU control module 3 collects the power supply current of the DDR module 4 through a high-precision ADC (12-bit resolution, sampling rate 1kHz), which is fed back to the MCU in real time, and then forwarded to the host computer 1 through the MCU control module 3, for analyzing current stability and power consumption characteristics. As a data carrier: temporary storage: stores temporary data generated by the SOC module 2 during the test process (such as test instruction cache and state parameters of the DDR module 4), to avoid test interruption caused by insufficient built-in storage capacity of the SOC; hardware design adaptation: uses a DDR chip compatible with LPDDR5X (or corresponding test model), supports high-speed data read / write (the highest transmission rate meets the chip specifications), and reduces the influence of external interference on the accuracy of test data through impedance matching and power filter design.

[0019] The host computer 1 sends a "start DDR current test" instruction (including test mode, sampling frequency parameters) to the MCU control module 3 through UART; the MCU control module 3 converts the UART instruction into SPI format and issues it to the SOC module 2, and controls the SOC module 2 to power on and waits for it to be ready; after the SOC receives the instruction, it sends a "enter Burst read-write mode" control signal to the DDR module 4 through the controller in the DDR module 4; the DDR module 4 enters the target mode, and the MCU control module 3 collects real-time current data through the DDR test port; the MCU control module 3 sends the current data to the SOC through SPI (optionally: the SOC temporarily stores part of the data), and then the MCU control module 3 collects the data and uploads it to the host computer 1 through UART; the host computer 1 displays the current curve in real time, generates a current analysis report after the test is completed; after the test is completed, the host computer 1 issues a "stop test" instruction, the MCU control module 3 notifies the SOC to save data, and then cuts off the power supply of the SOC.

[0020] When starting the test, the MCU control module 3 controls the SOC module 2 to power on, and the whole system runs the test program; During the test, the MCU control module 3 tests the read-write current, standby current, and sleep current of the DDR module 4 monitored by the current sensor; After each test is completed, the MCU control module 3 controls the SOC module 2 to power off, so that the DDR module 4 is taken out without power, and the current data monitored by the current sensor is uploaded to the host computer 1 through the ADC converter.

[0021] Specifically, the test preparation phase: Step A: The host computer 1 initiates a test task configuration, and the operator completes the parameter setting in the GUI (such as the interface developed by LabVIEW): test type: DDR module 4 Burst read-write mode current test; key parameters: sampling frequency 1 kHz, test duration 5 minutes, current overrun threshold 1.5 A, SOC power supply timing (core voltage 3.3 V is powered on first, IO voltage 1.8 V is powered on after a delay of 50 ms); the software automatically generates an instruction frame (format: 0xAA

instruction code 0x01

mode 0x03

sampling rate 0x04

duration 0x1388

threshold 0x05DC

[0022] Step B: MCU receives instructions and verifies, starts SOC power-on. After receiving UART data, first check the frame header / frame tail and CRC (Cyclic Redundancy Check), confirm that the instruction is correct (if the verification fails, return 0xEE alarm to the host computer 1); trigger the power management unit (PMU): output high level through GPIO1 pin, control the SOC core voltage 3.3V power supply loop to turn on, and start the internal timer at the same time; after the timer delays for 50ms, GPIO2 pin outputs high level, turning on the SOC IO voltage 1.8V loop; send initialization instructions to SOC through SPI interface (MCU as host, SCLK clock 10Mbps, CS# pin pulled low): 0x01

SOC address 0x1001F

[0023] Step C: SOC initialization and feedback ready state, after power supply is stable (about 100ms), automatically complete the initialization of internal DDR controller and SPI interface controller; detect the core voltage (3.3V±5%) and IO voltage (1.8V±5%), and return the ready signal through the MISO pin of SPI after confirming no abnormality: 0x81

SOC state 0x00

state 0x01

[0024] MCU feedback to host computer 1 is ready, after receiving the 0x810x00 signal of SOC, send the preparation completion frame to host computer 1 through UART: 0xAA

state 0x00

[0025] Test execution phase (DDR current acquisition and real-time control): Step D: host computer 1 issues test start instruction, operator clicks "start test" button, software generates start instruction: 0xAA

instruction code 0x02

[0026] Step E: MCU forwards the instruction, SOC drives DDR into test mode, MCU receives the instruction and forwards it to SOC through SPI: 0x02

DDR control address 0x2000

mode 0x03

DDR status 0x00

[0027] Step F: MCU collects and caches DDR current, MCU starts internal 12-bit ADC (analog-to-digital converter), collects current signal of DDR power supply terminal (VCC=1.8V) through current sampling pin of DDR test port (with 0.1Ω sampling resistor in series); at 1kHz sampling frequency (collecting 1 sample every 1ms), convert analog current signal to digital quantity (such as 1.2A corresponding to digital quantity 0x04D2, quantization error ±0.5%); collect 100 data points (100ms) and cache them in MCU internal RAM (address 0x4000-0x40C7) to avoid frequent communication occupying bandwidth; judge current value in real time: if it exceeds 1.5A (corresponding to digital quantity 0x05DC), immediately trigger emergency process (see "abnormal handling").

[0028] Real-time upload and visualization are performed in the data interaction stage (parallel with the execution stage): Step G: MCU uploads data to SOC and host computer 1 in batches, MCU caches 100 current data points, first uploads to SOC through SPI (data frame format: 0xAA

data length 0x64

frame number 0x01

[0029] Step H: Host 1 real-time processing and display, after receiving UART data, check the frame number to avoid frame loss, if the frame is missing (such as missing 0x02 frame), send 0xAD

missing frame number

[0030] Test ending phase (stop and data archiving): Step I: Host 1 initiates a stop command, the test duration ends (5 minutes) or the user manually clicks "stop", the software sends a stop command: 0xAA

command code 0x03

[0031] Step J: Module cooperation stops testing and power off, after receiving the command, MCU sends 0x03

stop identifier 0x01

stop complete 0x00

[0032] Step K: Data aggregation and report generation, MCU reads the complete test data (0x2000-0x20C8) saved in DDR module 4 through the DDR test port, aggregates all sampling points (30000 points in total, 5 minutes x 60 seconds x 100 points / second); Calculate key indicators: average current 1.18A, maximum current 1.25A, fluctuation range ±0.05A, generate data aggregation frame and upload to host 1 through UART; After receiving, host 1 automatically generates a standardized test report (including current curve screenshot, key indicator table, test time, module status), saves to local path (such as D:\TestReports\20251205_DDR_Current_001.xlsx), and updates historical data query library.

[0033] MCU control module 3 integrates a current sensor, which monitors the read / write current, standby current and sleep current of DDR module 4 in real time, and uploads the current data monitored by the current sensor to host 1 through an ADC converter.

[0034] The host computer 1 initiates a test task configuration. In addition to the original parameters, the operating personnel additionally configures current monitoring parameters in the GUI: current monitoring type: DDR read-write current (range 0~2A, precision ±1mA), standby current (range 0~500mA, precision ±0.5mA), hibernation current (range 0~100mA, precision ±0.1mA); sensor filtering parameter: read-write current sampling filtering coefficient 0x03 (low filtering, priority response speed), standby / hibernation current filtering coefficient 0x08 (high filtering, priority stability); instruction frame adds a current configuration field, and the format is updated to: 0xAA

instruction code 0x01

mode 0x03

sampling rate 0x04

time length 0x1388

threshold 0x05DC

read-write range 0x02

standby range 0x0080

hibernation range 0x0014

filtering coefficient 0x0308

[0035] The MCU receives the instruction and verifies it, starts the SOC module 2 power-on (newly added current sensor initialization), the original verification logic remains unchanged, after verification, the integrated current sensor (such as model ACS712) is initialized preferentially: through the I2C interface (sensor address 0x48) configuration: write 0x01

read-write range configuration 0x02

standby range configuration 0x0080

hibernation range configuration 0x0014

filtering coefficient 0x0308

self-check instruction

[0036] The SOC module 2 initializes and feeds back the ready state (newly added DDR module 4 state associated with the sensor range). After initialization, in addition to the original voltage detection, the DDR initial state (standby mode) is additionally fed back. 0x81

SOC state 0x00

DDR initial state 0x01

switch to standby range

[0037] MCU transmits the instruction, and the SOC drives the DDR into the test mode (new state switching and range linkage): the original instruction transmission logic remains unchanged. When the SOC drives the DDR to switch the mode, the SOC synchronously feeds back the current state of the DDR to the MCU through the SPI: entering the burst read-write mode: feeding back 0x82

DDR state 0x00

current mode 0x02

DDR state 0x00

current mode 0x03

switch to read-write range

switch to sleep range

[0038] The MCU collects the DDR current and caches (replaced by the current sensor collection logic). The current sensor real-time monitors the DDR power supply loop current, converts the current signal into 0~3.3V analog voltage (for example, 1A corresponds to 1.65V, and 0.1A corresponds to 0.33V), and outputs to the ADC input pin (AIN0) of the MCU. The MCU starts the 12-bit ADC (sampling rate 1kHz), collects the analog voltage output by the sensor, and converts it into the actual current value according to the range: read-write mode: voltage value x (2A / 3.3V) -> for example, 1.98V corresponds to 1.2A (digital quantity 0x04D2); standby mode: voltage value x (500mA / 3.3V) -> for example, 0.66V corresponds to 100mA (digital quantity 0x0190); sleep mode: voltage value x (100mA / 3.3V) -> for example, 0.33V corresponds to 10mA (digital quantity 0x0032); when caching data, 1 byte of "current type identifier" is added before each data point: 0x02 (read-write current), 0x01 (standby current), and 0x03 (sleep current). The cache format becomes:

current type 1 byte

current value 2 bytes

[0039] The MCU uploads the data to the SOC and the host computer 1 (the data format adds type identifier), and the MCU uploads the data to the SOC in batches. The data frame format is updated to: 0xAA

data length 0x96

frame number 0x01

[0040] The host computer 1 processes and displays in real time (distinguishes multi-state current visualization), after receiving the data, analyzes the "current type identifier", and stores according to the type: read-write current: stored in Current_RW array, draw red dynamic curve; standby current: stored in Current_Standby array, draw blue dynamic curve; sleep current: stored in Current_Sleep array, draw green dynamic curve; GUI adds "current type switching" button, supports viewing a certain type of current curve alone, and simultaneously displays multi-type current statistical values (such as "read-write current average 1.18A, standby current average 95mA, sleep current average 8mA").

[0041] Preferably, the MCU control module 3 integrates a power management integrated circuit, and the power management integrated circuit configures an output voltage sequence through an I2C bus.

[0042] The I2C master device interface of the MCU has two specific pins, namely an SDA pin (corresponding to PA10) and an SCL pin (corresponding to PA9), and the two pins are directly connected to the I2C slave device interface of the voltage configuration register PMIC (specific model TITPS65987). In order to match the 1.8V IO level, a 1.8kΩ pull-up resistor is mounted on the I2C bus. This hardware connection mode is suitable for board-level interconnection scenarios, and the maximum communication distance supported is 10 centimeters.

[0043] The I2C bus communication rate adopts I2C fast mode, and the rate is 400kHz. This rate can meet the real-time requirements of voltage sequence configuration, and the transmission time of a single configuration instruction does not exceed 10 microseconds. The address format adopts a 7-bit slave device address, and the default address of the PMIC is 0x48. There is no read / write bit extension. When performing a read operation, 0x01 is connected after the address, and 0x00 is connected when performing a write operation. The transmission of the data frame follows a fixed sequence: first, the start condition (indicated by "S") is sent, then the combination of the slave device address and the read / write bit, after the PMIC returns the response (indicated by "ACK"), 1 byte of register address is sent, the response is waited again, then 2 bytes of configuration data (the high bits are in front during transmission) are transmitted, and after the response, the stop condition (indicated by "P") is sent.

[0044] In order to avoid configuration failure caused by bus interference, a timeout retransmission mechanism is set: after the MCU sends an I2C instruction, the timeout time for waiting for the PMIC response is 100 microseconds. If no response is received within the timeout, retransmission will be triggered, and the maximum retransmission is 3 times, with an interval of 50 microseconds each time. At the same time, the MCU integrates an I2C bus conflict detection unit. When detecting that the SDA or SCL line has a level anomaly (for example, multiple master devices simultaneously pull down the line), the bus will be immediately released, and the communication will be re-initiated after a delay of 1 millisecond, preventing data transmission disorder.

[0045] The voltage configuration register takes the TITPS65987 model as an example. The core voltage configuration register is mainly divided into three categories, namely, voltage setting register, enable control register and timing configuration register. The specific functions of each type of register are as follows: voltage setting register: including SOC_VCORE_SET (address 0x10), SOC_VIO_SET (address 0x11), DDR_VCORE_SET (address 0x20), DDR_VDDQ_SET (address 0x21). Among them, SOC_VCORE_SET is used to configure the core voltage (VCORE) of SOC, SOC_VIO_SET is used to configure the IO voltage (VIO) of SOC, DDR_VCORE_SET is used to configure the core voltage (VDDR) of DDR, and DDR_VDDQ_SET is used to configure the auxiliary voltage (VDDQ) of DDR. The data bit meaning of the four registers is consistent, all of which are bit15~bit4 representing 12-bit voltage code value, bit3~bit0 being reserved bits. Enable control register: including SOC_PWR_EN (address 0x12) and DDR_PWR_EN (address 0x22). SOC_PWR_EN is used to control the enable state and power-up sequence of SOC voltage, wherein bit1 corresponds to the enable of VCORE (1 represents enable), bit0 corresponds to the enable of VIO (1 represents enable), and bit7~bit2 are used to configure the power-up interval, with a unit of 10 milliseconds; the function of DDR_PWR_EN is similar to that of SOC_PWR_EN, bit1 corresponds to the enable of VDDR (1 represents enable), bit0 corresponds to the enable of VDDQ (1 represents enable), and bit7~bit2 are also used to configure the power-up interval, with a unit of 10 milliseconds. Timing configuration related monitoring register: VOLT_MONITOR (address 0x01), mainly used to read the actual output value of each voltage to facilitate configuration verification, bit15~bit8 of the data bit represent the measured value of VCORE, bit7~bit0 represent the measured value of VIO, and the second byte of the register corresponds to the measured values of VDDR and VDDQ.

[0046] The voltage configuration register PMIC realizes voltage output through a 12-bit DAC (digital-to-analog converter), and the conversion formula of the actual output voltage and the voltage code value is: actual voltage (unit: V) = code value x voltage step. The voltage step is determined by the reference voltage inside the PMIC, and the reference voltage of TITPS65987 is 1.25V. The code range corresponding to the 12-bit DAC is 0~4095, and thus the basic step is about 0.305mV. However, the step of different voltage domains can be adjusted through the configuration register. In the system: the SOC voltage domain (including VCORE and VIO): the step is set to 1mV, and the step is realized by configuring the DAC gain through the 0x0F register. At this time, the code value is equal to the millivolt number of the target voltage. For example, the target voltage is 3.3V (i.e. 3300mV), and the corresponding code value is 0xD05 in hexadecimal, and the data transmitted to the register is 0x0D (high bit) and 0x05 (low bit). The DDR voltage domain (including VDDR and VDDQ): in order to adapt to the low-voltage high-precision requirement, the step is set to 0.5mV, and at this time the code value is equal to twice the millivolt number of the target voltage. For example, the target voltage is 1.1V (i.e. 1100mV), and the code value is 1100x2=2200, which corresponds to 0x8C8 in hexadecimal, and the data transmitted to the register is 0x08 (high bit) and 0xC8 (low bit) (0x0458 mentioned in the previous document is a simplified expression, which is the actual code logic here).

[0047] The I2C instruction sequence of the SOC module 2 voltage sequence configuration is as follows: first, the MCU control module 3 sends the first I2C write instruction to the voltage configuration register PMIC, the instruction sequence is the start condition, the slave address 0x48+write operation identifier 0x00, the response, the register address 0x10, the response, the configuration data 0x0D and 0x05, the response, and the stop condition. The instruction is used to configure the VCORE voltage of the SOC to be 3.3V, and after sending, the PMIC returns the response to confirm the reception. Then, the MCU sends the second write instruction, the register address is changed to 0x11, and the configuration data is changed to 0x07 and 0x08, which is used to configure the VIO voltage of the SOC to be 1.8V (1800mV corresponds to the code value 0x708 in hexadecimal), and the response of the PMIC is also received. Then, the MCU control module 3 sends the third write instruction, the register address is 0x12, and the configuration data is 0x00 and 0x03, wherein bit1 and bit0 are both set to 1, respectively enabling VCORE and VIO, and bits 7~2 are set to 0 (the power-on interval is controlled by the internal timer of the MCU control module 3). After the voltage configuration register PMIC responds, the MCU control module 3 starts the internal timer and sets a 100ms delay, waits for the subsequent power supply operation of the DDR module 4, and the timer will send a delay completion signal to the MCU control module 3 after counting is completed.

[0048] After receiving the delayed completion signal of the timer, the MCU control module 3 starts to configure the voltage of the DDR module 4. The register address of the first write instruction is 0x20, and the configuration data is 0x08 and 0xC8, which is used to configure the VDDR voltage of the DDR module 4 to 1.1V (1100mVx2=2200, corresponding to the encoding value 0x8C8), and the voltage configuration register PMIC returns a response. The register address of the second write instruction is 0x21, and the configuration data is 0x07 and 0x08, which is used to configure the VDDQ voltage of the DDR to 0.9V (900mVx2=1800, corresponding to the encoding value 0x708), and a response is also received. Finally, the MCU control module 3 sends the third write instruction, the register address is 0x22, and the configuration data is 0x00 and 0x03, which enables VDDR and VDDQ, and the PMIC responds to complete the voltage configuration of the DDR module 4.

[0049] The power-up sequence control is realized by a timer inside the MCU control module 3, and the timer accuracy is 1ms. When the MCU sends the SOC voltage enable instruction to the voltage configuration register PMIC, the timer starts counting immediately, and when the count reaches 100ms, the DDR module 4 voltage enable instruction is sent to the voltage configuration register PMIC. This delayed design can avoid the abnormal SOC initialization caused by the pre-power-on of the DDR module 4. The voltage rise slope control is realized by the voltage slope control unit integrated in the PMIC, which can be configured through the 0x02 register. In the system, the VCORE voltage rise slope of the SOC module 2 is set to 50mV / ms, which needs 66ms to rise from 0V to 3.3V; the VDDR voltage rise slope of the DDR is set to 30mV / ms, which needs 37ms to rise from 0V to 1.1V. Such slope setting can prevent the surge current caused by the sudden rise of voltage.

[0050] After voltage enable, MCU control module 3 needs to wait 200 milliseconds to ensure stable voltage output. Then, it reads the PMIC's VOLT_MONITOR register (address 0x01) via I2C read instructions. The read instruction sequence is: start condition, slave device address 0x48 + read operation flag 0x01, acknowledge, register address 0x01, acknowledge, receive high byte data, acknowledge, receive low byte data, NACK, stop condition. After reading the data, it is parsed. For example, if the read register data is 0x0D, 0x02, 0x08, 0xC7, it means that the measured value of VCORE of SOC module 2 is 0x0D02 (corresponding to 3330mV, i.e., 3.33V), which is within the allowable error range of ±5% (3.135V~3.465V) and is qualified. The measured value of VDDR of DDR is 0x08C7 (corresponding to 2247, 2247×0.5mV=1123.5mV, i.e., 1.1235V), which is within the allowable error range of ±3% (1.067V~1.133V) and is also qualified. If the measured value exceeds the corresponding error threshold, MCU control module 3 will send an I2C write command to reconfigure, retrying a maximum of 2 times. If it still fails, it will report "PMIC voltage configuration abnormal" to host computer 1.

[0051] After sending a voltage configuration command to a configuration register, MCU control module 3 immediately reads back the contents of that register via an I2C read command to confirm that the written coded value matches the target value. For example, after writing the coded value 0x0D05 corresponding to 3.3V to register 0x10 (SOC_VCORE_SET), and then reading back register 0x10, if the read result is 0x0D and 0x05, which matches the target code, then the configuration is successful; if they do not match, it indicates an error in the I2C command transmission, and the configuration command needs to be resent to avoid voltage configuration deviation due to transmission errors.

[0052] When the SOC feeds back to the MCU that the DDR module 4 enters the sleep mode, the MCU control module 3 needs to dynamically adjust the voltage of the DDR module 4 through the I2C instruction. First, the write instruction is sent to configure the VDDR voltage to be 0.8V: the register address is 0x20, the configuration data is 0x06 and 0x40, wherein 0.8V corresponds to 800mV, and the encoding value is 800x2=1600 (hexadecimal 0x640). Then, the write instruction is sent to configure the VDDQ voltage to be 0.75V: the register address is 0x21, the configuration data is 0x05 and 0xDC, 0.75V corresponds to 750mV, and the encoding value is 750x2=1500 (hexadecimal 0x5DC). After the adjustment is completed, the VOLT_MONITOR register (0x01) is read through the read instruction, and it is confirmed that the measured value of VDDR is within the range of 0.776V~0.824V (±3% error allowed range), so as to ensure that the adjusted voltage meets the requirements of the sleep mode.

[0053] If it is necessary to test the low-power performance of the DDR module 4, the host computer 1 can issue a corresponding instruction, and the MCU control module 3 receives the instruction and configures a lower voltage sequence through the I2C instruction. For the VCORE voltage of the SOC, it is reduced to 3.0V (corresponding to 3000mV), and the data written into the 0x10 register is 0x0B and 0xB8 (3000mV corresponds to the encoding value of hexadecimal 0xBB8). For the VDDR voltage of the DDR, it is reduced to 0.7V (corresponding to 700mV), and the data written into the 0x20 register is 0x05 and 0x38 (700mVx2=1400, corresponding to hexadecimal 0x538). At the same time, the power-on timing is adjusted, and the power-on interval of the SOC module 2 and the DDR module 4 is shortened from 100 milliseconds to 50 milliseconds, which is realized by modifying the counting time of the internal timer of the MCU control module 3, so as to adapt to the special requirements of the low-power test.

[0054] Preferably, the power management integrated circuit is provided with an MT6319 multiphase controller, the SOC module 2 transmits and starts the MT6319 multiphase controller through the SPI bus, and configures various parameters, wherein the various parameters at least include an output voltage, a switching timing, and a protection threshold value, and the power-on timing is executed. The MT6319 multiphase controller sequentially turns on each power supply for supplying at least the core, the memory, and the I / O of the SOC module 2 in a preset order. When the system is running, the SOC module 2 dynamically adjusts the output voltage (DVFS) of the MT6319 multiphase controller through the SPI command transmitted through the SPI bus according to the load condition, so as to balance the performance and the power consumption.

[0055] MT6319 as a multi-phase controller inside the PMIC, using SPI slave device mode, SOC module 2 as SPI master device, connected by 4 special pins: SOC SCLK (clock pin, such as PC10) provides synchronous clock, MOSI (master send slave receive pin, such as PC12) transmits instructions and configuration data, MISO (master receive slave send pin, such as PC11) feedbacks the state and measured data of MT6319 multi-phase controller, CS# (chip select pin, such as PC9) is used to enable / disable MT6319 multi-phase controller (low active). The bus has no additional pull-up resistor, supports short-distance transmission (maximum distance 5 cm) at the board level, and meets the requirements of multi-phase controller for signal synchronization.

[0056] The communication rate is set to 1 MHz, taking into account real-time performance (single instruction transmission time ≤10us (microsecond)) and anti-interference ability (avoiding signal distortion caused by high-speed clock). Data transmission uses "high bit first (MSB first)" format, clock polarity (CPOL) is set to 0 (SCLK is low during idle), clock phase (CPHA) is set to 1 (data is sampled at the second edge of SCLK), which meets the SPI interface timing requirements of MT6319. The instruction frame structure is fixed at 16 bits: the first 4 bits are instruction type (such as 0x01 for start, 0x02 for parameter configuration), and the last 12 bits are data field (including parameter encoding or state information). When transmitting, CS# needs to be pulled low first, then 16-bit data is sent after SCLK synchronization, and CS# is pulled high after transmission to complete one communication.

[0057] To ensure reliable instruction transmission, MT6319 will return an 8-bit confirmation code through the MISO pin after receiving each instruction sent by the SOC: 0x00 indicates that the instruction is received successfully and effectively, 0x01 indicates that the instruction format is incorrect, and 0x02 indicates that the parameter is out of range. After the SOC sends the instruction, it needs to wait for 1us (MT6319 response delay) to read the confirmation code of the MISO pin. If it is 0x01 or 0x02, the instruction needs to be re-sent (up to 2 retries), with a 5us interval between retries to avoid configuration failure due to single transmission error.

[0058] During the initial power-on of the system, the PMIC main power first provides basic power supply (such as 3.3V) for MT6319, and MT6319 enters standby state. At this time, the SOC starts the controller through SPI: first pull down CS# to enable MT6319, send 16-bit start instruction (0x0100, the first 4 bits 0x01 are start instruction, the last 12 bits 0x00 are default initialization parameters), and after MISO returns 0x00 confirmation code, pull up CS# to complete the start. After MT6319 is started, it automatically enters the "parameter configuration ready" state, waiting for the SOC to issue specific power supply parameters.

[0059] SPI configuration of key parameters (output voltage, switch timing, protection threshold): Output voltage configuration: SOC configures voltage for three core power domains of SOC (core VCORE, memory VMEM, I / O VIO) respectively. MT6319 multi-phase controller uses 10-bit DAC to encode and control output voltage, with a step of 1 mV, and the encoding value = target voltage (mV). For example, when configuring VCORE as 1.0V (1000mV), SOC sends instruction 0x023E8 (the first 4 bits 0x02 are parameter configuration, the last 10 bits 0x3E8 are the hexadecimal encoding of 1000, and the last 2 bits are reserved); 0x024B0 is sent to configure VMEM as 1.2V (1200mV), and 0x02708 is sent to configure VIO as 1.8V (1800mV). After sending the voltage configuration instruction each time, SOC needs to read the MISO feedback of MT6319 to confirm that the voltage encoding has been correctly written to the internal register.

[0060] Switch timing configuration: In order to avoid the inrush current generated by the simultaneous power-on of multiple power domains, SOC sets the start interval of each power supply through SPI. The instruction format is 0x03XXY (0x03 is the timing configuration instruction, XX is the interval time encoding of the previous power supply and the current power supply, and Y is the power domain identifier: 1 = VCORE, 2 = VMEM, 3 = VIO). For example, set VCORE to start and delay 200us to start VMEM, send instruction 0x03C82 (XX=0xC8 corresponds to 200us, Y=2 corresponds to VMEM); set VMEM to start and delay 150us to start VIO, send instruction 0x03963 (XX=0x96 corresponds to 150us, Y=3 corresponds to VIO). MT6319 receives and stores the timing parameters to the internal timing controller for subsequent power-on execution.

[0061] Protection threshold configuration: Set the overvoltage, overcurrent, and overheat protection thresholds for each power domain. The overvoltage protection threshold is set to 120% of the target voltage, for example, VCORE=1.0V, the overvoltage threshold is 1.2V (1200mV), and the configuration instruction is 0x043E81 (0x04 is the protection configuration instruction, 0x3E8 is the 1200mV encoding, and 1 is the VCORE identifier); the overcurrent protection threshold is set according to the current level of the power domain, the maximum current of VCORE is 3A, the overcurrent threshold is set to 3.6A, the encoding is 0x0E10 (corresponding to 3600mA), and the instruction is 0x050E101; the overheat protection threshold is uniformly set to 125℃, the encoding is 0x7D, and the instruction is 0x067D (0x06 is the temperature protection instruction). After configuration is completed, MT6319 monitors each parameter in real time, and automatically triggers protection (such as turning off the corresponding power supply) when the threshold is exceeded and sends an alarm signal through MISO.

[0062] After SOC completes all parameter configurations, a power-on execution instruction 0x0700 (0x07 is a power-on instruction, and 0x00 is an execution identifier) is sent, and MT6319 receives the power-on execution instruction 0x0700 and starts internal timing logic, and each power supply domain is started in a preset order: in a first step, a core power supply VCORE is first started, an internal DAC outputs a voltage from 0V to a target value 1.0V at a slope of 50mV / us, and after the voltage is stabilized (about 20us), a "VCORE ready" signal (0x0801) is sent to the SOC through MISO; In a third step, after a delay of 150us, an I / O power supply VIO is started, and the slope is increased to 1.8V, and after the voltage is stabilized, a "VIO ready" signal (0x0803) is sent. The entire power-on process takes about 400us, and after the SOC receives all the "ready" signals, it is confirmed that MT6319 has completed the overall power supply of the SOC, and the subsequent system initialization can be started.

[0063] When MT6319 powers on each power supply domain, the feedback adjustment mechanism of the multi-phase Buck circuit is used to maintain voltage stability: for example, when VCORE is powered on, an internal current sampling resistor monitors the output current in real time, and if the voltage decreases (such as to 0.98V) due to load fluctuations, the feedback circuit immediately adjusts the PWM duty cycle to increase the output voltage to 1.0V. At the same time, the voltage rise slope is controlled to avoid inductance current spikes caused by too fast slope (the maximum spike current is controlled to be within 1.5 times the rated current), and the stability of the SOC power supply is ensured.

[0064] When the system is running, the SOC monitors the core operation load (such as CPU usage), memory bandwidth occupancy, and core temperature in real time through internal sensors: when the load rate exceeds 80% for 50ms (high load scenario), or the temperature exceeds 85℃ (power consumption needs to be reduced), or the load rate is less than 30% for 100ms (low load scenario), the DVFS adjustment logic is triggered to determine the target output voltage of MT6319. For example, VCORE needs to be increased to enhance performance in a high load scenario, and VCORE needs to be reduced to save power consumption in a low load scenario.

[0065] The SOC sends a dynamic adjustment instruction to the MT6319 through the SPI according to the load judgment result. Taking the case that the VCORE is raised from 1.0V to 1.2V in a high load as an example: the SOC sends the instruction 0x094B01 (0x09 is a DVFS adjustment instruction, 0x4B0 is 1200mV code, and 1 is the VCORE identifier), and the MT6319 adjusts the internal DAC immediately after receiving the instruction, and raises the VCORE voltage to 1.2V at a slope of 30mV / us (to avoid the voltage sudden rise affecting the system operation), and feeds back the current voltage value (such as 0x0A4A0 representing the current voltage 1184mV) in real time through the MISO during the adjustment.

[0066] When the voltage is stabilized at 1.2V, the MT6319 sends an "adjustment completion" signal (0x0B00), and the SOC completes the DVFS adjustment after confirmation.

[0067] After each DVFS adjustment is completed, the SOC reads the measured voltage register of the MT6319 through the SPI (instruction 0x0C01, 0x0C is a read instruction, and 01 is the VCORE identifier), and confirms that the deviation between the measured voltage and the target voltage is within ±2% (for example, when the target is 1.2V, the measured value needs to be between 1.176V and 1.224V). If the deviation exceeds the range, the SOC re-sends the adjustment instruction (with a maximum of 2 retries), and if the abnormality still exists, an alarm is triggered and the system is switched to a safe voltage (such as 1.0V) to ensure stable operation of the system.

[0068] The embodiment realizes accurate transmission of full-link instructions and data through hierarchical design, characteristics of each interface adaptation module, retry and verification mechanism, and forms a communication closed loop with "no loss and no disorder"; accurately configures the SOC and DDR voltage in different domains, dynamically adjusts the voltage according to the needs through DVFS to balance performance and power consumption, strictly controls the power-on sequence and slope, and executes the standard power-off sequence to ensure power supply safety; high-precision monitoring of DDR multi-state current, real-time verification of power supply parameters, structured processing of test data and generation of comparison reports provide accurate and readable basis for test evaluation; hardware-level rapid protection, software-level fault tolerance, and multi-module collaborative feedback greatly reduce the risk of failure.

[0069] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0070] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0071] In addition, each function unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist alone physically, or two or more units can be integrated into a unit. The integrated unit can be implemented in a form of hardware, or in a form of software functional unit.

[0072] The above are only some embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation made by using the contents of the present application specification and drawings, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method of hardware optimization for a test project, the method comprising: The method comprises: The host computer is a PC terminal; The SOC module is a system on chip, and the SOC module is a control core of the whole test system and realizes communication of the test system; The MCU control module performs asynchronous serial communication with the host computer through a UART interface, simultaneously performs high-speed data exchange with the master SOC module through an SPI interface, and realizes communication between the host computer and the SOC module through the MCU control module, and controls on-off of the SOC module; The DDR module is connected with the DDR end of the MCU control module, and the MCU control module tests current of the DDR module.

2. The method for hardware optimization of test programs according to claim 1, wherein, The MCU control module is integrated with a current sensor, which monitors read-write current, standby current and sleep current of the DDR module in real time, and uploads current data monitored by the current sensor to the host computer through an ADC converter.

3. The method of claim 2, wherein, The MCU control module is integrated with a power management integrated circuit, and the power management integrated circuit configures output voltage sequences through an I2C bus.

4. The hardware optimization method for test programs according to claim 3, wherein, The power management integrated circuit is provided with an MT6319 multiphase controller, the SOC module transmits and starts the MT6319 multiphase controller through an SPI bus, and configures parameters, wherein the parameters at least include output voltage, switching time sequence and protection threshold, and executes power-on time sequence: The MT6319 multiphase controller sequentially starts each power supply of the SOC module at least including core, memory and I / O according to a preset order; When the system runs, the SOC module dynamically adjusts output voltage of the MT6319 multiphase controller through an SPI command transmitted through the SPI bus according to load conditions, so as to balance performance and power consumption.

5. The method of claim 4, wherein, The step that the MCU control module is integrated with a current sensor, which monitors read-write current, standby current and sleep current of the DDR module in real time, and uploads current data monitored by the current sensor to the host computer through an ADC converter comprises: When starting the test, the MCU control module controls the SOC module to be powered on, and the whole system runs a test program; In the test process, the MCU control module tests read-write current, standby current and sleep current of the DDR module monitored by the current sensor; After each test is completed, the MCU control module controls the SOC module to be powered off, so that the DDR module is taken and placed without electricity, and current data monitored by the current sensor is uploaded to the host computer through the ADC converter.

6. The hardware optimization method for test programs according to claim 5, wherein, The step that when starting the test, the MCU control module controls the SOC module to be powered on, and the whole system runs a test program comprises: The host computer initiates a test task configuration, and an operator completes parameter setting in a GUI interface; The MCU control module receives instructions and verifies, and starts the SOC module to be powered on; The SOC module is initialized and feeds back a ready state; The MCU control module feeds back preparation completion to the host computer, and after receiving a signal of the SOC module, sends a preparation completion frame to the host computer through the UART.

7. The hardware optimization method for test programs according to claim 6, wherein, The step of testing the read-write current, standby current and sleep current of the DDR module monitored by the MCU control module through the current sensor during the testing process comprises: When the host computer issues a test start instruction, a "start test" button is opened and a start instruction is generated, and the start instruction is sent to the MCU control module through UART; After the MCU control module receives the start instruction, the start instruction is forwarded to the SOC module through the SPI bus, and the SOC module drives the DDR module to enter the test mode; The start instruction is parsed by the SOC module, and a timing signal is generated by the internal DDR controller of the SOC module, which is sent to the DDR module through the DDR bus and controls the DDR module to enter the Burst read-write mode, and the read-write current of the DDR module is collected.

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