DELTA-SIGMA sensing device

Abstract

A Delta-sigma (delta-sigma) device comprises a transducer (2) and a delta-sigma modulator (3), where the transducer (2) comprises: a sensing stage (100) for detecting a property of an environment (106) and an interface stage (101), where the sensing stage (100) is configured to detect the property of the environment (106); and the delta-sigma modulator (3) comprises: an input stage, a feed-forward low-pass filtering stage (102), an analog-to-digital encoder (104), an unfiltered in-modulator feedback path and a low-pass filtered in-modulator feedback path; wherein the input stage is connected to the interface stage (101) and comprises two subtraction stages (113, 114) of the input stage for receiving an unfiltered in-modulator feedback signal (109) and a low-pass filtered in-modulator feedback signal (110) and subtracting the unfiltered in-modulator feedback signal (109) and the low-pass filtered in-modulator feedback signal (110) from the sum of the one or more input converted signals (108), to obtain a delta error signal (111); the analog-to-digital encoder (104) converts the filtered delta error signal into a digital output signal dout (t) (112); the feedback path in the unfiltered modulator converts the dout (t) (112) into a feedback signal (109) in the unfiltered modulator; the low-pass filtering modulator internal feedback path converts the dout (t) (112) into a low-pass filtering modulator internal feedback signal (110).

Description

Technical Field

[0001] The purpose of this invention is to provide a Δ-Σ sensing device with background signal attenuation and distributed coding. Background Technology

[0002] Sensor technology plays a vital role in various industries, including environmental monitoring, automotive, aerospace, medical, and consumer electronics. These sensors are designed to measure and monitor diverse physical (such as pressure, temperature, and humidity) and chemical (such as analyte concentration) parameters, providing fundamental data for a wide range of applications. To enable sensors to communicate with other devices to perform further calculations, they are often "intelligentized" by incorporating integrated circuits (ICs) that process the sensor signals and convert them into a digital format readable by external user devices.

[0003] Factors such as drift and offset often hinder the achievement of high precision and accuracy in smart sensing devices. Drift refers to a slow, continuous change in the sensor's output over time, independent of the input signal of interest. This can be attributed to aging, contamination of the sensing surface, and other environmental factors such as thermal, mechanical, or electrical stress. Offset, on the other hand, is a constant component in the sensor's output signal, independent of the input value. This is typically caused by manufacturing defects or other external influences. Inaccurate measurements can lead to flawed decisions, reduced system efficiency, and, in some cases, serious malfunctions.

[0004] In practice, calibrating these two factors is often necessary to ensure that sensing devices perform within operational requirements. Calibration requirements and energy consumption are key challenges to device autonomy. The third aspect—miniaturization—increases autonomy, a crucial feature enabling the widespread use of devices. Recent advances in sensor technology have made it possible to manufacture physical and chemical sensors at the sub-micron level. However, because the amplitude of the converted signal decreases with increasing size, shrinking the size exacerbates sensitivity to the aforementioned drift and offset effects.

[0005] Different strategies for compensating for drift have been described in the prior art: a common strategy is to subtract the cancellation term from the sensor output during the calibration phase, but this strategy is ineffective for long-term monitoring because drift varies due to environmental determinants. Other popular techniques, such as using thresholds to distinguish between signal variation and drift, rely on the signal being greater than the drift, but this is not always the case. Performing differential measurements from a reference sensor requires electrical matching and drift similarity between the two, which may be infeasible due to inherent manufacturing variability.

[0006] The proposed circuitry approach for eliminating or offsetting offsets involves applying a bias on the device and reconfiguring it within a limited range during a separate calibration phase. Employing machine learning algorithms and artificial intelligence (AI) in sensor systems also helps detect and compensate for drift and offset. By analyzing historical sensor data and identifying patterns, these algorithms can predict and correct the resulting errors in real time, leading to more accurate and reliable measurements. However, due to their complexity, embedding AI models in devices typically results in a significant increase in their dimensionality and energy budget.

[0007] In this context, electrochemical microsensors manufactured using semiconductor technology offer advantages such as miniaturization, large-scale manufacturing, and ease of integration with complementary metal-oxide-semiconductor (CMOS) circuits, serving as intelligent sensing devices for embedded signal processing.

[0008] In fact, Figure 1 The illustrated amperometric sensor family is particularly attractive because its simple three-microelectrode cell structure allows for the evaluation of redox reactions in solution at the target analyte potential (VRW) between the reference electrode (RE) and the working electrode (WE). Under potentiostatic operation (i.e., ensuring a constant voltage at VRW and zero current through RE), the counter electrode (CE) provides all the current required for the electrochemical reactions at the WE surface. Therefore, the undesirable voltage drop at VRW at RE can be effectively avoided.

[0009] In this configuration, the electrode-electrolyte interface is typically modeled as Figure 1 A small-signal circuit, where i sens The required measurement is the change in CE-WE current, and R... ct C d1 and R s These represent charge transfer resistance, double-layer capacitance, and electrolyte solution resistance, respectively.

[0010] Figure 2A field-effect transistor (FET) sensor is illustrated, which is easily miniaturized and replicated as a sensor array in semiconductor technology. In standard CMOS technology, the FET can be integrated as a metal-oxide-semiconductor transistor, with the metal connection at the gate replaced by a liquid. The liquid contains the target analyte to be measured, which interacts with a gate insulator that serves as the sensing surface. Depending on the sensitivity to each analyte, changes in analyte concentration are converted into potential changes at the surface of the gate insulator. These electrical changes in the gate potential can then be read out in the electrical domain using electronic circuitry.

[0011] In the case of FET electrochemical sensors fabricated using standard CMOS technology, the FET can be modeled as... Figure 2 The circuit, where V sens Due to chemical contribution V chem The change in potential measured by the change in C sens This represents the sensing capacitance generated due to the dielectric sensing film.

[0012] Despite the advantages mentioned above, the practical use of electrochemical microsensors is limited by phenomena such as fouling and parasitic currents, or trapped charges (e.g., drift and offset components) on the sensing surface. These phenomena introduce variability between sensors and can severely impair the dynamic range and accuracy of transient measurements.

[0013] For small signals and long-term measurements, drift becomes particularly problematic because identifying the signal across a moving baseline can be difficult. Adding the offset component, the sensor output can be driven outside the analog-to-digital converter (ADC) input range and saturate during sensor readout. This also means the ADC needs to cover a wide input range, which increases quantization noise.

[0014] A classic solution for integrating a potentiostat-ammeter readout in CMOS technology employs an operational amplifier-based potentiostat circuit that implements a negative feedback loop for the collector-emitter current (CE) to control the voltage-to-motor (VRW). The resulting sensor current can then be converted to a voltage and transformed into the digital domain via a pulse width modulator (PWM) or pulse density modulator (PDM).

[0015] Recent efforts have pointed towards integrating both voltage regulator and ADC functions into a single circuit block using Δ-Σ modulators. An interesting concept related to this is the so-called sensor in a loop: reuse... Figure 1The sensor dynamics shown are used as a feedforward filter stage for quantization noise shaping within a Δ-Σ modulator with discrete-time or continuous-time feedback. In addition to the significant advantages of saving circuit power and area, reusing the sensor as a continuous-time feedforward filter allows its anti-aliasing cut-off frequency to automatically adapt to the sensor's inherent bandwidth.

[0016] In the case of field-effect transistor (FET) sensors, the common approach is to use the transistor as a voltage follower. Recent circuits employ current-mode readout devices, which facilitate direct filtering and the use of Δ-Σ modulation schemes, similar to those previously described for ampere-type sensors.

[0017] To overcome sensor offset and drift to some extent, on-chip and off-chip compensation methods have been proposed. However, previous methods have not addressed issues such as how to monitor under long-term drift or offset interference, which may have a higher intensity than the signal of interest and may be affected by evolving environmental factors. This is the case for commercial applications such as environmental monitoring or wearable chemical sensing, where the widespread adoption of these analytical systems remains limited, primarily due to the non-ideal nature of sensors and the limited deployment of these devices in terms of compactness and energy autonomy. Summary of the Invention

[0018] The Δ-Σ sensing device of the present invention has a built-in adaptive pulse modulation code for providing attenuation of sensor bias, analog-to-digital conversion, and unwanted background sensor signals (e.g., DC offset, drift) located outside the frequency band of interest.

[0019] The device includes one or more transducers and one or more delta-Σ modulators. First, each transducer includes a sensing stage for detecting environmental properties (such as temperature, humidity, and analyte concentration) and converting them into an electrical input signal. Each transducer also includes an interface stage connected to the sensing stage, which receives the electrical input signal, amplifies the signal for further processing, and outputs the amplified input transducer signal to one or more delta-Σ modulators.

[0020] Secondly, each Δ-Σ modulator includes an input stage connected to the interface stage, configured to receive feedback signals from the filter modulator and low-pass filter modulator, and subtract the feedback signals from the filter modulator and low-pass filter modulator from the sum of one or more amplified input transducer signals to obtain the Δ error signal.

[0021] Following the input stage, each modulator includes a feedforward low-pass filter stage and an analog-to-digital encoder. The feedforward low-pass filter stage filters the Δ error signal to generate a filtered Δ error signal. The analog-to-digital encoder, located after the feedforward low-pass filter stage, converts the filtered Δ error signal into a digital output signal d. out (t).

[0022] Between the analog-to-digital encoder and the input stage, the modulator includes an unfiltered modulator internal feedback path and a low-pass filtered modulator internal feedback path, wherein the unfiltered modulator internal feedback path will d out (t) is converted to the unfiltered modulator feedback signal. The feedback path in the low-pass filter modulator is between the analog-to-digital encoder and the input stage, which will convert d out (t) is converted into the feedback signal within the low-pass filter modulator.

[0023] With respect to the current level of technology, this invention provides: (i) Tunable compression of interference frequency components to increase dynamic range, readout resolution, and energy efficiency; and (ii) Distributed pulse modulation coding to increase the maximum total encoder sampling rate and effectively model the correlation between input signals converted by the sensor.

[0024] The Δ-Σ device of the present invention is characterized in that it comprises one or more transducers and one or more Δ-Σ modulators, wherein each transducer comprises: - Sensing stage, used to detect environmental X in The (t) attribute is configured to convert it into an electrical input signal, and - An interface level, which connects to the sensing level and is configured to receive electrical input signals, amplify the electrical input signals, and send the amplified input transducer signals to one or more Δ-Σ modulators. And each Δ-Σ modulator includes: - Input stage, connected to the interface stage, includes two subtraction stages and is configured to receive the feedback signal within the unfiltered modulator and the feedback signal within the low-pass filter modulator, and subtract the feedback signals from the low-pass filter modulator from the sum of one or more amplified input conversion signals to obtain the Δ error signal. - Feedforward low-pass filter stage, which is located after the two subtraction stages of the input stage, is configured to filter the Δ error signal to generate the filtered Δ error signal; - An analog-to-digital encoder, located after the feedforward low-pass filter stage, converts the filtered Δ error signal into a digital output signal d. out (t), - An unfiltered modulator feedback path, comprising one or more first digital-to-analog converters located between the analog-to-digital encoder and the first of two subtraction stages of the input stage, will d out (t) is converted into the feedback signal within the unfiltered modulator, and - A feedback path within the low-pass filter modulator, comprising a feedback low-pass filter stage and one or more second digital-to-analog converters, wherein one or more second digital-to-analog converters are located between the second of two subtraction stages of the analog-to-digital encoder and the input stage, and d out (t) is converted into the feedback signal within the low-pass filter modulator; - Furthermore, the cutoff frequency of the feedback low-pass filter stage is set between the range of the background signal component and the range of the signal component of interest.

[0025] Therefore, the feedback low-pass filter stage is configured to allow background signal components to pass while suppressing the signal of interest. Since the feedback low-pass filter stage subtracts from the amplified input transducer signal, it acts as a high-pass filter to subtract low-frequency background signals.

[0026] Preferably, the cutoff frequency of the feedback low-pass filter stage is set to be higher than the background signal component and lower than the signal component of interest.

[0027] In some embodiments, it is not possible to select a cutoff frequency that allows background signal components to pass while suppressing all signals of interest. Therefore, the background signal components cannot be completely filtered. In those cases, a compromise solution is employed, where the selected cutoff frequency blocks some background signal components and / or allows some signals of interest to pass.

[0028] Preferably, the background signal is drift and / or offset.

[0029] Each transducer can be connected to a single Δ-Σ modulator or more than one Δ-Σ modulator.

[0030] The device of the present invention may further include one or more transducers and two or more Δ-Σ modulators, and wherein the device further includes multiple unfiltered inter-modulator feedback paths, each path including one or more third digital-to-analog converters connected to the d-axis of each Δ-Σ modulator. out (t) and is configured to d out (t) is converted into multiple unfiltered inter-modulator feedback signals, wherein the device includes an additional subtraction stage located before the feedforward low-pass filter stage, the additional subtraction stage being configured to receive the unfiltered inter-modulator feedback signal of each of the remaining Δ-Σ modulators to subtract the unfiltered inter-modulator feedback signal of each of the remaining Δ-Σ modulators from the Δ error signal.

[0031] Preferably, the feedforward low-pass filter stage and / or feedback low-pass filter stage includes one or more leakage integrator stages or non-leakage integrator stages, each integrator stage being configured to integrate the corresponding input signal.

[0032] Preferably, one or more leakage integrator stages or non-leakage integrator stages of the feedforward low-pass filter stage are the small-signal equivalent circuits of the dynamic electrical response of the transducer under small-signal excitation.

[0033] In addition, the analog-to-digital encoder of the Δ-Σ modulator may include a one-bit synchronous quantizer or a one-bit asynchronous quantizer, or a three-level asynchronous quantizer or a three-level synchronous quantizer.

[0034] More preferably, the analog-to-digital encoder of the Δ-Σ modulator may include a one-bit asynchronous quantizer and a pulse generator, which convert the filtered Δ error signal into a digital pulse signal d. out (t).

[0035] The feedback low-pass filter stage may also include a finite impulse response (FIR) digital low-pass filter or an infinite impulse response (IIR) digital low-pass filter.

[0036] Preferably, the feedback low-pass filter stage may further include an asynchronous counter stage with a predetermined clock period, which is connected to d out Between (t) and the digital low-pass filter, and configured to integrate the number of asynchronous dou(t) pulses over the entire predetermined clock cycle.

[0037] The analog-to-digital encoder of the Δ-Σ modulator may include a three-level asynchronous quantizer and a three-level bipolar pulse generator, which convert the filtered Δ error signal into a digital bipolar pulse signal d. out (t), where a three-level asynchronous quantizer is configured to send a signal to a three-level bipolar pulse generator to generate three different digital signals, each corresponding to a value within a predetermined range of the received filtered Δ error signal.

[0038] Preferably, the sensing stage and interface stage of the transducer, as well as the leakage integrator stage of the feedforward low-pass filter stage, are three-electrode units operating as a constant-potential-ampere type sensor, wherein, in current mode, the feedback signals within the unfiltered modulator and the feedback signals within the low-pass filter modulator are subtracted from the amplified input signal, and in current mode, the feedback signals between the unfiltered modulators are subtracted from the input of any integrator stage included in the feedforward low-pass filter stage, wherein the feedforward low-pass filter stage is connected to the feedback path within the unfiltered modulator and the feedback path within the low-pass filter modulator.

[0039] The device of the present invention may further include a second current source and a first current source, wherein the second current source is located in the feedback path within the unfiltered modulator and is configured to perform the operation by d out (t) Controlled digital-to-analog conversion, the first current source includes a metal-oxide-semiconductor (MOS) transistor, which is configured to perform the conversion by d out (t) control the amplification and digital-to-analog conversion of the feedback path within the low-pass filter modulator.

[0040] Preferably, the metal-oxide-semiconductor (MOS) transistor operates with a selectable drain-source voltage bias when d out When the output of (t) is zero, the drain-source voltage bias can be selected as zero drain-source voltage or zero source-substrate voltage, and when d out When the output of (t) is not zero, choose d out (t) Proportional to a non-zero extremely low drain-source voltage.

[0041] In a preferred embodiment, the sensing stage may include a FET sensor, and the interface stage performs capacitive amplification through the passivation capacitor and feedback capacitor of the FET sensor, wherein, in current mode, the feedback signal within the low-pass filter modulator, the feedback signal within the unfiltered modulator, and the feedback signal between the unfiltered modulators are subtracted from the amplified input transducer signal. Attached Figure Description

[0042] To supplement the description of the invention, to better understand its features, and according to preferred examples of its practical embodiments, a set of drawings is attached as an integral part of the description. The drawings are illustrated and non-limiting in nature:

[0043] Figure 1 This illustrates a small-signal electrical model of the electrode-electrolyte interface in a prior art three-electrode electrochemical cell.

[0044] Figure 2 An electrical model of a conventional FET electrochemical sensor fabricated using standard CMOS technology is shown.

[0045] Figure 3 A general schematic diagram of a first example implementation of the device is shown, in which each transducer is connected to a unique Δ-Σ modulator.

[0046] Figure 4 A detailed schematic diagram of a first example implementation of the device is shown, in which each transducer is connected to a unique Δ-Σ modulator.

[0047] Figure 5 A general schematic diagram of a second example implementation of the device is shown, in which one or more transducers are connected to one or more Δ-Σ modulators.

[0048] Figure 6 A detailed schematic diagram of a second example implementation of the device is shown, in which one or more transducers are connected to one or more Δ-Σ modulators.

[0049] Figure 7 A general schematic diagram of a third example implementation of the device is shown, wherein some transducers are connected to more than one Δ-Σ modulator, and wherein some outputs of the Δ-Σ modulator are fed back to some other Δ-Σ modulators constituting the device.

[0050] Figure 8 A detailed schematic diagram of a third example implementation of the device is shown, in which some transducers are connected to more than one Δ-Σ modulator, and in which some outputs of the Δ-Σ modulator are fed back to some other Δ-Σ modulators constituting the device.

[0051] Figure 9A and 9B A detailed schematic diagram of the device implemented according to the first embodiment is shown, wherein the FET electrochemical transducer is connected to the Δ-Σ modulator.

[0052] Figure 10 A detailed schematic diagram of a device implemented according to a second embodiment is shown, wherein one or more FET electrochemical transducers are connected to one or more Δ-Σ modulators.

[0053] Figure 11 A detailed schematic diagram of the device implemented according to the third embodiment is shown, wherein a three-electrode unit operating as a constant potential-ampere type transducer is connected to a Δ-Σ modulator.

[0054] Figure 12 A detailed schematic diagram of a device implemented according to a fourth embodiment is shown, wherein one or more three-electrode units operating as constant-potential-ampere type transducers are connected to one or more Δ-Σ modulators.

[0055] Figure 13 The following figure shows the signal recovered after demodulation of the transient response of the first embodiment of the device to a typical increase in analyte concentration, which causes V at a constant and significant drift rate. sens The change in effective rate (above figure).

[0056] Figure 14 The third embodiment of the device is shown for I sens The signal recovered after demodulation of the transient response (see figure below), I sens This corresponds to a typical half-volt-ampere cycle with high resistive loss at the working electrode-electrolyte interface (see figure above). Detailed Implementation

[0057] With the help ofFigures 1 to 14 The preferred embodiments of the Δ-Σ device with background signal attenuation and distributed coding according to the present invention are described below. It should be noted that the use of the terms "first" and "second" may not imply any particular order or rank unless such order or rank is explicitly or implicitly indicated in the context.

[0058] like Figure 3 and Figure 5 As shown, the Δ-Σ device includes one or more transducers (2) and one or more Δ-Σ modulators (3). Figure 4 and Figure 6 As shown in detail, each transducer (2) includes a sensing stage (100) and an interface stage (101), the sensing stage (100) being designed to detect the environment X. in1 (t) (106) attribute, and is configured to convert it into an electrical input signal (107), the interface level (101) is connected to the sensing level (100), receives the electrical input signal (107), amplifies the electrical input signal (107) for further processing, and outputs the amplified input transducer signal (108) to one of the Δ-Σ modulators (3). Figure 4 ) or more ( Figure 6 ).

[0059] In addition, such as Figure 4 and Figure 6 As shown, each Δ-Σ modulator (3) includes an input stage connected to an interface stage (101), which includes two subtraction stages (113, 114). The subtraction stages (113, 114) are configured to receive the unfiltered feedback signal (109) within the modulator and the low-pass filtered feedback signal (110) within the modulator, and from one ( Figure 4 ) or more ( Figure 6 The feedback signals in the unfiltered modulator and the low-pass filter modulator are subtracted from the sum of the amplified input transducer signals (108) to obtain the Δ error signal (111).

[0060] Following both of the two subtraction stages (113, 114) at the input stage, each modulator (3) includes: a feedforward low-pass filter stage (102), an analog-to-digital encoder (104), an unfiltered modulator in-internal feedback path, and a low-pass filter modulator in-internal feedback path, wherein the feedforward low-pass filter stage (102) is configured to filter the Δ error signal to generate a filtered Δ error signal; the analog-to-digital encoder (104), located after the feedforward low-pass filter stage (102), converts the filtered Δ error signal into a digital output signal d. out (t)(112); The feedback path within the unfiltered modulator is located between the analog-to-digital encoder (104) and the two subtraction stages (113, 114), which will d out(t) (112) is converted into the unfiltered modulator feedback signal (109); the low-pass filtered modulator feedback path is located between the analog-to-digital encoder (104) and the two subtraction stages (113, 114) of the input stage, which will d out (t) (112) is converted into the feedback signal (110) within the low-pass filter modulator. The feedback path within the low-pass filter modulator can compress the background signal at the low-pass frequency to increase the dynamic range, readout resolution, and energy efficiency of the Δ-Σ device.

[0061] In aspects of the present invention, such as Figure 3 and Figure 4 As shown, each transducer (2) is connected to a unique Δ-Σ modulator (3).

[0062] In aspects of the present invention, such as Figure 5 and Figure 6 As shown, each transducer (2) is connected to more than one Δ-Σ modulator (3). In particular, the output of the interface stage (101) of the first Δ-Σ modulator (3) is connected to the intermodulator subtraction stage (115) of the second Δ-Σ modulator (3), and the input stage also includes the second Δ-Σ modulator (3) before the two subtraction stages (113, 114).

[0063] exist Figure 7 and Figure 8 In the aspects of the invention disclosed herein, the device includes one or more transducers (2) and two or more Δ-Σ modulators (3). In this case, the device also includes multiple unfiltered inter-modulator feedback paths connected to the d-axis of each Δ-Σ modulator (3). out (t) (112), and is configured to d out (t) is converted into multiple unfiltered inter-modulator feedback signals (116). Furthermore, the device includes an additional subtraction stage (117) located before the feedforward low-pass filter stage (102), which is configured to receive the unfiltered inter-modulator feedback signals (116) of each of the remaining Δ-Σ modulators (3) to subtract the unfiltered inter-modulator feedback signals of each of the remaining Δ-Σ modulators from the Δ error signal (111). Adding inter-modulator feedback paths allows for the distribution of pulse modulation coding among the Δ-Σ modulators. This is an important feature for increasing the maximum total encoder sampling rate and effectively simulating the correlation between the input signals converted by the sensors.

[0064] In aspects of the invention, the feedback path within the unfiltered modulator includes one or more first digital-to-analog converters (105), and / or the feedback path within the unfiltered modulator includes one or more third digital-to-analog converters (305).

[0065] In this invention, the feedback path within the low-pass filter modulator includes a feedback low-pass filter stage (103) and one or more second digital-to-analog converters (205).

[0066] like Figure 4 As shown, the second digital-to-analog converter (205) can be placed before or after the low-pass filter.

[0067] In aspects of the invention, the feedforward low-pass filter stage (102) and the feedback low-pass filter stage (103) include one or more leakage integrator stages or non-leakage integrator stages, each integrator stage being configured to integrate a corresponding input signal.

[0068] In this embodiment, the low-pass filter stage can be implemented by incorporating multiple feedback loops and feedforward loops within a backbone consisting of cascaded integrator stages. Negative feedback connects the integrator output to the input of the same or previous integrator stage to adjust the filter's gain and frequency response. Feedforward connects the output of each integrator stage to the input of the next stage to compensate for phase and amplitude distortion introduced by the feedback mechanism.

[0069] Furthermore, a leakage integrator is a stage that receives the input signal and generates the output signal by integrating the leakage signal over time. The leakage signal is obtained based on a damping factor applied to reduce the amplitude of the input signal. A non-leakage integrator, on the other hand, is a stage that receives the input signal and generates the output signal by integrating the input signal without any leakage or attenuation.

[0070] In aspects of the invention, one or more leakage integrator stages or non-leakage integrator stages of the feedforward low-pass filter stage (102) include a small-signal equivalent circuit of the dynamic electrical response of the transducer (2).

[0071] The small-signal equivalent circuit is a simplified representation of the dynamic response of a device, describing its electrical behavior under small-signal excitation. A small-signal equivalent circuit consists of a set of linear circuit elements (such as resistors, capacitors, and controlled sources) connected together to simulate the device.

[0072] In this invention, the analog-to-digital encoder (104) of the Δ-Σ modulator (3) includes a one-bit quantizer synchronous or a one-bit asynchronous quantizer.

[0073] In an aspect of the invention, the analog-to-digital encoder (104) of the Δ-Σ modulator (3) includes a one-bit asynchronous quantizer connected to a pulse generator that converts the filtered Δ error signal into a digital pulse signal d. out (t) (112). An asynchronous quantizer is configured to send a signal to a pulse generator to generate a digital signal when the received filtered Δ error signal is higher than a predetermined threshold signal.

[0074] In this invention, the analog-to-digital encoder (104) of the Δ-Σ modulator (3) includes a three-level asynchronous quantizer and a three-level bipolar pulse generator, which convert the filtered Δ error signal into a digital bipolar pulse signal d. out (t)(112). The three-level asynchronous quantizer is configured to send a signal to the three-level bipolar pulse generator to generate three different digital signals, each corresponding to a value within a predetermined range of the received filtered Δ error signal.

[0075] Regarding the previously described embodiments, a one-bit asynchronous quantizer is a stage that uses threshold operation to convert a continuous or discrete signal into a binary signal of "0" or "1". A one-bit synchronous quantizer uses threshold operation and a sampling clock to convert a continuous or discrete signal into a binary signal. It maps the input signal to "0" or "1" at regular intervals determined by the clock frequency. A three-level asynchronous quantizer uses threshold operation to convert a continuous or discrete signal into three output levels. A three-level synchronous quantizer uses threshold operation and a clock that determines the regular sampling interval to convert a continuous or discrete signal into three output levels.

[0076] Furthermore, digital pulse signals consist of a series of square wave electrical pulses, each occupying one of two discrete binary amplitude levels: "0" or "1". Bipolar pulse signals consist of a series of square wave electrical pulses, each occupying one of three discrete amplitude levels: positive, negative, or zero.

[0077] In aspects of the present invention, such as Figure 11 and Figure 12 As shown, the sensing stage (100), interface stage (101), and feedforward low-pass filter stage (102) of the transducer (2) are three-electrode units operating as a constant-potential-ampere type sensor. In current mode, the unfiltered modulator feedback signal (109) and the low-pass filter feedback signal (110) are subtracted from the amplified input signal (108), and in current mode, the unfiltered modulator feedback signal (116) is subtracted from the input of the second integrator stage contained in the feedforward low-pass filter stage. The three-electrode unit is connected to an analog-to-digital encoder (104), which outputs a digital output signal d. out (t)(112). The feedback path within the unfiltered modulator and the feedback path within the low-pass filtered modulator are connected after the analog-to-digital encoder (104). Furthermore, the feedback path within the unfiltered modulator and the feedback path within the low-pass filtered modulator are connected to the three-electrode unit. The three-electrode unit has a small-signal equivalent circuit.

[0078] exist Figure 11 Of all the feedback signals, the one using d out(t) or the current source (911) controlled by the output of the feedback low-pass filter stage (103) performs the digital-to-analog conversion. To allow for programmable and miniaturized filtering of very low cutoff frequencies within a microchip, the feedback low-pass filter stage (103) of the feedback path within the low-pass filter modulator is implemented in the digital domain. For this purpose, the implementation of the feedback low-pass filter stage (103) may include a finite impulse response (FIR) digital low-pass filter or an infinite impulse response (IIR) digital low-pass filter. In the case of asynchronous quantization, the implementation of the feedback low-pass filter stage (103) may include an asynchronous counter stage with a predetermined clock period connected to d out (t) and the digital low-pass filter, and configured to asynchronously operate over the entire clock cycle. out The number of pulses (t) is integrated. The sensor in the loop detects the current I. sens Integrate the points.

[0079] exist Figure 14 In the diagram, the dashed, solid, and dotted lines correspond to the voltammograms showing a decreasing peak size for oxidation. For example... Figure 14 As shown in the figure below, by setting the cutoff frequency of the feedback path within the low-pass filter modulator to be higher than the cutoff frequency of the background signal to be attenuated, but lower than the effective I... sens The cutoff frequency of the spectral component of interest in the signal allows the device to be configured to filter out increasing background signals and active I / O. sens The summation of the signals is compressed into a recoverable bulge with decreasing amplitude. This helps distinguish between analyte concentration and electrode kinetics. It also expands the available dynamic range over time to read out information of interest.

[0080] exist Figure 12 In the middle, multiple I generated by multiple transducers sens The voltage is integrated by each sensor in the loop, and the resulting integrated voltage signal is converted back into a current by the transconductor (905), and summed together in that current domain. The resulting summed current signal is integrated in the integrating capacitor (904) of the second integrator stage. Therefore, multiple IL signals are generated before the transconductor (905). sens It is transmitted to different Δ-Σ modulators (3). Furthermore, Figure 12 The unfiltered inter-modulator feedback path is defined, connecting the output of the analog-to-digital encoder (104) of the first Δ-Σ modulator (3) to each of the other Δ-Σ modulators (3) preceding its analog-to-digital encoder (104). Using d out (t) controls the current source (911) to perform digital-to-analog conversion of the feedback signal (116) between unfiltered modulators.

[0081] exist Figure 9A , Figure 9B and Figure 10 In the aspects of the invention described herein, the sensing stage (100) includes a FET sensor, and the interface stage (101) performs capacitive amplification via the passivation capacitor and feedback capacitor of the FET sensor, wherein, in current mode, the unfiltered modulator feedback signal, the low-pass filter modulator feedback signal, and the low-pass filter modulator inter-feedback signal are subtracted from the amplified input transducer signal (108) of the Δ-Σ modulator (3) including the device.

[0082] exist Figure 9A , Figure 9B and Figure 10 In, using d out The current source (911) controlled by (t) is used to perform the digital-to-analog conversion of the feedback path within the unfiltered modulator. The current source and the current source controlled by d... out (t) controls a metal-oxide-semiconductor (MOS) transistor (901) to perform digital-to-analog conversion within the feedback path of the low-pass filter modulator. Figure 10 In, using d out The current source (911) controlled by (t) performs the digital-to-analog conversion of the feedback path between the unfiltered modulators. The transduction, capacitive amplification, and subtraction stages are performed by an amplifier (in this case, a minimized implementation of a metal-oxide-semiconductor (MOS) transistor including the current source and the FET sensor (906)), a dielectric capacitor (902) of the sensing film, and a feedback capacitor (903). The output voltage of the capacitive amplifier is connected to a transconductor (905) that converts it into a transconductor output current. In current mode, the transconductor output current is integrated in an integrating capacitor (904) of a single-stage integrator after subtracting the feedback signal within the unfiltered modulator and an optional inter-modulator signal. The integrating capacitor (904) is connected to generate the digital output signal d. out The analog-to-digital encoder (104) of (t).

[0083] To allow for very low cutoff frequencies to be configured in a microchip and to minimize leakage at the gate of the MOS transistor, the controlled current source (901) of the feedback path within the low-pass filter modulator can be configured as follows: Figure 9B The implementation shown uses an ultra-low leakage MOS transistor, operating with selectable drain-source voltage via, for example, a multiplexer stage. When d out When the output of (t) is zero, the transistor can be biased to have zero drain-source voltage. It can also be biased to zero source-substrate voltage, resulting in zero conduction from the capacitor amplifier through the MOS transistor channel and the diffused diode, respectively. Although non-zero d out (t) Select a non-zero drain-source voltage, but this voltage (i.e., ±ΔV)dout In practice, it can also be set to very low and related to d. out (t) is proportional.

[0084] exist Figure 13 In the diagram, the solid line corresponds to an increase in analyte concentration, resulting in a shift similar to V. sens Effective V of the rate sens Rate; the dashed line corresponds to an increase in analyte concentration, resulting in an effective Vg. sens The rate is approximately the drift V sens Half the rate; the dashed line corresponds to an increase in analyte concentration, resulting in an effective Vg. sens The rate is approximately the drift V sens Twice the speed. For example... Figure 13 As shown in the figure below, by setting the cutoff frequency of the feedback path within the low-pass filter modulator to be higher than the desired attenuation drift and lower than the effective Vc... sens The cutoff frequency of the spectral component of interest in the signal. Figure 9A and 9B The device can be configured to control drift and effective V sens The sum of the signal increases is compressed into a recovered bulge whose amplitude is proportional to the rate of increase. This helps to distinguish the effective V. sens The signal can be detected before drift and helps to identify chemical reactions that increase the concentration of analytes of interest by measuring pH changes that interact with DNA fragments or antigens, such as in infectious disease detection based on ion-selective field-effect transistors (ISFETs). It also extends the usable dynamic range of the sensor before drift.

Claims

1. A delta-sigma device, wherein, The delta-sigma device comprises one or more transducers (2) and one or more delta-sigma modulators (3), wherein each of the transducers (2) comprises: a sensing stage (100) for detecting an environment X in (t) (106) properties, and configured to convert said environment X in (t) (106) into an electrical input signal (107), and an interface stage (101) connected to the sensing stage (100) and configured to receive the electrical input signal (107), amplify the electrical input signal (107), and send the amplified input transduction signal (108) to one or more delta-sigma modulators (3), and wherein each of the delta-sigma modulators (3) comprises: an input stage connected to the interface stage (101) comprising two subtraction stages (113, 114) configured to receive an unfiltered intra-modulator feedback signal (109) and a low-pass filtered intra-modulator feedback signal (110) and to subtract the unfiltered intra-modulator feedback signal (109) and the low-pass filtered intra-modulator feedback signal (110) from a sum of one or more of the amplified input transduction signals (108) to obtain a delta error signal (111), a feed-forward low-pass filtering stage (102) located after the two subtraction stages (113, 114) of the input stage and configured to filter the delta error signal (111) to generate a filtered delta error signal; an analog-to-digital encoder (104) located after the feed-forward low-pass filter stage (102) which converts the filtered delta error signal into a digital output signal d out (t) (112), an unfiltered modulator inner feedback path comprising one or more first digital-to-analog converters (105) located between the said analog-to-digital encoder (104) and a first of two subtraction stages (114) of the input stage and converting d out (t) (112) into the unfiltered modulator inner feedback signal (109), and a low-pass filter modulator inner feedback path comprising a feedback low-pass filter stage (103) and one or more second digital-to-analog converters (205) located between the sigma-delta encoder (104) and a second one of the two subtraction stages (113) of the input stage and converting d out (t) (112) into a low-pass filter modulator inner feedback signal (110); and wherein the cut-off frequency of the feedback low-pass filtering stage (103) is set between a background signal component range and a signal of interest component signal range.

2. The apparatus of claim 1, wherein, The background signal is a drift and / or an offset.

3. The apparatus of claim 1, wherein, Each transducer (2) is connected to a single delta-sigma modulator (3) or to more than one delta-sigma modulator (3).

4. The apparatus of claim 1, wherein, The device comprises one or more transducers (2) and two or more delta-sigma modulators (3); and wherein the device further comprises a plurality of unfiltered inter-modulator feedback paths comprising one or more third digital-to-analog converters (305) connected to the d out (t) (112) of each delta-sigma modulator (3) and configured to convert the d out (t) into a plurality of unfiltered inter-modulator feedback signals (116); and wherein the device comprises an additional subtraction stage (117) located before the feedforward low-pass filter stage (102) and configured to receive the unfiltered inter-modulator feedback signals (116) of each delta-sigma modulator (3) remaining to subtract the unfiltered inter-modulator feedback signals (116) of each delta-sigma modulator (3) remaining from the delta error signal (111).

5. The apparatus of claim 1, wherein, The feed-forward low-pass filtering stage (102) or the feedback low-pass filtering stage (103) comprises one or more leaky integrator stages or non-leaky integrator stages, each integrator stage being configured to integrate a respective input signal.

6. The apparatus of claim 5, wherein, The one or more leaky integrator stages or non-leaky integrator stages of the feed-forward low-pass filtering stage (102) are a small-signal equivalent circuit of a dynamic electrical response of the transducer (2) under small-signal excitation.

7. The apparatus of claim 1, wherein, The analog-to-digital encoder (104) of the delta-sigma modulator (3) comprises a one-bit synchronous quantizer or a one-bit asynchronous quantizer, or a three-level asynchronous quantizer or a three-level synchronous quantizer.

8. The apparatus of claim 1, wherein, The analog-to-digital encoder (104) of the delta-sigma modulator (3) comprises a one-bit asynchronous quantizer and a pulse generator, which converts the filtered delta error signal into a digital pulse signal d out (t) (112).

9. The apparatus of claim 8, wherein, The feedback low-pass filtering stage (103) further comprises a finite impulse response digital low-pass filter or an infinite impulse response digital low-pass filter.

10. The apparatus of claim 9, wherein, The feedback low-pass filter stage (103) further comprises an asynchronous counter stage with a predetermined clock period, connected between d out (t) and the digital low-pass filter, and configured to integrate the number of asynchronous d out (t) pulses over the entire clock period.

11. The apparatus of claim 1, wherein, The analog-to-digital encoder (104) of the delta-sigma modulator (3) comprises a three-level asynchronous quantizer and a three-level bipolar pulse generator, which convert the filtered delta error signal into a digital bipolar pulse signal d out (t) (112), wherein the three-level asynchronous quantizer is configured to send signals to the three-level bipolar pulse generator to generate three different digital signals, each digital signal corresponding to a predetermined range of values of the received filtered delta error signal.

12. The apparatus of claim 4, wherein, The sensing stage (100) and the interface stage (101) of the transducer (2) and the leak integrator stage of the feedforward low pass filter stage (102) are a three electrode cell working as a potentiometric-ampere type sensor; and wherein the unfiltered modulator internal feedback signal (109) and the low pass filtered modulator internal feedback signal (110) are subtracted from the amplified input signal in current mode and the unfiltered modulator inter feedback signal (116) is subtracted from the input of any of the integrator stages comprised in the feedforward low pass filter stage in current mode, wherein the feedforward low pass filter stage is connected to the analog to digital encoder (104), the analog to digital encoder (104) is connected to the unfiltered modulator internal feedback path and the low pass filtered modulator internal feedback path.

13. The apparatus of claim 12, further comprising a second current source (911) and a first current source, the second current source (911) being located in a feedback path within the unfiltered modulator configured to perform the amplification and digital-to-analog conversion controlled by d out (t). The first current source comprises a metal oxide semiconductor (MOS) transistor (901) configured to perform the amplification and digital-to-analog conversion controlled by d out (t) within the low pass filter modulator feedback path.

1. A method for generating a modulated signal, the method comprising: generating a first signal comprising a plurality of first signal components, each first signal component having a first frequency; generating a second signal comprising a plurality of second signal components, each second signal component having a second frequency; and combining the first signal and the second signal to generate a third signal comprising a plurality of third signal components, each third signal component having a third frequency, wherein the third frequency is different from the first frequency and the second frequency.

2. The method of claim 1, wherein the first frequency is higher than the second frequency.

3. The method of claim 1, wherein the first frequency is lower than the second frequency.

4. The method of claim 1, wherein the first frequency is equal 14. The apparatus of claim 13, wherein, The metal oxide semiconductor (MOS) transistor operates with a selectable drain-source voltage, when d out (t) is zero, the selectable drain-source voltage is biased to a zero drain-source voltage or a zero source-substrate voltage; and, when d out (t) is not zero, then a non-zero, very low drain-source voltage is selected that is proportional to d out (t).

15. The apparatus of claim 4, wherein, The sensing stage (100) comprises a field effect transistor sensor and the interface stage (101) performs a capacitive amplification through a passivation capacitor and a feedback capacitor of the field effect transistor sensor and wherein the low pass filtered modulator internal feedback signal (110), the unfiltered modulator internal feedback signal (109) and the unfiltered modulator inter feedback signal (116) are subtracted from the amplified input transduction signal (108) in current mode.

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