Quantum device, quantum chip and quantum computer

Abstract

The invention discloses a quantum device, a quantum chip and a quantum computer, and belongs to the technical field of quantum chip manufacturing. The quantum device comprises a substrate of which the surface is provided with quantum bits; the resonant cavity and the quantum bit are arranged on the substrate in a coplanar mode, and the resonant cavity is coupled with the quantum bit and used for reading the quantum state of the quantum bit; wherein the resonant cavity takes the quantum bit as a starting point and spirally extends in a direction far away from the starting point. Through the mode, the quantum device provided by the invention comprises the spiral resonant cavity, and the resonant cavity in the form is smaller in size, namely, the area occupied by the surface of the substrate is smaller, so that more quantum devices such as quantum bits can be integrated on the surface of the substrate with the same size.

Description

Technical Field

[0001] This application belongs to the field of quantum chip manufacturing technology, and in particular relates to a quantum device, a quantum chip, and a quantum computer. Background Technology

[0002] The core of a quantum computer is a superconducting quantum chip, and the core of a superconducting quantum chip is a superconducting qubit. In order to continuously improve the computing power of a quantum computer, more and more qubits need to be highly integrated into the superconducting quantum chip.

[0003] As the integration density of integrated circuits continues to increase, the number of I / O pins in integrated circuits is growing rapidly, and the number of I / O pins in microelectronic packages is also increasing accordingly. This undoubtedly leads to a continuous increase in interconnect density. With the development of technology, a limited number of qubits have been integrated onto the surface of a substrate, which is approaching the physical limit. It is no longer possible to integrate more qubits on a substrate with a limited size, which is undoubtedly detrimental to the development of quantum computers. Summary of the Invention

[0004] The purpose of this application is to provide a quantum device, a quantum chip, and a quantum computer to solve the problem in the prior art that due to the development of quantum computers, the substrate surface of the quantum chip has reached the physical limit of integrating a limited number of qubits, making it impossible to integrate more qubits. By setting a spiral-shaped resonant cavity, the area occupied by the resonant cavity on the substrate surface can be reduced, making the arrangement of qubits and their related electronic components more compact, reducing the size occupied by a single qubit and its related readout signal line, thereby allowing more qubits to be expanded on a limited substrate surface.

[0005] To address the aforementioned technical problems, the present invention provides a quantum device, comprising:

[0006] A substrate with qubits disposed on its surface; and

[0007] A resonant cavity is disposed coplanarly with the quantum bit on the substrate, the resonant cavity is coupled to the quantum bit and used to read the quantum state of the quantum bit;

[0008] The resonant cavity extends in a spiral shape from the quantum bit as the starting point and in a direction away from the starting point.

[0009] Preferably, the qubit includes a Josephson junction and two vias for forming a bit capacitance;

[0010] All of the vias penetrate the substrate.

[0011] Preferably, the through hole is cylindrical;

[0012] Alternatively, the through hole is a rectangular cuboid.

[0013] Preferably, the through hole is a cylinder, and a depth-diameter ratio of the through hole is 5-10.

[0014] Preferably, one end of the resonant cavity is coupled to the bit capacitor.

[0015] Preferably, the resonant cavity is in the form of a coplanar waveguide.

[0016] Preferably, one end of the resonant cavity close to the quantum bit is open-circuited to ground, and the other end is connected to ground.

[0017] The application also provides a quantum chip, comprising: the quantum device described above; and

[0018] A superconducting metal layer of the substrate is disposed coplanarly with the quantum bit, and part of the superconducting metal layer is used to be etched to form the resonant cavity.

[0019] Part of the superconducting metal layer away from the resonant cavity forms a window exposing part of the substrate, and the quantum bit is formed in the window.

[0020] Preferably, the superconducting metal layer away from the resonant cavity and the window further forms a read bus.

[0021] One end of the resonant cavity away from the quantum bit is coupled to the read bus.

[0022] The application also provides a quantum computer, comprising: the quantum chip described above.

[0023] Compared with the prior art, the application provides a spiral resonant cavity, the resonant cavity extends spirally away from the quantum bit as a starting point, the quantum bit is disposed on the inner side of the spiral resonant cavity, the space occupied by the resonant cavity on the substrate surface can be reduced, the quantum bit and related elements are arranged more compactly, the size of the quantum bit is reduced, and more quantum bits can be expanded on the limited substrate surface. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A structure diagram of a quantum bit provided by an embodiment of the application;

[0025] Figure 2 A structure diagram of a quantum chip provided by an embodiment of the application;

[0026] Figure 3 A structure diagram of a Josephson junction and a capacitor provided by an embodiment of the application;

[0027] Figure 4The substrate provided by the embodiment of the application is provided with a Josephson junction and a capacitor structure.

[0028] Legend: 1 - substrate, 2 - resonant cavity, 3 - Josephson junction, 4 - via. DETAILED DESCRIPTION

[0029] The specific embodiments of the application will be described in more detail below with reference to the accompanying drawings. The advantages and features of the application will be more apparent from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the application.

[0030] In the description of the application, it should be understood that the terms "center", "upper", "lower", "left", "right" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the application.

[0031] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0032] According to different physical systems for constructing quantum bits, quantum bits in physical implementation include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quantum, photons, etc.

[0033] Quantum computing of superconducting quantum circuits is currently the fastest and best solid quantum computing implementation method. Because the energy level structure of superconducting quantum circuits can be controlled by external electromagnetic signals, the controllability of circuit design customization is strong. At the same time, benefiting from the existing mature integrated circuit process, superconducting quantum circuits have scalability that is difficult to match by multiple quantum physical systems.

[0034] In a superconducting quantum circuit, a qubit includes a Josephson junction, which is a structure formed by separating two thin-film superconducting layers with a non-superconducting material. When the temperature is lowered to a certain low-temperature (below the critical temperature, milli-Kelvin), the superconducting layers achieve superconductivity, and electron pairs can tunnel from one superconducting layer to another through the non-superconducting layer. In a qubit, the Josephson junction, which serves as a nonlinear inductive device, is connected in parallel with one or more capacitive devices to form a nonlinear microwave oscillator, so that the qubit has a resonance / transition frequency determined by the values of the inductance and capacitance therein.

[0035] The physical basis of qubit reading is dispersive reading, which utilizes the nonlinear coupling of the qubit with the cavity to carry or transmit the information processed by the qubit in the form of a microwave signal in the microwave frequency range, and to capture, process and analyze the microwave signal, i.e., the quantum information that can be encoded therein. The readout circuit is a circuit coupled with the qubit for capturing, reading and measuring the quantum information.

[0036] In one example of a superconducting quantum circuit, as Figure 1 described, the structure of the qubit employs a single ground-connected capacitor, and a superconducting quantum interference device (SQUID) / superconducting quantum interference meter with one end connected to the ground and the other end connected to the capacitor. The capacitor is typically a cross-plate capacitor (Cq) as Figure 1 shown. Notably, the cross-plate capacitor has a gap between the capacitor and the ground plane. In addition, one end of the superconducting quantum interference device is connected (coupled) to the cross-plate capacitor, and the other end is connected to the ground plane. Since the first end of the cross-plate capacitor is typically used to connect the superconducting quantum interference device, and the second end is used to couple with the readout resonant cavity and other readout structures, a certain space is needed near the first and second ends for wiring. For example, a space is needed near the first end for arranging the XY signal line and the Z signal line. The other two ends of the cross-plate capacitor are used to couple with adjacent qubits.

[0037] Based on this structure, the qubits can be arranged in a one-dimensional chain to achieve the integration and expansion of the qubits. The qubits at adjacent positions are coupled and share a readout signal line (ReadOut Line). The circuit structure for reading includes a readout resonant cavity coupled with the qubit to be read, and a readout signal line coupled with the readout resonant cavity. Each qubit independently corresponds to a resonant cavity and a readout signal line. Based on the coupling of the respective readout resonant cavities and the shared readout signal line, the state information of the qubits is transmitted from the qubits to the transmission line.

[0038] However, as the integration of integrated circuits continues to increase, the number of signal ports (I / O) of the integrated circuits also rapidly increases, and the number of pins of the microelectronic package also increases, which undoubtedly makes the interconnection density continue to increase. For this reason, the traditional two-dimensional interconnection packaging technology cannot solve the problems of interconnection delay, power consumption increase and the like caused by high integration and signal size approaching the physical limit; in addition, based on the above reasons, it is difficult to expand the limited space to arrange more quantum bits for detection, which is undoubtedly a great problem for the development of quantum computing.

[0039] Among them, the quantum bit needs a high-quality factor Q shunt capacitor, which is usually realized by using a large coplanar capacitor, and the readout resonant cavity for reading the state of the quantum bit is usually composed of a coplanar waveguide with a length of millimeters.

[0040] In a typical configuration in the past, the resonant cavity is partially meandering, one end of which is open-circuited to ground, and the other end is connected to ground; and in a superconducting quantum chip, a plurality of resonant cavities share one readout bus, one end of each resonant cavity is close to a readout bus and coupled to the readout bus, and the other end is close to the corresponding quantum bit and used to read out the quantum information of the quantum bit. In addition, the frequency of the resonant cavity is determined by the inductance per unit length, the capacitance and the total length. The current resonant cavity is simple to manufacture, but the large area occupied by the resonant cavity makes it difficult to arrange more quantum bits on the limited substrate surface.

[0041] In an embodiment of the present application, a quantum device is provided as shown in Figure 2 The substrate 1 has a surface formed with a quantum bit and a resonant cavity 2, and the resonant cavity 2 is coupled to the quantum bit and mainly used for reading the quantum state of the quantum bit. It is worth noting that in this embodiment, the resonant cavity 2 is mainly changed in the form of construction compared with the traditional way, that is, the resonant cavity 2 is manufactured to extend spirally away from the quantum bit as the starting point.

[0042] For the above spiral resonant cavity 2, the spiral shape not only reduces the unexpected crosstalk with other devices around, but more importantly, this form can greatly reduce the area occupied by the resonant cavity 2 on the surface of the substrate 1; based on the above reasons, it can be known that the selection of the spiral resonant cavity makes the same area of the substrate 1 surface can arrange more quantum bits to improve the computing power.

[0043] In an embodiment of the present application, the quantum bit is manufactured based on the substrate 1, that is, the substrate 1 is processed, including but not limited to film plating on the surface of the substrate 1 and etching the substrate 1 to form the quantum bit and the like; here, the quantum bit includes, for example, Figure 3one Josephson junction 3 and two vias 4 corresponding to the Josephson junction 3; and, all the vias 4 must be through the substrate 1 to form a complete bit capacitor. Among them, the Josephson junction 3 is prepared on one surface of the substrate 1 by means of inclined evaporation, etc., and the number is at least one, which can be determined according to the actual demand for the number of quantum bits and the process capability; in addition, the via 4 is used to form the bit capacitor, and the number is specifically corresponding to the Josephson junction 3, specifically one Josephson junction 3 corresponds to two vias 4, two vias 4 together form a bit capacitor, and at least one via 4 adjacent to or with high coupling strength is coupled to the Josephson junction 3 to form a quantum bit; it is worth noting that the via 4 is generally obtained by etching the substrate 1, which requires a high aspect ratio, and the bit capacitor in the form of via 4 can realize the characteristics of small size and large capacitance value at the same time.

[0044] Here, for the above embodiment, a compact superconducting silicon via 4 is used to realize a lumped element capacitor between the quantum bit and the resonant cavity 2, and the silicon via 4 is a high-quality factor shunt capacitor, which can be used as a capacitor element, and its size is significantly reduced compared with the prior art.

[0045] Further, all the vias 4 above are in the shape of a cylinder; or, the via 4 can also be a rectangular cuboid with a rectangular cross section. In fact, the shape of the via 4 is not particularly limited, and what needs to be met is that the two vias 4 associated (together form a bit capacitor) are made into the same shape, but due to uncontrollable variables in the manufacturing process of the via 4, such as the hardness of each region of the substrate 1 material, the etching parameters or time of each via 4, and the precision problem of the photoetch machine used to etch the via 4 on the substrate 1, there are some errors between the shapes of the two vias 4 finally manufactured, which has no negligible negative impact on the quantum bit itself, which is also feasible here; and, one of the two vias 4 is selected to be connected with the Josephson junction 3 to achieve the best connection effect. In addition, as long as the shape of the two vias 4 can form a bit capacitor, the shape can not be limited, that is, other shapes that meet the requirements are also available.

[0046] Please refer to Figure 4In the prior art, the shape of the through hole 4, which is generally cylindrical, has a depth-to-diameter ratio of 4-20, where the depth is the thickness of the substrate 1 and the diameter is the diameter of the cross-section. In this case, the TSV through hole 4 with a high depth-to-diameter ratio has a large self-capacitance, which is a good example of reducing the area occupied by the bit capacitance. According to tests by the inventor, the bit capacitance of the through hole 4 is only 1 / 20-1 / 30 of the area occupied by the substrate 1 compared to the commonly used flat capacitor.

[0047] In the manufacturing method of the through hole 4, the substrate 1 is etched to form the through hole 4. The substrate 1 can be a silicon substrate 1 or a sapphire substrate 1, and other materials can also be used as the substrate 1. The surface of the substrate 1 can be polished to form a smooth and flat surface structure, which can make the flatness of the substrate 1 surface higher than that of the substrate 1 after etching. The actual manufacturing conditions are used as the reference, and the above examples are not limited.

[0048] It is worth noting that all the through holes 4 are perpendicular to the surface of the substrate 1 to achieve the best results.

[0049] For the above quantum device, the through hole 4 used to form the bit capacitance can be a cylinder or a cuboid, and the bit capacitance formed by the through hole 4 can be used as part of the quantum device. In addition, the quantum device also includes at least one resonant cavity 2 in the form of a coplanar waveguide, which has one end disconnected from the ground and one end connected to the ground, and is manufactured on the surface of the substrate 1 together with the Josephson junction 3. The end of the resonant cavity 2 disconnected from the ground is coupled to the quantum bit to read the quantum state of the quantum bit.

[0050] In another embodiment of the present application, a quantum chip is provided, which includes the quantum device described above, and a superconducting metal layer disposed on the substrate 1 together with the quantum bit, part of the superconducting metal layer being etched to form the resonant cavity 2. The superconducting metal layer is etched to form a window exposing part of the substrate 1 in the area away from the resonant cavity 2, and the Josephson junction 3 is manufactured in the window by oblique evaporation or other methods.

[0051] Further, the superconducting metal layer on the surface of the substrate 1 is etched to form a read bus in the area away from the resonant cavity 2 and the window, and the read bus is coupled to the end of the resonant cavity 2 away from the quantum bit.

[0052] For the above quantum chip, the embodiments of the present application also provide several quantum chip manufacturing methods:

[0053] Method one:

[0054] First step: coating a superconducting metal layer on the substrate 1; the superconducting metal layer includes one or more of aluminum, niobium, tantalum, and titanium nitride;

[0055] Second step: etching the substrate 1 and the superconducting metal layer to form two through holes 4 penetrating through the opposite surfaces of the substrate 1;

[0056] Third step: etching the superconducting metal layer to form a window exposing part of the substrate 1;

[0057] Fourth step: preparing a Josephson junction 3 in the window.

[0058] Method two:

[0059] First step: etching the substrate 1 to form two through holes 4 penetrating through the opposite surfaces;

[0060] Second step: coating a superconducting metal layer on the substrate 1 and forming a window exposing part of the substrate 1;

[0061] Third step: forming a Josephson junction 3 in the window.

[0062] For the above method one and method two, the following problems often exist in practice: after the through holes 4 are etched on the substrate 1, when the Josephson junction 3 is prepared, photoresist needs to be coated on the surface of the substrate 1 first, but due to the existence of the through holes 4, the photoresist flows into the through holes 4 and even seeps to the bottom of the substrate 1, so that the back surface of the substrate 1 is not easy to be sucked by vacuum, resulting in that the photoresist cannot be spin-coated. In addition, after the photoresist flows into the through holes 4, it is also not easy to clean the photoresist in the through holes 4, which will cause the performance of the quantum chip to be damaged.

[0063] To this end, the following solutions are proposed by the technical personnel of the present application: a polyimide film is attached to the bottom of the substrate 1, or a piece of silicon wafer is padded at the bottom of the substrate 1, which can prevent the seepage of the glue to the bottom of the silicon wafer; in addition, for the problem that the photoresist in the through holes 4 is difficult to clean, EKC solution and megasonic cleaning machine can be used to effectively clean the seepage of the glue in the holes (ordinary glue cleaning uses ultrasonic cleaning).

[0064] Method three:

[0065] First step: coating a superconducting metal layer on the substrate 1 and forming a window exposing part of the substrate 1;

[0066] Second step: forming a Josephson junction 3 in the window;

[0067] Third step: etching the substrate 1 and the superconducting metal layer to form two through holes 4 penetrating through the opposite surfaces of the substrate 1.

[0068] For the above method three, in practice, there are often the following problems: that is, in the last preparation of the via 4, due to the high overlay accuracy requirement, it needs to be well controlled and the distance of the Josephson junction 3 and other devices, that is, to perfectly overlay the via 4 between the one end of the readout resonator 2 which is disconnected to the ground and the Josephson junction 3, this step is extremely difficult.

[0069] To this end, the applicant proposes the following solution: set the mark point of overlay alignment in advance, and use the DUV (deep ultraviolet) exposure machine with high exposure accuracy for overlay exposure.

[0070] In addition, in the quantum chip, there are also various circuit structures with different functions around the quantum bit, which are used to regulate the state of the quantum bit. For example, the circuit structure also includes the driving control signal line (XY-Control Line, also known as xy control line or pulse control signal line) for XY rotation operation of the quantum bit. By applying a driving voltage signal in the circuit, the quantum bit can be excited to transition; it is associated with the quantum bit through capacitive coupling. The circuit structure also includes the circuit structure for Z rotation operation of the quantum bit, and is completed by the control signal line near the superconducting quantum interference device (squid); it is called the magnetic flux control signal line (Z-Control Line, also known as Z control signal line or frequency control signal line).

[0071] As described above, the magnetic flux control signal line is arranged near the superconducting quantum interference device (squid), which excites the current and inductively couples with the superconducting quantum interference device (squid) through the magnetic field. It should be noted that the magnetic flux control signal line and the driving control line can be used to control the quantum bit, but the essence of the control of the quantum bit by the two is not the same. For example, the signal (current) transmitted by the magnetic flux control signal line generates a magnetic field, which is applied to the superconducting quantum interference device region and passes through the region to change the current of the superconducting quantum interference device, so as to achieve the control effect, thereby changing the frequency of the quantum bit and achieving the purpose of frequency control of the quantum bit; while for the driving control signal line, it applies a pulse to the quantum bit in the form of an electric field, which makes the energy level of the quantum bit transition.

[0072] Specifically, the material of the superconducting metal layer satisfies the superconducting performance at or below the critical temperature (10-100 millikelvin (mK) or about 4K), such as one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN). The superconducting material is selected according to the actual situation, and is not limited by the above examples.

[0073] In a quantum chip (or quantum processor), a large number of quantum bits (e.g., superconducting quantum bits) are integrated to provide more powerful quantum computing performance. Therefore, more quantum bits are integrated in a quantum chip in pursuit of performance and practicality. However, quantum bits such as superconducting quantum bits require various control lines, and the number of control lines increases as the number of quantum bits increases. On the other hand, the size of the substrate 1 of the chip is limited, and in order to accommodate more quantum bits, a reasonable spatial layout needs to be performed, including control of the area occupied by the quantum bit structure and planning of the layout of the control lines of the corresponding bits.

[0074] In another embodiment of the present application, a quantum computer is also provided, comprising: a measurement and control system, a refrigeration system, and the aforementioned quantum chip. The signal transmission, hierarchical arrangement, etc. can refer to other similar technologies, and will not be described here.

[0075] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", or "a specific example" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0076] The above embodiments according to the drawings illustrate the structure, features and effects of the present application, and the above description is only the preferred embodiment of the present application, but the present application is not limited by the drawings shown. Any change or modification made in accordance with the concept of the present application, or equivalent embodiments with equivalent changes, still within the spirit of the specification and drawings, shall be within the scope of protection of the present application.

Claims

1. A quantum device, characterized in that, The quantum device comprises: a substrate (1) provided with a quantum bit; and a resonant cavity (2) provided on the substrate (1) in coplanar with the quantum bit, the resonant cavity (2) being coupled with the quantum bit and used for reading quantum state of the quantum bit; wherein the resonant cavity (2) extends spirally from the quantum bit to a direction away from the quantum bit.

2. The quantum device of claim 1, wherein, The quantum bit comprises a Josephson junction (3) and two through holes (4) used for forming a bit capacitance; all the through holes (4) penetrate the substrate (1).

3. The quantum device of claim 2, wherein, The through holes (4) are cylindrical; alternatively, the through holes (4) are rectangular cuboids.

4. The quantum device of claim 2, wherein, The through holes (4) are cylindrical, and the depth-diameter ratio of the through holes (4) is 5-10.

5. The quantum device of claim 3 or 4, wherein, One end of the resonant cavity (2) is coupled with the bit capacitance.

6. The quantum device of claim 1, wherein, The resonant cavity (2) is in the form of a coplanar waveguide.

7. The quantum device of claim 6, wherein, One end of the resonant cavity (2) is open to ground, and the other end is connected to ground.

8. A quantum chip, characterized by The quantum device comprises: the quantum device according to any one of claims 1-7; and a superconducting metal layer provided on the substrate (1) in coplanar with the quantum bit, part of the superconducting metal layer being used for being etched to form the resonant cavity (2); wherein a region of the superconducting metal layer away from the resonant cavity (2) forms a window exposing part of the substrate (1), and the quantum bit is formed in the window.

9. The quantum chip of claim 8, wherein, The region of the superconducting metal layer away from the resonant cavity (2) and the window further forms a read bus; one end of the resonant cavity (2) away from the quantum bit is coupled with the read bus.

10. A quantum computer, comprising: The quantum chip comprises: the quantum chip according to claim 8 or 9.

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