Chip single-line IIC signal analysis method based on function test

Abstract

The invention relates to the technical field of signal analysis, and particularly discloses a chip single-line IIC signal analysis method based on a function test, which comprises the following steps: S1, carrying out dynamic window median filtering on an input signal, effectively eliminating signal jitter and burrs through sliding window dynamic expansion and median replacement, and outputting a smooth digital signal; s2, virtual clock generation is carried out, a time interval sequence is obtained based on jump edge detection, an interval variance is calculated by adopting a sliding window, effective intervals are screened according to a variance threshold, and finally a virtual clock is generated through equal division; s3, sampling in the center of a signal steady-state interval by using the clock, and analyzing sampled data according to an IIC protocol state machine to complete data decoding; the whole process is realized through a pure software algorithm, hardware limitation is broken through, and analysis precision and equipment compatibility are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal analysis, in particular to a chip single-wire IIC signal analysis method based on function test. BACKGROUND

[0002] In the field of automatic testing of integrated circuits, automatic test equipment (ATE) is widely used for function and performance verification of chips (DUTs). Among many chip communication protocols, the IIC (Inter-Integrated Circuit) bus is widely used due to its simple structure and few pins. The traditional IIC bus uses independent serial data lines (SDA) and serial clock lines (SCL) for synchronous communication. However, to further save pin resources, a single-wire IIC protocol has been derived, which combines data and clock signals on a single line for transmission, and no longer provides an independent clock signal.

[0003] This feature poses a serious challenge to the signal capture mechanism of existing ATE machines. Traditional ATE relies heavily on stable, independent clock signals as a sampling reference when capturing DUT signals. For single-wire IIC signals, the lack of this reference makes it impossible for ATE to directly and reliably synchronize and analyze the data signal. Although some high-end ATE machines provide a hardware-based pattern matching (MATCH) function to attempt to capture such signals, this solution is limited by its fixed hardware circuit structure, has inherent defects such as poor flexibility, complex configuration, and inability to adapt to all types of DUTs, resulting in low test coverage and efficiency.

[0004] Therefore, there is an urgent need in the prior art to find a signal analysis method that does not rely on an independent clock signal, can overcome the jitter interference of single-wire IIC signals, and has wide applicability, to achieve efficient and accurate testing of chips using the single-wire IIC protocol. SUMMARY

[0005] The purpose of the present application is to provide a chip single-wire IIC signal analysis method based on function test, which solves the following technical problems.

[0006] The purpose of the present application can be achieved by the following technical solutions: The chip single-wire IIC signal analysis method based on function test comprises the following steps: Step S1: using a dynamic window median filter algorithm to filter the input single-wire IIC signal to eliminate jitter and glitches in the signal, and outputting a smoothed digital signal; Step S2: detecting the jump edge of the smoothed digital signal to obtain a timestamp sequence, obtaining the time interval between the continuous jump edges; obtaining the variance of the time interval by using a sliding window, and screening the time interval based on the variance and a preset variance threshold to filter out noise intervals to obtain effective time intervals; generating a virtual clock signal according to the effective time intervals; Step S3: using the virtual clock signal to perform center sampling on the steady-state interval of the IIC signal to obtain sampling data, and analyzing the sampling data according to an IIC protocol state machine to output decoded IIC data.

[0007] As a further scheme of the present application, the process of the dynamic window median filtering algorithm comprises: Initializing a sliding window, and if the number of data points in the sliding window is insufficient for median calculation, dynamically expanding the boundary of the sliding window, wherein the left boundary of the sliding window is preferentially expanded to the left, and if the left boundary of the sliding window cannot be expanded, the right boundary of the sliding window is expanded to the right.

[0008] As a further scheme of the present application, in the initialization process of the sliding window, the sliding window is 3 by default, and the size of the sliding window is dynamically adjusted based on signal quality.

[0009] As a further scheme of the present application, the setting process of the variance threshold comprises: Obtaining the average value T of each time interval in the current sliding window, and setting the variance threshold as αT, wherein α is a preset configurable parameter and α=0.2.

[0010] As a further scheme of the present application, the process of screening the time interval comprises: For any time interval in the sliding window, if the time interval is greater than the sum of the average value and the variance threshold, or less than the difference between the average value and the variance threshold, the time interval is determined as noise and is filtered out.

[0011] As a further scheme of the present application, the generation process of the virtual clock signal comprises equally dividing the effective time interval filtered of noise to obtain a virtual clock signal with a constant period.

[0012] As a further scheme of the present application, the process of center sampling in the steady-state interval comprises: In one clock period of the virtual clock signal, the smoothed digital signal is sampled at the center position of the clock period.

[0013] As a further scheme of the present application: the process of parsing the sampling data according to the IIC protocol state machine comprises identification and state conversion of a start condition, data bits, a response bit and a stop condition.

[0014] Advantages of the present application: The present application completely gets rid of the dependence on independent clock signals and special hardware matching circuits by the innovative virtual clock generation algorithm, so that the standard ATE test platform can be compatible with various single-wire IIC devices without hardware modification, significantly improving the test coverage and device utilization rate; and the dynamic window median filtering technology can intelligently eliminate the jitter and burr interference in the signal transmission process, effectively restoring the real signal waveform. Combined with the noise interval filtering mechanism based on variance analysis, the accuracy and stability of the virtual clock extraction are ensured, providing a high-integrity signal basis for subsequent data decoding. The key parameters in the method, such as the filtering window size, the variance threshold coefficient α, etc., can be configured by software, so that it can be flexibly adapted to different rates, different signal quality single-wire IIC communication scenes, meet the diversified test requirements, and greatly improve the universality and application value of the method. BRIEF DESCRIPTION OF DRAWINGS

[0015] The present application will be further described below with reference to the accompanying drawings.

[0016] Figure 1 is a step schematic diagram of the single-wire IIC signal analysis method of the chip based on functional testing of the present application; Figure 2 is a signal processing flowchart in the single-wire IIC signal analysis method of the chip based on functional testing of the present application; Figure 3 is a preprocessing flowchart in the single-wire IIC signal analysis method of the chip based on functional testing of the present application; Figure 4 is a clock extraction flowchart in the single-wire IIC signal analysis method of the chip based on functional testing of the present application; Figure 5 is a data decoding flowchart in the single-wire IIC signal analysis method of the chip based on functional testing of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0018] Please refer to Figure 1As shown, the application is a chip single-line IIC signal analysis method based on function test, comprising the following steps: Step S1: using a dynamic window median filtering algorithm to filter the input single-line IIC signal to eliminate jitter and burr in the signal, and output a smoothed digital signal; As a preferred embodiment of the application, the process of the dynamic window median filtering algorithm comprises: initializing a sliding window, if the number of data points in the sliding window is insufficient for median calculation, dynamically expanding the boundary of the sliding window, wherein the left boundary of the sliding window is preferentially expanded to the left, and if the left boundary of the sliding window cannot be expanded, the right boundary of the sliding window is expanded to the right; In the initialization process of the sliding window, the sliding window is 3 by default, and the size of the sliding window is dynamically adjusted based on signal quality; Specifically, a fixed-size sliding window is initialized for the currently processed data point, and when the number of valid data points in the window is insufficient, the window boundary is dynamically expanded, and the expansion logic is: preferentially expanding the left boundary of the window to the left, and if there is no data on the left, expanding the right boundary of the window to the right; left is the direction of the processed historical signal, and right is the direction of the new signal to be processed; the expansion logic aims to preferentially use the confirmed stable signal segment to evaluate the current point, thereby achieving an optimal balance between real-time and accuracy of filtering; The level values of all data points in the current dynamic window are sorted and the median value is taken, and the median value is used to replace the original current data point. This operation can effectively filter out narrow pulse form positive or negative burr, and pull the unstable level caused by jitter back to the stable dominant level state, thereby outputting a smoothed digital signal that eliminates isolated interference points without significantly distorting the original signal edge; It should be noted that in the ATE test environment, signals will introduce random jitter and transient burr, such as ringing. Traditional fixed window filtering or mean filtering will either fail due to insufficient data near the signal edge when processing in real time, or will cause the signal edge to become smooth, i.e. the slope is reduced, which is not conducive to subsequent accurate jump edge detection. Through dynamic window median filtering, especially the preferential left expansion strategy, it is ensured that even at the first point after the signal jump edge, sufficient window data can be obtained for effective filtering. At the same time, the characteristics of median filtering make it extremely effective in eliminating isolated peak burrs, and can well maintain the step edge of the signal. Step S2: detecting the jump edge of the smoothed digital signal to obtain a timestamp sequence, obtaining the time interval between continuous jump edges; obtaining the variance of the time interval by using a sliding window, and screening the time interval based on the variance and a preset variance threshold to filter out noise intervals to obtain effective time intervals; generating a virtual clock signal according to the effective time intervals; Specifically, the jump edge of the smoothed digital signal is detected, the time stamp of each rising edge and falling edge is accurately recorded to form a sequence, and the time interval between continuous jump edges is calculated; in order to solve the core problem that the interval time cannot be directly and stably reconstructed into a clock due to abnormal fluctuations of the interval time caused by residual noise after filtering or non-ideal jump of the signal, a screening mechanism of the interval based on statistical characteristics is introduced; A fixed-size sliding window is defined, and the window is slid on the time interval sequence; for N time intervals in the window, the statistical variance is calculated to quantify the timing stability of the signal; a dynamic variance threshold is set, the threshold is obtained by multiplying the average value of the time intervals in the window by a configurable parameter alpha, the current time interval is compared with the interval, if the current interval is outside the interval, it is determined that the interval is an abnormal interval caused by noise and is filtered out, thereby obtaining a pure sequence composed of effective time intervals; Based on the effective time intervals after filtering out noise, a virtual clock signal with a constant period is generated by equally dividing the effective intervals, and the virtual clock signal is equivalent to an independent SCL clock in the traditional IIC bus, which provides a stable and reliable sampling reference for subsequent data decoding; As a preferred embodiment of the present application, the setting process of the variance threshold comprises: The average value T of each time interval in the current sliding window is obtained, and the variance threshold is set as alpha T, wherein alpha is a preset configurable parameter and alpha=0.2; The process of screening the time interval comprises: For any time interval in the sliding window, if the time interval is greater than the sum of the average value and the variance threshold, or less than the difference between the average value and the variance threshold, the time interval is determined to be noise and is filtered out; As a preferred embodiment of the present application, the generation process of the virtual clock signal comprises equally dividing the effective time intervals after filtering out noise to obtain a virtual clock signal with a constant period; It needs to be explained that, since single-wire IIC has no physical clock line, the core task of the application is to create one out of nothing; even after filtering, there may still be slight timing jitter in the actual signal, or intervals of different lengths caused by the protocol itself, and if these intervals are directly taken as clock periods, a huge timing error will be generated; therefore, the application uses variance analysis and dynamic threshold algorithm to intelligently distinguish the intervals into valid signal transition intervals, invalid noise and abnormal intervals; this ensures that the source data used to generate the clock is clean and representative, thereby synthesizing a virtual clock with high stability; successfully separating the clock information from the merged signal with high precision, breaking through the key bottleneck of single-wire IIC testing, and being able to handle different rates through average processing and different signal quality communication scenarios through variance processing, with strong universality; Step S3: using the virtual clock signal to perform center sampling on the steady-state interval of the IIC signal to obtain sampling data, and parsing the sampling data according to an IIC protocol state machine to output decoded IIC data; Specifically, the virtual clock signal generated in step S2 is used to sample and protocol-analyze the smoothed digital signal output in step S1; this solves the two ultimate problems of how to determine the optimal sampling time to reliably read each bit of data in the absence of hardware clock synchronization, and how to accurately interpret the sampled bit stream as a command and data that meet the IIC standard; As a preferred embodiment of the application, the process of center sampling in the steady-state interval includes: In one clock period of the virtual clock signal, the smoothed digital signal is sampled at the center position of the clock period; Specifically, to avoid the problem that the setup and hold time of the signal near the transition edge does not meet the requirements and possible residual jitter, the sampling point is set at the center of the steady-state interval of each data bit defined by the virtual clock signal; in one virtual clock period, the data signal is sampled once at the time center point of the period; this ensures that the sampling point is far away from the dangerous area of signal change, thereby capturing stable and error-free data bit level values, i.e., 0 or 1, to obtain the original bit stream sequence; As a preferred embodiment of the application, the process of parsing the sampling data according to the IIC protocol state machine includes identifying and state transitioning the start condition, data bit, response bit, and stop condition; Specifically, an IIC protocol state machine is constructed to real-time parse the bit stream sequence, and the IIC protocol state machine sequentially identifies according to the IIC standard communication frame format and performs the following processing: Start condition, detecting the falling edge of the SDA line during the high level of the SCL; Address and data bits, in each subsequent virtual clock cycle, a bit of data is read and the byte is assembled; Acknowledge bits, after each byte (8 bits) transmission, an acknowledge signal (ACK) or non-acknowledge signal (NACK) from the receiver is detected; Stop condition, a rising edge of the SDA line during the SCL high level is detected; The IIC protocol state machine makes state transition according to these specific sequences, so that the start signal, slave address, read / write operation bit, valid data byte and stop signal are accurately separated from the original bit stream, and finally the structured and decoded IIC communication data is output.

[0019] The above has carried out the detailed explanation to one embodiment of the application, but the content is only the preferred embodiment of the application, cannot be considered for limiting the implementation scope of the application. All equivalent changes and improvements made according to the scope of the application should still belong to the inventive scope of the application.

Claims

1. A chip single-wire IIC signal analysis method based on functional testing, characterized in that, Includes the following steps: Step S1: The input single-line IIC signal is filtered using a dynamic window mid-range filtering algorithm to eliminate jitter and glitches in the signal and output a smoothed digital signal. Step S2: Perform edge detection on the smoothed digital signal to obtain a timestamp sequence and the time interval between consecutive edges; use a sliding window to obtain the variance of the time interval, and filter the time interval based on the variance and a preset variance threshold to remove noise intervals and obtain an effective time interval; generate a virtual clock signal based on the effective time interval. Step S3: Using the virtual clock signal, perform center sampling in the steady-state range of the IIC signal to obtain sampled data, and parse the sampled data according to the IIC protocol state machine to output the decoded IIC data.

2. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S1, the process of the dynamic window mid-range filtering algorithm includes: Initialize a sliding window. If the number of data points within the sliding window is insufficient for median calculation, dynamically expand the boundary of the sliding window. Prioritize expanding the left boundary of the sliding window to the left. If the left boundary of the sliding window cannot be expanded further, expand the right boundary of the sliding window to the right.

3. The chip single-wire IIC signal analysis method based on functional testing according to claim 2, characterized in that, In step S1, during the initialization of the sliding window, the sliding window is set to 3 by default, and the size of the sliding window is dynamically adjusted based on the signal quality.

4. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S2, the process of setting the variance threshold includes: Obtain the average value T of each time interval within the current sliding window, and set the variance threshold to αT, where α is a preset configurable parameter and α=0.

2.

5. The chip single-wire IIC signal analysis method based on functional testing according to claim 4, characterized in that, In step S2, the process of filtering the time intervals includes: For any time interval within the sliding window, if the time interval is greater than the sum of the average value and the variance threshold, or less than the difference between the average value and the variance threshold, then the time interval is determined to be noise and is filtered out.

6. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S2, the process of generating the virtual clock signal includes dividing the effective time interval after noise filtering into equal parts to obtain a virtual clock signal with a constant period.

7. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S3, the process of performing center sampling in the steady-state region includes: Within one clock cycle of the virtual clock signal, the smoothed digital signal is sampled at the center of the clock cycle.

8. The chip single-wire IIC signal analysis method based on functional testing according to claim 1, characterized in that, In step S3, the process of parsing the sampled data according to the IIC protocol state machine includes the identification and state transition of the start condition, data bits, response bits, and stop condition.

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