DAC digital calibration circuit and implementation method thereof
By designing a DAC digital calibration circuit and utilizing circuit structures such as multipliers, shift registers, and adders for digital signal processing, the problem of DAC accuracy being affected by process mismatch was solved, achieving high-precision conversion and chip consistency, and reducing system complexity and cost.
Patent Information
- Application Number
- CN202511564113.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-06
AI Technical Summary
The core performance indicators of a DAC are affected by random mismatches during the manufacturing process, causing the conversion characteristics to deviate from the ideal curve. Existing technologies make it difficult to improve accuracy without increasing chip area and power consumption.
The DAC is calibrated using a circuit structure consisting of multipliers, shift registers, adders, selectors, and data registers. This is achieved through digital signal processing to compensate for the inherent errors in the analog section, thus realizing linear correction and zero-point error adjustment.
This improves the conversion accuracy of the DAC, reduces the accuracy differences between different chips, achieves higher chip consistency and system performance, and reduces system complexity and cost.
Smart Images
Figure CN121485689A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design and proposes a design and implementation method for a DAC digital calibration circuit. Background Technology
[0002] As a bridge between digital and analog signals, the performance of a digital-to-analog converter (DAC) directly determines the final quality of a system application. However, the core performance indicators of a DAC are affected by random mismatches during the manufacturing process, causing the conversion characteristics to deviate from the ideal curve.
[0003] In traditional designs, achieving high precision typically involves increasing cell area, using complex analog calibration circuits, or relying on high-precision specialized processes. This not only increases chip area and power consumption but is also difficult to implement using deep submicron processes.
[0004] DAC digital calibration technology further improves accuracy by using digital signal processing. It no longer relies solely on the physical precision of the process components. Instead, it actively measures and compensates for errors caused by inherent mismatches in the analog section using digital signal processing. This technology will be widely used in DAC design.
[0005] Therefore, there is an urgent need for a high-precision digital calibration circuit with a simple structure that can compensate for the inherent errors of the chip. Summary of the Invention
[0006] The purpose of this invention is to design a DAC digital calibration circuit. Employing circuit structures such as multipliers, shift registers, adders, selectors, and data registers, it further improves the conversion accuracy of the DAC through digital signal processing. Using the DAC digital calibration circuit design and implementation method, the raw conversion data from the controller is superimposed with calibration parameters to achieve linear correction and zero-point error adjustment of the DAC. This maximizes the reduction of inherent errors present after the DAC chip is fabricated, meeting the accuracy requirements of DACs in integrated circuit applications and avoiding problems such as user difficulties and system performance impact caused by insufficient DAC accuracy.
[0007] The technical solution adopted by the present invention to achieve the above objectives is: a DAC digital calibration circuit, comprising: The multiplier receives the raw DAC conversion data and slope calibration parameters, performs multiplication operations, and outputs a result with a bit width that includes the DAC bit width and the calibration parameter bit width. The shift register is used to shift the output of the multiplier. The number of bits shifted is equal to the width of the calibration parameter. The width of the result is the DAC width plus the width of the calibration parameter, which yields the fractional multiplication result and completes the slope calibration. The adder is used to add the fractional multiplication result output by the shift register to the zero-point calibration parameter to adjust the zero-point error, and outputs a result containing high-order and low-order bits; the high-order data corresponds to the bit width of the calibration parameter, and the low-order data corresponds to the number of bits of the DAC. The selector is used to receive the output of the adder; if the high-order data is not 0, the full-scale data of all 1s is selected for output; otherwise, the adder result is selected for output. The data register is used to store the output of the selector so that the subsequent analog-to-digital converter can sample it.
[0008] In the multiplier, the output result has a bit width equal to the integer multiplication result. The shift register right-shifts the multiplier output by a number of bits equal to the calibration parameter bit width, resulting in a final bit width equal to the DAC bit width plus the calibration parameter bit width. The zero-point calibration parameter is a setting parameter from the MCU.
[0009] A DAC digital calibration circuit is disposed between the DAC function register of a mode converter and the digital-to-analog converter; the raw DAC conversion data and slope calibration parameters are respectively derived from the DAC special function register and the MCU; the data register outputs the digitally calibrated conversion data to the digital-to-analog converter. It is applied in a DAC, which includes: The MCU is used to control the special function registers according to the instructions of the host computer, write the raw conversion data, and read the slope calibration parameters of digital calibration from the non-volatile memory of the host computer and send them to the DAC digital calibration circuit. Special function registers are used to obtain raw conversion data from the MCU and forward it to the DAC digital calibration circuit; The DAC digital calibration circuit is used to perform conversion processing based on the original conversion data and slope calibration parameters, and generate the adjusted data to be converted. A digital-to-analog converter is used to sample and convert the adjusted data to digital-to-analog conversion.
[0010] A method for implementing a DAC digital calibration circuit includes the following steps: The multiplier receives the raw DAC conversion data and slope calibration parameters, performs the multiplication operation, and outputs a result with a bit width that includes the DAC bit width and the calibration parameter bit width. The shift register performs a shift operation on the output of the multiplier. The number of shift bits is equal to the width of the calibration parameter. The width of the result is the DAC width plus the width of the calibration parameter, thus obtaining the fractional multiplication result and completing the slope calibration. The adder adds the fractional multiplication result output from the shift register to the zero-point calibration parameter to adjust the zero-point error, and outputs a result containing both high and low bits; the high-bit data corresponds to the bit width of the calibration parameter, and the low-bit data corresponds to the number of bits in the DAC. The selector receives the output of the adder; if the high-order data is not 0, it selects the full-scale data of all 1s for output; otherwise, it selects the output of the adder. The data register stores the output of the selector so that the subsequent analog-to-digital converter can sample it.
[0011] The shift register performs a right shift operation on the result output by the multiplier. The number of bits shifted is equal to the width of the calibration parameter, and the resulting bit width is the DAC bit width plus the calibration parameter bit width.
[0012] The raw DAC conversion data and slope calibration parameters come from the DAC function register and the MCU, respectively; the data register outputs the digitally calibrated conversion data to the digital-to-analog converter.
[0013] A method for implementing a digital calibration circuit for a DAC, applied in a DAC, includes the following steps: The MCU controls the special function registers according to the instructions of the host computer, writes the original conversion data, and reads the slope calibration parameters of digital calibration from the non-volatile memory of the host computer and sends them to the DAC digital calibration circuit. The special function register obtains the raw conversion data from the MCU and forwards it to the DAC digital calibration circuit; The DAC digital calibration circuit performs conversion processing based on the original conversion data and slope calibration parameters to generate adjusted data to be converted. The digital-to-analog converter samples and converts the adjusted data to digital.
[0014] The present invention has the following beneficial effects and advantages: 1. This invention designs a digital calibration circuit for a DAC, which can perform actual measurement and analysis on the chip after fabrication to determine the calibration and adjustment parameters, compensate for the chip's inherent errors, and achieve higher precision.
[0015] 2. This invention uses sequential logic circuits to design and implement a digital calibration circuit for a DAC, which is not limited by the physical precision of the process devices. While improving the conversion accuracy of the DAC, it basically does not increase the area and power consumption.
[0016] 3. The digital calibration circuit of the DAC used in this invention can be configured with different calibration parameters according to the individual differences of the chips, which greatly reduces the difference in DAC accuracy caused by process deviations between different chips and achieves higher chip consistency. Attached Figure Description
[0017] Figure 1 The present invention provides a circuit diagram of a DAC digital calibration circuit design and implementation.
[0018] Figure 2A schematic diagram illustrating an application example of this invention in an embedded microcontroller system. Detailed Implementation
[0019] The present invention will now be described in detail with reference to the accompanying drawings.
[0020] like Figure 1 As shown, a DAC digital calibration design implementation circuit includes the following components: multiplier, shift register, adder, selector, and data register. The multiplier circuit performs a multiplication operation on the raw conversion data and slope calibration parameters from the controller. The resulting bit width is the DAC bit width plus the calibration parameter bit width, and the result is an integer multiplication result.
[0021] The shift register circuit right-shifts the multiplier output by a number of bits equal to the calibration parameter bit width. The resulting bit width is the DAC bit width plus the calibration parameter bit width, thus obtaining the fractional multiplication result and completing the slope calibration. By adjusting the bit widths of the multiplier, shift register, and adder, the system can handle input data of different bit widths, thereby improving its applicability. Supporting multiple bit widths allows the use of different DAC specifications in a single design, increasing design versatility. Selecting the appropriate bit width for different application scenarios optimizes performance.
[0022] The adder adds the decimal multiplication result output by the shift register to the zero-point calibration parameter to adjust the zero-point error.
[0023] The selector divides the adder output into two parts: the high-order bit corresponds to the calibration parameter bit width, and the low-order bit corresponds to the DAC bit width. If the high-order bit data is not 0, the full-scale data of all 1s is selected for output; otherwise, the adder output is selected.
[0024] The data register stores the output of the selector, keeping the data stable and facilitating sampling by the analog circuitry of the subsequent DAC.
[0025] This invention comprises a multiplier, a shift register, an adder, a selector, and a data register, reducing system complexity, saving costs, improving the synchronization and consistency of multi-channel systems, and simplifying system design. The extended design supports multi-channel DAC output, enabling calibration of multiple DACs on the same chip, adapting to the needs of multi-channel signal processing.
[0026] like Figure 2 As shown, the DAC digital calibration circuit is applied in the DAC, which includes: The MCU is used to control the special function registers according to the instructions of the host computer, write the raw conversion data, and read the slope calibration parameters of digital calibration from the non-volatile memory of the host computer and send them to the DAC digital calibration circuit. Special function registers are used to obtain raw conversion data from the MCU and forward it to the DAC digital calibration circuit; The DAC digital calibration circuit is used to perform conversion processing based on the original conversion data and slope calibration parameters, and generate the adjusted data to be converted. A digital-to-analog converter is used to sample and convert the adjusted data to digital-to-analog conversion.
[0027] The host computer MCU controls the DAC's special function registers, writes the original conversion data, and reads the zero point and slope adjustment value of digital calibration from the host computer's non-volatile memory. These three data are used as inputs to the DAC digital calibration circuit. After conversion by the digital calibration circuit, the adjusted data to be converted is generated for sampling and digital-to-analog conversion by the subsequent DAC analog circuit.
Claims
1. A DAC digital calibration circuit, characterized by, include: The multiplier receives the raw DAC conversion data and slope calibration parameters, performs multiplication operations, and outputs a result with a bit width that includes the DAC bit width and the calibration parameter bit width. The shift register is used to shift the output of the multiplier. The number of bits shifted is equal to the width of the calibration parameter. The width of the result is the DAC width plus the width of the calibration parameter, which yields the fractional multiplication result and completes the slope calibration. The adder is used to add the fractional multiplication result output by the shift register to the zero-point calibration parameter to adjust the zero-point error, and outputs a result containing high-order and low-order bits; the high-order data corresponds to the bit width of the calibration parameter, and the low-order data corresponds to the number of bits of the DAC. A selector is used to receive the output of the adder; If the high-order data is not 0, then the full-scale data of all 1s is selected for output; otherwise, the adder result is selected for output. The data register is used to store the output of the selector so that the subsequent analog-to-digital converter can sample it.
2. The DAC digital calibration circuit of claim 1, wherein, In the multiplier, the output result has a bit width equal to the integer multiplication result.
3. The DAC digital calibration circuit of claim 1, wherein, The shift register performs a right shift operation on the result output by the multiplier. The number of bits shifted to the right is equal to the width of the calibration parameter, and the resulting bit width is the DAC bit width plus the calibration parameter bit width.
4. The DAC digital calibration circuit of claim 1, wherein, The zero-point calibration parameters are set parameters from the MCU.
5. The DAC digital calibration circuit of claim 1, wherein, It is located between the DAC function register of the mode converter and the digital-to-analog converter; the raw DAC conversion data and slope calibration parameters come from the DAC function register and the MCU, respectively; the data register outputs the digitally calibrated conversion data to the digital-to-analog converter.
6. The DAC digital calibration circuit of claim 1, wherein, Applied in a DAC, the DAC includes: The MCU is used to control the special function registers according to the instructions of the host computer, write the raw conversion data, and read the slope calibration parameters of digital calibration from the non-volatile memory of the host computer and send them to the DAC digital calibration circuit. The DAC function register is used to obtain raw conversion data from the MCU and forward it to the DAC digital calibration circuit. The DAC digital calibration circuit is used to perform conversion processing based on the original conversion data and slope calibration parameters, and generate the adjusted data to be converted. A digital-to-analog converter is used to sample and convert the adjusted data to digital-to-analog conversion.
7. A method for implementing a DAC digital calibration circuit, characterized in that, Includes the following steps: The multiplier receives the raw DAC conversion data and slope calibration parameters, performs the multiplication operation, and outputs a result with a bit width that includes the DAC bit width and the calibration parameter bit width. The shift register performs a shift operation on the output of the multiplier. The number of shift bits is equal to the width of the calibration parameter. The width of the result is the DAC width plus the width of the calibration parameter, thus obtaining the fractional multiplication result and completing the slope calibration. The adder adds the fractional multiplication result output from the shift register to the zero-point calibration parameter to adjust the zero-point error, and outputs a result containing both high and low bits; the high-bit data corresponds to the bit width of the calibration parameter, and the low-bit data corresponds to the number of bits in the DAC. The selector receives the output of the adder; If the high-order data is not 0, then the full-scale data of all 1s is selected for output; otherwise, the adder result is selected for output. The data register stores the output of the selector so that the subsequent analog-to-digital converter can sample it.
8. The method of claim 7, wherein, The shift register right shifts the result of the multiplier output by a shift number of the calibration parameter bit width, and the result bit width is the DAC bit width plus the calibration parameter bit width.
9. The method of claim 7, wherein, The DAC original conversion data and the slope calibration parameter come from a DAC function register and an MCU respectively, and the data register outputs the digital calibrated conversion data to a digital-to-analog converter.
10. The method of claim 7, wherein, The application is applied to a DAC and includes the following steps: The MCU controls a special function register according to an instruction of a host computer, writes original conversion data, reads digital calibrated slope calibration parameters from a nonvolatile memory of the host computer, and sends the parameters to a DAC digital calibration circuit; The DAC function register obtains the original conversion data from the MCU and forwards the data to the DAC digital calibration circuit; The DAC digital calibration circuit converts and processes the original conversion data and the slope calibration parameters to generate adjusted to-be-converted data; The digital-to-analog converter samples and converts the adjusted to-be-converted data.