Android box based on phase-locked loop circuit and low-power-consumption starting circuit

Abstract

The invention discloses an Android box based on a phase-locked loop circuit and a low-power-consumption starting circuit, and relates to the technical field of intelligent terminal peripheral control. Comprising an Android box main body which carries an Android 10 and above operating system, is equipped with a four-core and above architecture CPU, and is at least provided with an HDMI interface and an SPI interface; the low-power-consumption starting circuit comprises an auxiliary frequency locking ring, and an AFLL and a main clock circuit of the Android box are of a parallel connection structure and serve as a core frequency control module in the starting stage. Through a main phase-locked loop and AFLL double-loop parallel architecture, rapid frequency capture within 200 microseconds is realized, and the power consumption is reduced by 70% after AFLL dormancy; and in combination with a phase error offset module, voltage range limitation and PCB electromagnetic isolation design, the peripheral communication error rate is remarkably reduced, and the problem of control interruption caused by slow starting and noise interference of a traditional circuit is solved.

Description

Technical Field

[0001] This invention relates to the field of smart terminal peripheral control technology, and in particular to an Android box based on a phase-locked loop circuit and a low-power startup circuit. Background Technology

[0002] In existing technologies, the interaction and control between Android boxes and smart peripherals has many limitations: In terms of frequency synchronization, most adopt a single phase-locked loop structure, and frequency acquisition during the startup phase relies on point-by-point scanning, which often takes more than 1ms. Moreover, the lack of an auxiliary sleep mechanism in steady state leads to high power consumption. At the same time, insufficient phase noise control makes them susceptible to power fluctuations and electromagnetic interference, causing frequent interruptions in peripheral communication. In terms of protocol adaptation, traditional Android boxes mostly only support preset limited communication protocols, with poor compatibility with emerging protocols such as Bluetooth 5.3, Zigbee, and Matter. New peripherals need to be manually configured with frequency parameters, and the adaptation process is cumbersome and takes more than 30 minutes, making it difficult to achieve unified control of multiple devices. In terms of timing coordination and scene adaptability, existing technologies cannot dynamically adjust the synchronization accuracy for different peripheral types. Audio and video devices often experience audio-visual asynchrony due to excessive phase differences, while industrial control peripherals suffer from operation delays due to synchronization errors exceeding 10μs. Furthermore, there is a lack of frequency drift compensation under wide temperature environments, making it prone to failure outside the range of -20℃ to 85℃, which is difficult to cover the needs of multiple scenarios in both consumer and industrial applications. Summary of the Invention

[0003] The purpose of this invention is to provide an Android box based on a phase-locked loop circuit and a low-power startup circuit, which solves the technical problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: an Android box with a low-power startup circuit, comprising: The main body of the Android box runs on Android 10 or above, is equipped with a quad-core or higher CPU, and has at least one HDMI port and one SPI port. The low-power startup circuit includes an auxiliary frequency lock-in loop (AFLL). The AFLL and the main clock circuit of the Android box adopt a parallel connection structure, serving as the core frequency control module during the startup phase. AFLL is equipped with a frequency sweeping algorithm based on the binary division method, which can reduce the frequency deviation from ±100MHz to ±10kHz within 100μs during the startup phase, so that the total startup time of the Android box from power-on to frequency stabilization is ≤200μs. AFLL also features a sleep trigger mechanism, which automatically enters sleep mode when the phase error of the master clock circuit is detected to be ≤0.1rad.

[0005] Preferably, the AFLL sleep mechanism includes: turning off the power supply of the internal frequency divider, switching to a CLC-like oscillator working mode, and reducing the module power consumption in the sleep state by 70%, from 50mW to 15mW, based on the power consumption during the startup phase.

[0006] Preferably, it also includes a power management unit, which is electrically connected to the AFLL and can dynamically adjust the power supply voltage of the AFLL according to the load rate of the Android box: when the load rate is >80%, the power supply voltage is reduced from 1.8V to 1.2V.

[0007] Preferably, the low-power startup circuit further includes a wake-up module, which can wake up the AFLL from the sleep state to the working state within 50μs when an external wake-up signal is detected.

[0008] Preferably, the EMMC storage module of the Android box body pre-stores a low-power startup parameter table, which includes the AFLL optimal startup frequency parameters under different peripheral access scenarios, so that the startup adaptation time when a new peripheral is connected is ≤3 seconds.

[0009] Android boxes based on phase-locked loop circuits include: The phase-locked loop circuit, together with the AFLL in the low-power startup circuit, forms a dual-loop parallel architecture, including a main phase-locked loop module and a phase error cancellation module; The main phase-locked loop module is composed of a frequency and phase detector, a charge pump, a loop filter and a voltage-controlled oscillator connected in series by electrical connection. It can achieve stable frequency locking in the range of 1MHz to 6GHz. After the AFLL completes the frequency acquisition in the startup phase, it takes over the steady-state frequency control. The phase error cancellation module is a digital compensation circuit, which includes a 16-bit ADC and a digital signal processor. It is connected to the phase difference output terminal of the main phase-locked loop module through a coaxial cable and can convert the phase error into a 0~3.3V compensation voltage and feed it back to the VCO. When the output frequency is 2.4GHz, the phase noise at a frequency deviation of 1MHz is ≤-119.6dBc / Hz.

[0010] Preferably, it also includes a voltage range limiting module, which calibrates the VCO input voltage through a 12-bit DAC, with the VCO center operating voltage as a reference, and the calibration accuracy is ±5mV. It can maintain the circuit lockout state when the power supply voltage fluctuates by ±15%.

[0011] Preferably, the physical distance between the phase-locked loop circuit and the radio frequency circuit of the Android box on the PCB board is ≥3mm, and electromagnetic isolation is achieved by a grounded copper layer with a thickness of ≥0.2mm, with an isolation impedance of ≥100Ω at a test frequency of 1MHz.

[0012] Preferably, it also includes a calibration logic unit, which incorporates a temperature sensor with an accuracy of ±1℃. This unit dynamically compensates for frequency drift in environments ranging from -20℃ to 85℃, triggering compensation when the temperature change exceeds 5℃. The compensation accuracy is ±20ppm, and the frequency deviation is ≤ the target frequency. .

[0013] Preferably, it also includes a programmable frequency synthesizer, which is connected to the Android box CPU via an SPI interface, supports dynamic switching of frequency bands from 1MHz to 6GHz, has a step accuracy of 1Hz, and is compatible with multiple communication protocols such as Bluetooth 5.3, Zigbee, and Matter. Its frequency switching command is triggered by a synchronous clock provided by the phase-locked loop circuit.

[0014] Compared with related technologies, the Android box based on a phase-locked loop circuit and a low-power startup circuit provided by this invention has the following advantages: 1. This invention provides an Android box based on a phase-locked loop circuit and a low-power startup circuit. Through the parallel architecture of the main phase-locked loop and the AFLL dual-loop, it achieves fast frequency acquisition within 200μs, and the power consumption is reduced by 70% after the AFLL goes into sleep mode. Combined with the phase error cancellation module, voltage range limitation and PCB electromagnetic isolation design, it significantly reduces the bit error rate of peripheral communication and solves the control interruption problem caused by slow startup and noise interference in traditional circuits.

[0015] 2. This invention provides an Android box based on a phase-locked loop circuit and a low-power startup circuit. By relying on a multi-protocol abstraction layer and a programmable frequency synthesizer, it is compatible with mainstream protocols such as Bluetooth 5.3 and Zigbee, with a protocol switching latency of ≤50ms. Combined with the intelligent learning function of the TensorFlowLite model, it can automatically adapt to newly connected peripherals within 5 minutes, solving the limitations of traditional Android boxes that have poor protocol compatibility and require manual configuration, and realizing "one box to control all devices in the house".

[0016] 3. This invention provides an Android box based on a phase-locked loop circuit and a low-power startup circuit. By dynamically adjusting the synchronization threshold for different peripherals: ±5ns for audio devices and ≤1μs for industrial PLC devices; combined with edge computing collaboration, cross-screen control and wide temperature compensation, it breaks through the bottlenecks of traditional Android boxes in real-time performance and scene adaptability, covering consumer-grade smart home and industrial-grade control scenarios. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the structure of the phase-locked loop synchronization circuit of the present invention; Figure 2 This is a flowchart illustrating the structure of the intelligent peripheral control method of the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] Example 1: Please see Figures 1-2 The present invention provides a technical solution: an Android box with a low-power startup circuit, comprising: The main body of the Android box runs on Android 10 or above, is equipped with a quad-core or higher CPU, and has at least one HDMI port and one SPI port. The low-power startup circuit includes an auxiliary frequency lock-in loop (AFLL). The AFLL and the main clock circuit of the Android box adopt a parallel connection structure, serving as the core frequency control module during the startup phase. AFLL is equipped with a frequency sweeping algorithm based on the binary division method, which can reduce the frequency deviation from ±100MHz to ±10kHz within 100μs during the startup phase, so that the total startup time of the Android box from power-on to frequency stabilization is ≤200μs. AFLL also features a sleep trigger mechanism, which automatically enters sleep mode when the phase error of the main clock circuit is detected to be ≤0.1rad. AFLL's sleep mechanism includes: turning off the internal frequency divider power supply, switching to a CLC-like oscillator working mode, and reducing the module power consumption in sleep mode by 70%, from 50mW to 15mW, based on the power consumption during startup. In this implementation scheme, AFLL's sleep mechanism combines hardware-level power management with working mode switching to reduce module power consumption from 50mW to 15mW during startup, achieving a 70% power consumption reduction while ensuring stable operation of the main clock circuit. This significantly improves the standby efficiency of the Android box, making it particularly suitable for scenarios with high requirements for low power consumption.

[0020] It also includes a power management unit, which is electrically connected to the AFLL and can dynamically adjust the AFLL's power supply voltage according to the Android box's load rate: when the load rate is >80%, the power supply voltage is reduced from 1.8V to 1.2V; In this implementation scheme, the dynamic voltage adjustment strategy of the power management unit is designed for high load scenarios. When the load rate exceeds 80%, the AFLL supply voltage is reduced from 1.8V to 1.2V to reduce energy consumption while ensuring normal circuit operation, avoid overheating under high load, balance performance and power consumption, and extend the continuous operation time of the device.

[0021] The low-power startup circuit also includes a wake-up module that can wake up the AFLL from sleep state to working state within 50μs when an external wake-up signal is detected. In this implementation, the 50μs fast response capability of the wake-up module ensures that AFLL is quickly activated when it receives an external signal, switching from sleep state to working state, avoiding startup delays that could affect user experience or the timeliness of peripheral communication.

[0022] The EMMC storage module of the Android box contains a low-power startup parameter table, which includes the optimal startup frequency parameters of AFLL under different peripheral access scenarios, so that the startup adaptation time when a new peripheral is connected is ≤3 seconds. In this implementation scheme, the low-power startup parameter table pre-stored in the EMMC storage module covers the optimal frequency parameters of various peripherals such as smart home and industrial control. When a new peripheral is connected, the parameters are automatically matched by identifying the device type, eliminating the need for manual debugging by the user. This reduces the adaptation time of more than 30 minutes in the traditional solution to less than 3 seconds, greatly improving the convenience of multi-device collaborative control.

[0023] Android boxes based on phase-locked loop circuits include: The phase-locked loop circuit, together with the AFLL in the low-power startup circuit, forms a dual-loop parallel architecture, including a main phase-locked loop module and a phase error cancellation module; The main phase-locked loop module consists of a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator connected in series via electrical connections. It can achieve stable frequency locking in the range of 1MHz to 6GHz and takes over steady-state frequency control after the AFLL completes the frequency acquisition during the startup phase. The phase error cancellation module is a digital compensation circuit, which includes a 16-bit ADC and a digital signal processor. It is connected to the phase difference output terminal of the main phase-locked loop module via a coaxial cable and can convert the phase error into a 0~3.3V compensation voltage and feed it back to the VCO. When the output frequency is 2.4GHz, the phase noise at a frequency deviation of 1MHz is ≤-119.6dBc / Hz. In this implementation scheme, the main phase-locked loop module takes over control after frequency acquisition during the startup phase of AFLL. Combined with the 16-bit ADC and digital signal processing capabilities of the phase error cancellation module, the phase noise with a 1MHz frequency offset at 2.4GHz is controlled below -119.6dBc / Hz, effectively reducing signal interference in wireless communication, reducing the data transmission error rate of protocols such as Bluetooth 5.3 and Zigbee, and avoiding peripheral control interruptions.

[0024] It also includes a voltage range limiting module, which calibrates the VCO input voltage through a 12-bit DAC, with the VCO center operating voltage as a reference, and a calibration accuracy of ±5mV. It can maintain the circuit lockout state when the power supply voltage fluctuates by ±15%. In this implementation, the voltage range limiting module achieves a calibration accuracy of ±5mV through a 12-bit DAC, which can stabilize the VCO input voltage under extreme conditions of power supply voltage fluctuation of ±15%, ensure that the phase-locked loop circuit maintains a frequency-locked state, avoid frequency drift caused by voltage instability, and ensure reliable operation of the equipment in complex power supply environments.

[0025] The physical distance between the phase-locked loop circuit and the RF circuit of the Android box on the PCB board is ≥3mm. Electromagnetic isolation is achieved through a grounded copper layer with a thickness of ≥0.2mm. The isolation impedance at a test frequency of 1MHz is ≥100Ω. In this implementation scheme, the physical isolation design between the phase-locked loop circuit and the radio frequency circuit, and the isolation impedance of ≥100Ω, can effectively block the electromagnetic interference of radio frequency signals to the phase-locked loop and prevent the frequency synchronization accuracy from decreasing. Especially in multi-band concurrent communication scenarios, it can ensure the purity and synchronization of signals from various peripherals.

[0026] It also includes a calibration logic unit, which incorporates a temperature sensor with an accuracy of ±1℃. This unit dynamically compensates for frequency drift in environments ranging from -20℃ to 85℃, triggering compensation when the temperature change exceeds 5℃. The compensation accuracy is ±20ppm, and the frequency deviation is ≤ the target frequency. ; In this implementation scheme, the ±1℃ accuracy temperature sensor of the calibration logic unit can monitor the ambient temperature in real time. Within the range of -20℃ to 85℃, when the temperature change exceeds 5℃, compensation is triggered to correct the frequency drift with an accuracy of ±20ppm, ensuring that the device can still work stably in extreme low and high temperature environments, taking into account the needs of both consumer and industrial application scenarios.

[0027] It also includes a programmable frequency synthesizer, which connects to the Android box CPU via an SPI interface, supports dynamic switching of frequency bands from 1MHz to 6GHz, with a step accuracy of 1Hz, and is compatible with multiple communication protocols such as Bluetooth 5.3, Zigbee, and Matter. Its frequency switching command is triggered by a synchronous clock provided by a phase-locked loop circuit. In this implementation scheme, the programmable frequency synthesizer is connected to the CPU via the SPI interface, supports 1Hz step switching in the 1MHz~6GHz frequency band, and can flexibly adapt to multiple protocols such as Bluetooth 5.3, Zigbee, and Matter. With the synchronous clock triggering mechanism provided by the phase-locked loop circuit, it can achieve seamless frequency transition when switching protocols. It can be compatible with new protocol peripherals without hardware upgrades, realizing the multi-scenario application goal of "one box controlling all the devices in the house".

[0028] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the phrase "comprising an element defined as..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0029] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An Android box with low power start-up circuitry, characterized by: It comprises: an Android box body, equipped with an Android 10 and above operating system, equipped with a quad-core and above architecture CPU, at least with 1 HDMI interface and 1 SPI interface; a low-power start-up circuit, including an auxiliary frequency lock loop, AFLL, and the main clock circuit of the Android box adopts a parallel connection structure, as the core frequency control module in the start-up stage; the AFLL is configured with a dichotomy-based sweep algorithm, which can reduce the frequency deviation from ±100MHz to ±10kHz within 100μs in the start-up stage, so that the total start-up time of the Android box from power-on to frequency stabilization is ≤200μs; the AFLL is also provided with a sleep trigger mechanism, which automatically enters a sleep state when the phase error of the main clock circuit is ≤0.1 rad.

2. The Android box of low-power start-up circuit according to claim 1, characterized in that: The sleep mechanism of the AFLL includes: turning off the power supply of the internal frequency divider, switching to a CLC oscillator working mode, and reducing the module power consumption in the sleep state by 70% based on the start-up stage power consumption, from 50mW to 15mW.

3. The Android box of low-power start-up circuit according to claim 1, characterized in that: It also includes a power management unit, which is electrically connected with the AFLL and can dynamically adjust the supply voltage of the AFLL according to the load rate of the Android box: when the load rate is >80%, the supply voltage is reduced from 1.8V to 1.2V.

4. The Android box of low-power start-up circuit according to claim 1, characterized in that: The low-power start-up circuit also includes a wake-up module, which can wake up the AFLL from the sleep state to the working state within 50μs when detecting an external wake-up signal.

5. The Android box of low-power start-up circuit according to claim 1, characterized in that, The EMMC storage module of the Android box body pre-stores a low-power start-up parameter table, which contains the optimal start-up frequency parameters of the AFLL in different peripheral access scenarios, so that the start-up adaptation time when a new peripheral is accessed is ≤3 seconds.

6. The Android box based on the phase-locked loop circuit, applied to the low-power start-up circuit of any one of claims 1-5, characterized in that, It comprises: a phase-locked loop circuit, which forms a double-loop parallel architecture with the AFLL in the low-power start-up circuit, including a main phase-locked loop module and a phase error cancellation module; The main phase-locked loop module is composed of a frequency discriminator, a charge pump, a loop filter and a voltage-controlled oscillator connected in series by electrical connection, which can realize stable frequency locking in the range of 1MHz~6GHz, and take over the stable state frequency control after the AFLL completes the frequency capture in the start-up stage; The phase error cancellation module is a digital compensation circuit, including a 16-bit ADC and a digital signal processor, which accesses the phase difference output end of the main phase-locked loop module through a coaxial cable, and can convert the phase error into a 0~3.3V compensation voltage feedback to the VCO; when the output frequency is 2.4GHz, the phase noise under 1MHz frequency deviation is ≤-119.6dBc / Hz.

7. The phase-locked loop circuit-based Android box of claim 6, wherein: It also includes a voltage range limiting module, which calibrates the VCO input voltage through a 12-bit DAC, with the VCO center working voltage as the reference, the calibration accuracy is ±5mV, and it can maintain the circuit in a locked state when the power supply voltage fluctuates by ±15%.

8. The phase-locked loop circuit-based Android box of claim 6, wherein: The physical distance between the phase-locked loop circuit and the radio frequency circuit of the Android box on the PCB board is ≥3mm, which realizes electromagnetic isolation through a ground copper layer with a thickness of ≥0.2mm, and the isolation impedance under a 1MHz test frequency is ≥100Ω.

9. The phase-locked loop circuit-based Android box of claim 6, wherein: Also include calibration logic unit, the calibration logic unit built-in ±1 ℃ precision temperature sensor, dynamic compensation frequency drift in-20 ℃ ~ 85 ℃ environment, temperature change more than 5 ℃ trigger compensation, compensation accuracy ± 20 ppm, frequency deviation ≤ target frequency .

10. The phase-locked loop circuit-based Android box of claim 6, wherein: Also include a programmable frequency synthesizer, connected with the Android box CPU through the SPI interface, support 1MHz~6GHz frequency band dynamic switching, step precision 1Hz, can adapt to Bluetooth 5.3, Zigbee, Matter multiple communication protocols, and its frequency switching instruction is provided by the phase-locked loop circuit synchronous clock trigger.

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