Simulated EEPROM intelligent management method, device and equipment and storage medium

Abstract

The invention discloses an EEPROM (Electrically Erasable Programmable Read-Only Memory) intelligent management simulation method, device and equipment and a storage medium, and the method comprises the following steps: dividing a Flash memory into a data storage area and a backup data storage area, and constructing a data index structure and a data storage structure; during power-on initialization, a data reading source is determined according to the backup area state of the backup data storage area, and latest valid data is analyzed; when it is detected that the target write-in data is written in, data change is judged through CRC verification, and overflow is processed; the method comprises the following steps: automatically switching to a next erasable area when a write-in exception is detected, optimizing the erasable area according to the data length of target write-in data and a Flash minimum erasure unit, dynamically adjusting a write-in strategy, and reducing the erasure times caused by frequent write-in, thereby prolonging the service life of the Flash memory, improving the response speed of the Flash memory, and improving the reliability of the Flash memory. And the stability and the efficiency of simulating EEPROM intelligent management are improved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a method, apparatus, device, and storage medium for intelligent management of simulated EEPROM. Background Technology

[0002] Traditional Flash memory, while having a larger capacity than electrically erasable programmable read-only memory (EEPROM), has a limited number of erase and write cycles.

[0003] Flash memory typically exhibits slow response speeds under high-frequency read / write conditions, failing to meet the real-time application requirements that necessitate rapid data access.

[0004] Flash memory and EEPROM are widely used in electronic products. The main differences between them lie in their storage principles, erase / write cycles, and speeds. EEPROM is a non-volatile memory that can be programmed and erased under the action of electrical signals. Its characteristic is that it can be erased and written at the byte level. It is usually used to store small amounts of non-volatile data, such as configuration parameters and device status. Flash memory, on the other hand, uses block erasure for data storage. It is usually used to store larger amounts of data and exhibits higher speed and larger storage capacity during data storage and retrieval.

[0005] Traditionally, Flash memory and EEPROM each have their own application scenarios, but they also have some shortcomings. Flash memory usually has the problem of limited write cycles, while EEPROM, although having a longer write life, has a smaller storage capacity and a higher price, so it is not suitable for large-scale data storage. As the requirements of embedded systems continue to increase, how to balance storage capacity, write cycles and power consumption has become an important technical challenge.

[0006] To address this issue, many technical solutions attempt to utilize Flash memory to simulate the characteristics of EEPROM. By adding intelligent management algorithms and optimizing processes such as writing and erasing, Flash memory can maintain a high storage capacity while having a similar long lifespan as EEPROM. Such technical solutions are widely used in embedded systems, especially in the fields of the Internet of Things, smart devices, and automotive electronics.

[0007] Existing technical solutions mainly fall into two categories: Option 1: 1. Predefine an EEPROM data structure containing the data definitions to be stored, used to simulate the data storage of an actual EEPROM; divide the Flash memory into several Flash blocks, each Flash block into several EEPROM storage spaces, and each EEPROM storage space carries an EEPROM data structure; whenever the data in the EEPROM storage space of the current Flash block is modified, the modified data is written to the next EEPROM storage space of the current EEPROM storage space; when the current Flash block is full, the modified data is written to the first EEPROM storage space of the next Flash block; when the last Flash block is full, the modified data is written to the first EEPROM storage space of the first Flash block; each time a data is written, the data number of the current data is incremented by 1.

[0008] Option 2: 1. Predefine an EEPROM data structure, which includes the data definition to be stored, Cyclic Redundancy Check (CRC) data check bits, and data start and end flags to simulate the data storage of an actual EEPROM; divide the Flash into A / B blanks, and divide each blank into several Flash blocks, each Flash block into several EEPROM storage spaces, each EEPROM storage space carrying an EEPROM data structure; whenever the data in the current Flash block's EEPROM storage space is modified, the modified data is written to the next EEPROM storage space of the current EEPROM storage space; when the current Flash block is full, the modified data is written to the first EEPROM storage space of the next Flash block; when the last Flash block is full, the modified data is written to the first EEPROM storage space of the first Flash block; each time a data is written, the data number of the current data is incremented by 1; when the current Blank is full or the data is abnormal, the last set of valid data is copied to another Blank, the current Blank is enabled, and the previously invalid Blank is disabled and erased.

[0009] However, the existing solution has the following drawbacks: Option 1: If the data is not completely written, a power reset will cause abnormal data reading and will affect the next data writing.

[0010] Option 2: When the current Blank is full and a Blank is switched, erasing invalid Blank data takes a long time, which can lead to system timing abnormalities. Summary of the Invention

[0011] The main objective of this invention is to provide a method, apparatus, device, and storage medium for simulating EEPROM intelligent management, aiming to solve the technical problems in the prior art where data loss is caused by write interruption and the lifespan of Flash memory is shortened due to improper erase operation when simulating EEPROM.

[0012] In a first aspect, the present invention provides a simulated EEPROM intelligent management method, the simulated EEPROM intelligent management method comprising the following steps: The Flash memory is divided into a data storage area and a backup data storage area, and a data index structure and a data storage structure are constructed. During power-on initialization, the data read source is determined based on the backup area status of the backup data storage area, and the latest valid data is parsed out. When the write of target data is detected, a CRC check is used to determine the data change and handle the overflow. When an error occurs during writing, the system automatically switches to the next erasable area and optimizes the erasable area based on the data length of the target data to be written and the minimum erasure unit of the Flash memory.

[0013] Optionally, the step of dividing the Flash memory into a data storage area and a backup data storage area, and constructing a data index structure and a data storage structure, includes: The Flash memory is divided into a data storage area and a backup data storage area. The data storage area includes a data area and an index area, and the backup data storage area includes a backup index area and a backup data area. Construct a data index structure based on data type, data size, data status, current data address, and rewritten data address; The data storage structure is constructed based on the data start flag, the specific data, the CRC check bit, and the data end flag.

[0014] Optionally, the step of determining data change and handling overflow through CRC check when target data is detected to have been written includes: When the write of target data is detected, the data type of the target write data is obtained, the corresponding target index value is found according to the data type, and the corresponding Flash address is obtained according to the index value; Determine whether the target index value is empty. If the target index value is empty, obtain the end address of the Flash address corresponding to the latest data. When the target index value is not empty, the write CRC checksum of the target data is compared with the current CRC checksum of the current data; If the written CRC checksum is consistent with the current CRC checksum, it is determined that no data change has occurred. When the written CRC check value is inconsistent with the current CRC check value, it is determined that a data change has occurred; When data changes occur, the remaining length of the data storage area is compared with the current length of the data storage area to determine whether the data storage area has overflowed. When the data storage area overflows, the latest data is migrated to the backup data storage area and the index is updated.

[0015] Optionally, the step of migrating the latest data to the backup data storage area and updating the index when data changes occur and the data storage area overflows includes: When data changes occur, exit the Flash memory write process and obtain the Flash address end address corresponding to the latest data of all data types based on the data address and length of the current data index. Determine whether the data storage area has overflowed based on the Flash address end address; When the data storage area overflows, the latest data is moved to the backup data storage area, and the index value is updated in the backup data storage area.

[0016] Optionally, determining the data read source and parsing the latest valid data based on the backup area status of the backup data storage area during power-on initialization includes: Upon detecting power-on initialization, the backup state of the backup data storage area is obtained; When the backup area is in a state where valid backup data exists, the latest data is read first from the backup data storage area; When the backup area is in a state where no valid backup data exists, the index area of ​​the data storage area is traversed in a loop, and the latest valid data is located and read by reading the latest index value.

[0017] Optionally, obtaining the backup zone status of the backup data storage area upon detecting power-on initialization includes: Upon detecting power-on initialization, the backup area index of the backup data storage area is obtained, and the backup area data is obtained based on the backup area index; Based on the backup area data, determine whether the latest valid backup data is stored in the backup data storage area, and determine the backup area status of the backup data storage area based on the determination result.

[0018] Optionally, when a write error occurs, automatically switching to the next erasable area and optimizing the erasable area based on the data length of the target write data and the minimum erase unit of the Flash memory includes: When an error occurs during writing, the system retrieves the next erasable area and automatically switches to it until the data is successfully written. After detecting that the data was successfully written, the storage address of the target data to be written is updated to the rewritten data address corresponding to the index value of the previous data. During data erasure, the minimum erase unit of the Flash memory is obtained, and the data length of the target data to be written is obtained. The maximum value is then taken based on the data length and the minimum erase unit. The erasure range is determined based on the maximum erasure length, the erasureable area is optimized based on the erasure range, and the erasure operation is performed in the erasureable area.

[0019] Secondly, to achieve the above objectives, the present invention also proposes a simulated EEPROM intelligent management device, the simulated EEPROM intelligent management device comprising: The module is divided into a data storage area and a backup data storage area, and a data index structure and a data storage structure are constructed. The power-on and data reading module is used to determine the data reading source based on the backup area status of the backup data storage area during power-on initialization and to parse out the latest valid data. The data writing module is used to determine data changes and handle overflows by performing CRC checks when the target data is detected being written. The write-erase module is used to automatically switch to the next erasable area when an error occurs during writing, and optimize the erasable area according to the data length of the target write data and the minimum erase unit of Flash.

[0020] Thirdly, to achieve the above objectives, the present invention also proposes a simulated EEPROM intelligent management device, which includes: a memory, a processor, and a simulated EEPROM intelligent management program stored in the memory and executable on the processor. The simulated EEPROM intelligent management program is configured to implement the steps of the simulated EEPROM intelligent management method described above.

[0021] Fourthly, to achieve the above objectives, the present invention also proposes a storage medium storing a simulated EEPROM intelligent management program, wherein the simulated EEPROM intelligent management program, when executed by a processor, implements the steps of the simulated EEPROM intelligent management method described above.

[0022] The proposed intelligent management method for simulated EEPROM divides the Flash memory into a data storage area and a backup data storage area, and constructs a data index structure and a data storage structure. During power-on initialization, the data read source is determined based on the backup data storage area's status, and the latest valid data is parsed out. When target data is detected being written, a CRC check is used to determine data changes and handle overflows. When a write anomaly occurs, the system automatically switches to the next erasable area. The erasable area is optimized based on the target data length and the Flash's minimum erasure unit, dynamically adjusting the write strategy to reduce the number of erase / write cycles caused by frequent writes, thereby extending the Flash memory's lifespan. By optimizing the data storage and read mechanisms, the system improves the Flash memory's responsiveness. To address speed limitations, this solution overcomes performance bottlenecks in high-frequency read / write scenarios, simulating the characteristics of EEPROM while overcoming the inherent shortcomings of Flash memory in these areas. It achieves similar storage characteristics to EEPROM at a lower cost, thus improving system cost-effectiveness. The Flash memory, through an intelligent management scheme simulating EEPROM characteristics, effectively solves issues such as write cycles and real-time storage, adapting to the needs of embedded systems. It completely avoids data loss due to write interruptions, intelligently switching erasable areas and optimizing the erasure range based on data length and the minimum Flash erase unit in case of write anomalies. This significantly reduces unnecessary Flash write / erase cycles, effectively extending memory lifespan and improving system real-time stability, thereby enhancing the stability and efficiency of intelligent management of the simulated EEPROM. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention; Figure 2 This is a flowchart illustrating the first embodiment of the simulated EEPROM intelligent management method of the present invention; Figure 3 This is a flowchart illustrating the second embodiment of the simulated EEPROM intelligent management method of the present invention; Figure 4 This is a schematic diagram of the data index structure in the simulated EEPROM intelligent management method of the present invention; Figure 5 This is a schematic diagram of the data storage structure in the simulated EEPROM intelligent management method of the present invention; Figure 6 This is a flowchart illustrating the third embodiment of the simulated EEPROM intelligent management method of the present invention; Figure 7 This is a schematic diagram illustrating the data storage and allocation process in the simulated EEPROM intelligent management method of the present invention; Figure 8This is a schematic diagram of the data reading process in the simulated EEPROM intelligent management method of the present invention; Figure 9 This is a flowchart illustrating the fourth embodiment of the simulated EEPROM intelligent management method of the present invention; Figure 10 This is a schematic diagram of the data writing process in the simulated EEPROM intelligent management method of the present invention; Figure 11 This is a schematic diagram of the data erasure process in the simulated EEPROM intelligent management method of the present invention; Figure 12 This is a functional block diagram of the first embodiment of the simulated EEPROM intelligent management device of the present invention.

[0024] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0026] The solution of this invention mainly involves: dividing the Flash memory into a data storage area and a backup data storage area, and constructing a data index structure and a data storage structure; determining the data read source based on the backup area status during power-on initialization, and parsing out the latest valid data; detecting target data writes, determining data changes through CRC check and handling overflows; automatically switching to the next erasable area when an abnormal write occurs, optimizing the erasable area based on the data length of the target write data and the minimum erase unit of the Flash memory, dynamically adjusting the write strategy, reducing the number of erase / write cycles caused by frequent writes, thereby extending the lifespan of the Flash memory; improving the response speed of the Flash memory by optimizing the data storage and read mechanisms, solving the performance bottleneck in high-frequency read / write scenarios, and simulating the characteristics of EEPROM. This technology achieves similar storage characteristics to EEPROM at a lower cost, overcoming the shortcomings of Flash memory itself in these aspects and improving the system's cost-effectiveness. The Flash memory simulates EEPROM characteristics through an intelligent management scheme, effectively solving problems such as write cycles and real-time storage, thus meeting the needs of embedded systems. It completely avoids data loss due to write interruptions, intelligently switching erasable areas and optimizing the erasure range based on data length and the minimum erase unit in case of write anomalies. This significantly reduces unnecessary Flash write / erase cycles, effectively extending memory lifespan and improving system real-time stability. It also enhances the stability and efficiency of intelligent management of simulated EEPROM, solving the technical problems of data loss due to write interruptions and shortened Flash lifespan caused by improper erase operations when simulating EEPROM in existing technologies.

[0027] Reference Figure 1 , Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention.

[0028] like Figure 1As shown, the device may include: a processor 1001, such as a CPU; a communication bus 1002; a user interface 1003; a network interface 1004; and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0029] Those skilled in the art will understand that Figure 1 The device structure shown does not constitute a limitation on the device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0030] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating device, a network communication module, a user interface module, and an analog EEPROM intelligent management program.

[0031] The device of the present invention calls the simulated EEPROM intelligent management program stored in the memory 1005 through the processor 1001 and performs the following operations: The Flash memory is divided into a data storage area and a backup data storage area, and a data index structure and a data storage structure are constructed. During power-on initialization, the data read source is determined based on the backup area status of the backup data storage area, and the latest valid data is parsed out. When the write of target data is detected, a CRC check is used to determine the data change and handle the overflow. When an error occurs during writing, the system automatically switches to the next erasable area and optimizes the erasable area based on the data length of the target data to be written and the minimum erasure unit of the Flash memory.

[0032] The device of the present invention, through processor 1001 calling the simulated EEPROM intelligent management program stored in memory 1005, also performs the following operations: The Flash memory is divided into a data storage area and a backup data storage area. The data storage area includes a data area and an index area, and the backup data storage area includes a backup index area and a backup data area. Construct a data index structure based on data type, data size, data status, current data address, and rewritten data address; The data storage structure is constructed based on the data start flag, the specific data, the CRC check bit, and the data end flag.

[0033] The device of the present invention, through processor 1001 calling the simulated EEPROM intelligent management program stored in memory 1005, also performs the following operations: When the write of target data is detected, the data type of the target write data is obtained, the corresponding target index value is found according to the data type, and the corresponding Flash address is obtained according to the index value; Determine whether the target index value is empty. If the target index value is empty, obtain the end address of the Flash address corresponding to the latest data. When the target index value is not empty, the write CRC checksum of the target data is compared with the current CRC checksum of the current data; If the written CRC checksum is consistent with the current CRC checksum, it is determined that no data change has occurred. When the written CRC check value is inconsistent with the current CRC check value, it is determined that a data change has occurred; When data changes occur, the remaining length of the data storage area is compared with the current length of the data storage area to determine whether the data storage area has overflowed. When the data storage area overflows, the latest data is migrated to the backup data storage area and the index is updated.

[0034] The device of the present invention, through processor 1001 calling the simulated EEPROM intelligent management program stored in memory 1005, also performs the following operations: When data changes occur, exit the Flash memory write process and obtain the Flash address end address corresponding to the latest data of all data types based on the data address and length of the current data index. Determine whether the data storage area has overflowed based on the Flash address end address; When the data storage area overflows, the latest data is moved to the backup data storage area, and the index value is updated in the backup data storage area.

[0035] The device of the present invention, through processor 1001 calling the simulated EEPROM intelligent management program stored in memory 1005, also performs the following operations: Upon detecting power-on initialization, the backup state of the backup data storage area is obtained; When the backup area is in a state where valid backup data exists, the latest data is read first from the backup data storage area; When the backup area is in a state where no valid backup data exists, the index area of ​​the data storage area is traversed in a loop, and the latest valid data is located and read by reading the latest index value.

[0036] The device of the present invention, through processor 1001 calling the simulated EEPROM intelligent management program stored in memory 1005, also performs the following operations: Upon detecting power-on initialization, the backup area index of the backup data storage area is obtained, and the backup area data is obtained based on the backup area index; Based on the backup area data, determine whether the latest valid backup data is stored in the backup data storage area, and determine the backup area status of the backup data storage area based on the determination result.

[0037] The device of the present invention, through processor 1001 calling the simulated EEPROM intelligent management program stored in memory 1005, also performs the following operations: When an error occurs during writing, the system retrieves the next erasable area and automatically switches to it until the data is successfully written. After detecting that the data was successfully written, the storage address of the target data to be written is updated to the rewritten data address corresponding to the index value of the previous data. During data erasure, the minimum erase unit of the Flash memory is obtained, and the data length of the target data to be written is obtained. The maximum value is then taken based on the data length and the minimum erase unit. The erasure range is determined based on the maximum erasure length, the erasureable area is optimized based on the erasure range, and the erasure operation is performed in the erasureable area.

[0038] This embodiment, through the above-described scheme, divides the Flash memory into a data storage area and a backup data storage area, and constructs a data index structure and a data storage structure. During power-on initialization, the data read source is determined based on the backup data storage area's status, the latest valid data is parsed, and when target data is detected being written, a CRC check is used to determine data changes and handle overflows. When a write anomaly occurs, the system automatically switches to the next erasable area. The erasable area is optimized based on the data length of the target data and the Flash's minimum erasure unit, dynamically adjusting the write strategy to reduce the number of erase / write cycles caused by frequent writes, thereby extending the Flash memory's lifespan. By optimizing the data storage and read mechanisms, the Flash memory's response speed is improved, and the write speed is reduced. It solves the performance bottleneck in high-frequency read / write scenarios, can simulate the characteristics of EEPROM, and overcomes the shortcomings of Flash memory itself in these aspects. It can achieve similar storage characteristics to EEPROM at a lower cost, thereby improving the system's cost-effectiveness. The Flash memory simulates the characteristics of EEPROM through an intelligent management scheme, which can effectively solve problems such as write cycles and real-time storage, and adapt to the needs of embedded systems. It completely avoids data loss caused by write interruption, intelligently switches erasable areas and optimizes the erasure range based on data length and the minimum erase unit of Flash when write anomalies occur, significantly reducing unnecessary Flash erase / write cycles, effectively extending memory life and improving system real-time stability, and improving the stability and efficiency of intelligent management of simulated EEPROM.

[0039] Based on the above hardware structure, an embodiment of the simulated EEPROM intelligent management method of the present invention is proposed.

[0040] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the simulated EEPROM intelligent management method of the present invention.

[0041] In the first embodiment, the simulated EEPROM intelligent management method includes the following steps: Step S10: Divide the Flash memory into a data storage area and a backup data storage area, and construct a data index structure and a data storage structure.

[0042] It should be noted that by physically dividing the Flash memory into a data storage area and a backup data storage area, and defining the data index structure and data storage structure, a basic architecture is provided for reliable data writing, anomaly recovery, and lifespan optimization.

[0043] Step S20: During power-on initialization, determine the data reading source based on the backup area status of the backup data storage area and parse out the latest valid data.

[0044] It should be understood that during power-on initialization, the system automatically selects the data reading source based on the backup area status, thereby parsing out and saving the latest valid data.

[0045] Furthermore, step S20 specifically includes the following steps: Upon detecting power-on initialization, the backup state of the backup data storage area is obtained; When the backup area is in a state where valid backup data exists, the latest data is read first from the backup data storage area; When the backup area is in a state where no valid backup data exists, the index area of ​​the data storage area is traversed in a loop, and the latest valid data is located and read by reading the latest index value.

[0046] It should be understood that when power-on initialization is detected, the system can check the status of the backup data storage area (e.g., the validity of the backup index) and prioritize reading valid data from the backup area. Otherwise, it can traverse the data area index to restore the latest data, ensuring reliable system startup and avoiding data loss due to write interruption.

[0047] Understandably, during power-on initialization, the status of the backup data storage area is checked. If valid backup data exists, the latest data is read from the backup area first. Otherwise, the data area index area is traversed and the valid data is located and read according to the latest index value. This ensures that the system can reliably restore to the state of the most recent successful write, and completely avoids the risk of data loss due to Flash write interruption (such as power failure).

[0048] Furthermore, the step of obtaining the backup area status of the backup data storage area upon detecting power-on initialization specifically includes the following steps: Upon detecting power-on initialization, the backup area index of the backup data storage area is obtained, and the backup area data is obtained based on the backup area index; Based on the backup area data, determine whether the latest valid backup data is stored in the backup data storage area, and determine the backup area status of the backup data storage area based on the determination result.

[0049] It should be noted that during the power-on initialization phase, the status of the backup data storage area (e.g., the validity of the backup index) is checked first. If the status indicates that there is valid backup data, the latest data is read from the backup area first. Otherwise, the data area index area is traversed, and the latest valid data is located and read by the index value. This ensures that the system can reliably restore to the state of the most recent successful write when it starts up, avoiding data loss or damage caused by Flash write interruption (such as power failure).

[0050] Step S30: When the target data is detected to be written, the data change is determined by CRC check and the overflow is handled.

[0051] It should be noted that during data writing, CRC checks can be used to determine whether the data has been changed and to handle overflow issues, ensuring that the system can reliably recover the latest valid data and avoid data loss due to write interruption.

[0052] Step S40: When an error occurs during writing, automatically switch to the next erasable area and optimize the erasable area according to the data length of the target write data and the minimum erase unit of Flash.

[0053] Understandably, when an anomaly is detected during data writing, the system can automatically switch to the next erasable area and optimize the erasure range by taking the maximum value between the target data length and the minimum erasure unit of the Flash memory, thus ensuring successful writing and extending the lifespan of the Flash memory.

[0054] This embodiment, through the above-described scheme, divides the Flash memory into a data storage area and a backup data storage area, and constructs a data index structure and a data storage structure. During power-on initialization, the data read source is determined based on the backup data storage area's status, and the latest valid data is parsed out. When target data is detected being written, a CRC check is used to determine data changes and handle overflows. When a write anomaly occurs, the system automatically switches to the next erasable area. The erasable area is optimized based on the data length of the target data and the Flash's minimum erasure unit, dynamically adjusting the write strategy to reduce the number of erase / write cycles caused by frequent writes, thereby extending the Flash memory's lifespan. By optimizing the data storage and read mechanisms, the Flash memory's response speed is improved, and the... It solves the performance bottleneck in high-frequency read / write scenarios, can simulate the characteristics of EEPROM, and overcomes the shortcomings of Flash memory itself in these aspects. It can achieve similar storage characteristics to EEPROM at a lower cost, thereby improving the system's cost-effectiveness. The Flash memory simulates the characteristics of EEPROM through an intelligent management scheme, which can effectively solve problems such as write cycles and real-time storage, and adapt to the needs of embedded systems. It completely avoids data loss caused by write interruption, intelligently switches erasable areas and optimizes the erasure range based on data length and the minimum erase unit of Flash when write anomalies occur, significantly reducing unnecessary Flash erase / write cycles, effectively extending memory life and improving system real-time stability, and improving the stability and efficiency of intelligent management of simulated EEPROM.

[0055] Furthermore, Figure 3 This is a flowchart illustrating the second embodiment of the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 3As shown, based on the first embodiment, a second embodiment of the simulated EEPROM intelligent management method of the present invention is proposed. In this embodiment, step S10 specifically includes the following steps: Step S11: Divide the Flash memory into a data storage area and a backup data storage area, wherein the data storage area includes a data area and an index area, and the backup data storage area includes a backup index area and a backup data area.

[0056] It should be noted that the Flash memory is physically divided into a data storage area (including a data area and an index area) and a backup data storage area (including a backup index area and a backup data area), providing an independent storage space foundation for reliable data writing, index management, and anomaly recovery.

[0057] Step S12: Construct a data index structure based on data type, data size, data status, current data address, and rewritten data address.

[0058] It should be understood that FLS is divided into a data storage area (storing current data) and a backup data storage area (storing the latest data when the data storage area is full); the data storage area is further divided into a data area (storing data) and an index area (storing the index corresponding to the data).

[0059] In the specific implementation, see Figure 4 , Figure 4 This is a schematic diagram of the data index structure in the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 4 As shown, the data index structure of the data storage includes data type (data ID, marking data type or ID), data size, data storage status, current data address, and rewritten data address.

[0060] Step S13: Construct a data storage structure based on the data start flag, the specific data, the CRC check bit, and the data end flag.

[0061] It is understandable that a data storage structure can be constructed based on the data start flag, the specific data, the CRC check bit, and the data end flag.

[0062] In the specific implementation, see Figure 5 , Figure 5 This is a schematic diagram of the data storage structure in the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 5 As shown, the data storage structure is as follows: data start flag, specific data, current data CRC checksum, and data end flag.

[0063] This embodiment, through the above-described scheme, divides the Flash memory into a data storage area and a backup data storage area. The data storage area includes a data area and an index area, and the backup data storage area includes a backup index area and a backup data area. A data index structure is constructed based on data type, data size, data status, current data address, and rewritten data address. A data storage structure is constructed based on data start flag, specific data, CRC check bit, and data end flag. This provides a reliable foundation for data writing, change judgment, and anomaly recovery, significantly improving data integrity and system robustness, and effectively avoiding data loss caused by Flash write interruptions.

[0064] Furthermore, Figure 6 This is a flowchart illustrating the third embodiment of the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 6 As shown, based on the first embodiment, a third embodiment of the simulated EEPROM intelligent management method of the present invention is proposed. In this embodiment, step S30 specifically includes the following steps: Step S31: When the target write data is detected, obtain the data type of the target write data, find the corresponding target index value according to the data type, and obtain the corresponding Flash address according to the target index value.

[0065] It should be noted that when data writing is detected, the corresponding index value can be located through the target data type, and the Flash storage address can be obtained based on the index value, thereby ensuring that the data is accurately written to the specified location and avoiding overwriting or writing failure caused by address errors.

[0066] Step S32: Determine whether the target index value is empty. If the target index value is empty, obtain the end address of the Flash address corresponding to the latest data.

[0067] Understandably, when the target index value is empty, the end address of the latest data is obtained by scanning the data end marker of the Flash data area to determine whether subsequent writing will overflow, thus avoiding data overwriting or writing failure.

[0068] Step S33: When the target index value is not empty, compare the write CRC check value of the target data with the current CRC check value of the current data.

[0069] It should be understood that when the target index value is not empty, that is, when the index value is valid, the CRC checksum of the target data to be written can be compared with the CRC checksum of the current data to determine whether the data has been changed, thus avoiding invalid write operations.

[0070] Step S34: When the written CRC check value is consistent with the current CRC check value, it is determined that no data change has occurred.

[0071] It is understandable that when the written CRC check value is consistent with the current CRC check value, it can be determined that no data change has occurred.

[0072] Step S35: When the written CRC check value is inconsistent with the current CRC check value, it is determined that a data change has occurred.

[0073] It should be understood that when the written CRC check value is inconsistent with the current CRC check value, it can be determined that a data change has occurred.

[0074] Step S36: Determine whether the data storage area has overflowed by comparing the remaining length of the data storage with the current length of the data storage.

[0075] Understandably, by comparing the remaining available space length of the data storage area with the current length of the data to be written in real time, if the remaining length is less than the current data length, it is determined that the storage area has overflowed (i.e., the data cannot be completely stored); otherwise, it is determined that the storage space is sufficient and overflow will not occur.

[0076] Step S37: When data changes occur and the data storage area overflows, migrate the latest data to the backup data storage area and update the index.

[0077] Understandably, when data changes and writing would cause the data storage area to overflow, all the latest data can be migrated to the backup data storage area and the index value updated to avoid data overwriting or loss and ensure the continuity of write operations and data integrity.

[0078] Furthermore, step S37 specifically includes the following steps: When data changes occur, exit the Flash memory write process and obtain the Flash address end address corresponding to the latest data of all data types based on the data address and length of the current data index. Determine whether the data storage area has overflowed based on the Flash address end address; When the data storage area overflows, the latest data is moved to the backup data storage area, and the index value is updated in the backup data storage area.

[0079] It should be noted that when the target data is detected to be written, the CRC check can be used to compare the check values ​​of the new and old data to determine whether the data has changed. If the data has changed and the writing may cause an overflow, all the latest data will be moved to the backup data storage area and the index will be updated. During the power-on initialization phase, the system will prioritize reading valid data from the backup area based on the status of the backup data storage area (e.g., the validity of the backup index). Otherwise, it will traverse the data area and index area to obtain the latest data, thereby ensuring that the system can reliably restore the latest valid state when it starts up and avoid data loss or damage caused by Flash write interruption.

[0080] In the specific implementation, see Figure 7 , Figure 7 This is a schematic diagram of the data storage and allocation process in the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 7 As shown, Flash is abbreviated as FLS, emulateEEpromInit refers to the initialization module that simulates EEPROM operation, emulateEEpromRead refers to the read module that simulates EEPROM operation, emulateEEpromWrite refers to the write module that simulates EEPROM operation, and emulateEEpromErase refers to the erase module that simulates EEPROM operation. Data storage allocation, FLS initialization module: 1. When the software is initialized upon power-on, the FLS is initialized.

[0081] 2. When retrieving the data index during initialization, first retrieve the index and data of the backup area, and then determine whether the latest data is stored in the backup area by retrieving the data of the backup area.

[0082] 3. If the latest data is stored in the backup area, then read the data from the backup area. 4. If the latest data is stored in the data area, then iterate through the index area of ​​the FLS data area, read the latest index value, and read the data value through the data address of the index value.

[0083] In the specific implementation, see Figure 8 , Figure 8 This is a schematic diagram of the data reading process in the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 8 As shown, when reading data, the system first obtains the type of the data to be retrieved and then obtains the index value of the data type. Then, based on the data address and length of the current data index, it reads the latest data. If the data has not been stored, the returned data is set to all "0".

[0084] This embodiment, through the above scheme, obtains the data type of the target data when target data is detected being written, finds the corresponding target index value based on the data type, and obtains the corresponding Flash address based on the target index value; determines whether the target index value is empty; if the target index value is empty, obtains the end address of the Flash address corresponding to the latest data; if the target index value is not empty, compares the write CRC checksum of the target data with the current CRC checksum of the current data; if the write CRC checksum matches the current CRC checksum, it is determined that no data change has occurred; if the write CRC checksum matches the current CRC checksum, it is determined that no data change has occurred; if the write CRC checksum matches the current CRC checksum, it is determined that no data change has occurred; When the C checksum is inconsistent, a data change is determined. When a data change occurs and the data storage area overflows, the latest data is migrated to the backup data storage area and the index is updated. When power-on initialization is detected, the data read source is determined according to the backup area status of the backup data storage area, and the latest valid data is parsed out. It can accurately identify data changes through CRC check, avoid invalid write operations, and automatically migrate the latest data to the backup area and update the index when data changes and overflows, ensuring data integrity. During power-on initialization, valid data is restored first according to the backup area status, completely eliminating the risk of data loss caused by Flash write interruption, while optimizing the erasure range to extend the memory life.

[0085] Furthermore, Figure 9 This is a flowchart illustrating the fourth embodiment of the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 9 As shown, based on the first embodiment, a fourth embodiment of the simulated EEPROM intelligent management method of the present invention is proposed. In this embodiment, step S40 specifically includes the following steps: Step S41: When an error occurs during writing, obtain the next erasable area and automatically switch to the next erasable area until the data is successfully written.

[0086] It should be noted that when an abnormal write operation is detected, the system can automatically switch to the next erasable area until the data is successfully written.

[0087] Step S42: After detecting that the data writing is successful, update the storage address of the target written data to the rewritten data address corresponding to the index value of the previous data.

[0088] It should be understood that after data is successfully written, the storage address of the target data can be updated to the "rewrite data address" field of the corresponding data type in the index structure to ensure that subsequent write operations can accurately locate the new data location, avoid address conflicts or overwriting, and maintain data consistency.

[0089] Step S43: During data erasure, obtain the minimum erase unit of the Flash memory and the data length of the target data to be written, and take the maximum value based on the data length and the minimum erase unit of the Flash memory.

[0090] Understandably, during data erasure, the erasure range can be determined by obtaining the minimum erasure unit of the Flash and the target data length, and taking the maximum value. This ensures that the erasure operation is accurate and efficient, and avoids resource waste or shortened Flash life due to improper range.

[0091] Step S44: Determine the erasure range based on the maximum erasure length, optimize the erasureable area based on the erasure range, and perform an erasure operation in the erasureable area.

[0092] It should be understood that dynamic optimization (taking the maximum of the two) based on the target data length and the minimum erase unit of the Flash memory precisely determines the erase range, thereby efficiently completing data writing and avoiding write failures, resource waste, and shortened Flash memory lifespan caused by an erase range that is too large or too small. For specific implementation details, see [link to implementation details]. Figure 10 , Figure 10 This is a schematic diagram of the data writing process in the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 10 As shown: 1. When writing data, first obtain the type of the data being written, and then find the index value of the corresponding data type and the address of the FLS corresponding to the index value.

[0093] 2. Check if the index value is empty. If the index value is empty, retrieve the end address of the FLS address corresponding to the latest data.

[0094] 3. If the index value is not empty, it means that there is currently data stored in FLS. Use the current data and the latest data in FLS to make a judgment. If the data has changed, get the end address of the FLS address corresponding to the latest data; if the data has not changed, exit the FLS write process.

[0095] 4. Determine whether writing current data will result in an overflow of the data area based on the data address of the latest data. If an overflow occurs, move the latest data of all data types to the data backup area and write the index value to the backup index area.

[0096] 5. If no overflow occurs, write the latest data after the current address. If the data writing fails, obtain the address of the next erasable area, erase it, and write the data, until the data is successfully written.

[0097] 6. After the data is successfully written, update the storage address of the current data to the rewritten data address corresponding to the index value of the previous data.

[0098] In the specific implementation, see Figure 11 , Figure 11 This is a schematic diagram of the data erasure process in the simulated EEPROM intelligent management method of the present invention, as shown below. Figure 11 As shown: 1. When erasing data, obtain the address to be erased, obtain the minimum erasure length, and take the maximum value based on the data length & FLS minimum erasure unit.

[0099] 2. If the current address has already been erased, return directly.

[0100] 3. If no erase is performed, an erase instruction is executed. If the erase fails, the next eraseable FLS address is obtained and erased until the erase is successful.

[0101] In practical implementations, some embedded systems use Flash memory to simulate EEPROM functionality. Through programming, a portion of the Flash memory can be divided into "virtual EEPROMs," and byte-level write operations can be implemented through software. Each time data needs to be updated, the data is written to a new location in the Flash memory, and the data in the original location is marked as invalid.

[0102] Suitable for Flash memory storage, the software mimics EEPROM to achieve write-erase balance; during the power-on initialization phase, it reads and parses Flash data to ensure that the latest data can be read normally; when writing data, it checks for changes and only updates if changes are found, reducing the number of writes; it adds a data backup area to ensure that the latest data is not lost due to abnormal erasure; each time the Flash is erased, the erase range is limited according to the minimum erase block and data length, shortening the Flash erase time and preventing the controller from causing system timing abnormalities during erasure; when a data write is abnormal, it will write to the next address block to prevent data loss in the event of a write error.

[0103] Flash memory attempts multiple times during writing to prevent current data from becoming a risk; a reset action is sent during data writing, and the latest data can be retrieved from backup data upon power-up to prevent data loss; erasure is performed in the smallest unit to prevent system timing anomalies caused by erasure.

[0104] Each piece of data has an index, including data type, size, storage status, current data address, and rewritten data address, which helps the system quickly locate the data and reduce storage space waste. Each data structure includes a data start marker, the actual data, a CRC checksum, and a data end marker to ensure data integrity and reduce the difficulty of data recovery. Intelligent block management and wear leveling are implemented to address the write cycle limit of Flash memory, ensuring balanced use of each storage block. Frequent erasing and writing of the same area is avoided, extending the lifespan of the Flash memory.

[0105] The system employs a write exception detection and rewrite mechanism and a data backup area to ensure that data will not be corrupted by power reset. CRC check bits and data end markers are used to ensure data integrity. Based on the actual usage scenario, dynamically adjusting the size of the erase flash can reduce timing delays caused by the erase operation, thereby improving the stability and efficiency of the system.

[0106] This embodiment, through the above-described scheme, automatically switches to the next erasable area when a write error occurs, until the data is successfully written. After successful data writing is detected, the storage address of the target written data is updated to the rewrite data address corresponding to the index value of the previous data. During data erasure, the minimum erase unit of the Flash memory is obtained, and the data length of the target written data is obtained. The maximum value is taken based on the data length and the minimum erase unit. The erasure range is determined based on the maximum erase length, and the erasure area is optimized based on the erasure range. The erasure operation is performed in the erasure area. This allows for automatic switching to the next erasable area to ensure successful writing when a write error occurs. After successful writing, the index rewrite address is accurately updated to maintain data consistency. During data erasure, the erasure range is optimized based on the maximum value of the data length and the minimum erase unit, effectively reducing invalid write operations, significantly extending the life of the Flash memory, and improving system reliability and stability.

[0107] Accordingly, the present invention further provides an analog EEPROM intelligent management device.

[0108] Reference Figure 12 , Figure 12 This is a functional block diagram of the first embodiment of the simulated EEPROM intelligent management device of the present invention.

[0109] In a first embodiment of the simulated EEPROM intelligent management device of the present invention, the simulated EEPROM intelligent management device includes: Module 10 is used to divide the Flash memory into a data storage area and a backup data storage area, and to build a data index structure and a data storage structure.

[0110] The power-on and data reading module 20 is used to determine the data reading source based on the backup area status of the backup data storage area during power-on initialization and to parse out the latest valid data.

[0111] The data writing module 30 is used to determine data changes and handle overflows by means of CRC check when the target data is detected to be written.

[0112] The write-erase module 40 is used to automatically switch to the next erasable area when an error occurs during writing, and to optimize the erasable area according to the data length of the target write data and the minimum erase unit of Flash.

[0113] The steps for implementing each functional module of the simulated EEPROM intelligent management device can be referred to in the various embodiments of the simulated EEPROM intelligent management method of the present invention, and will not be repeated here.

[0114] Furthermore, this embodiment of the invention also proposes a storage medium storing a simulated EEPROM intelligent management program, which, when executed by a processor, performs the operations described in the above-described simulated EEPROM intelligent management method embodiment.

[0115] Those skilled in the art will understand that all or part of the steps in the methods described above can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium is a computer-readable storage medium, including: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program code.

[0116] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0117] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0118] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for simulating EEPROM intelligent management, characterized in that, The analog EEPROM intelligent management method comprises: The flash memory is divided into a data storage area and a backup data storage area, and a data index structure and a data storage structure are constructed; During power-on initialization, the backup area state of the backup data storage area is determined to determine the data reading source, and the latest valid data is parsed out; When target write data is detected to be written, data change is judged by CRC check and overflow is handled; When write exception occurs, the next erasable area is automatically switched to, and the erasable area is optimized according to the data length of the target write data and the minimum erasing unit of the flash.

2. The method of claim 1, wherein the method comprises: The flash memory is divided into a data storage area and a backup data storage area, and a data index structure and a data storage structure are constructed, comprising: The flash memory is divided into a data storage area and a backup data storage area, wherein the data storage area comprises a data area and an index area, and the backup data storage area comprises a backup index area and a backup data area; A data index structure is constructed according to data type, data size, data state, current data address and rewritten data address; A data storage structure is constructed according to data start flag, specific data, CRC check bit and data end flag.

3. The method of claim 1, wherein the method comprises: When target write data is detected to be written, data change is judged by CRC check and overflow is handled, comprising: When target write data is detected to be written, the data type of the target write data is obtained, the corresponding target index value is found according to the data type, and the corresponding flash address is obtained according to the target index value; It is judged whether the target index value is empty, and when the target index value is empty, the end address of the flash address corresponding to the latest data is obtained; When the target index value is not empty, the write CRC check value of the target write data is compared with the current CRC check value of the current data; When the write CRC check value is consistent with the current CRC check value, it is determined that no data change has occurred; When the write CRC check value is inconsistent with the current CRC check value, it is determined that data change has occurred; Whether overflow occurs in the data storage area is judged by comparing the data storage remaining length with the current data length; When data change occurs and overflow occurs in the data storage area, the latest data is migrated to the backup data storage area and the index is updated.

4. The method of claim 3, wherein the method comprises: When data change occurs, the flash memory write process is exited, the flash address end address corresponding to the latest data of all data types is obtained according to the data address and length of the current data index; Whether overflow occurs in the data storage area is judged according to the flash address end address; When overflow occurs in the data storage area, the latest data is migrated to the backup data storage area, and the index value is updated to the backup data storage area. When power-on initialization is performed, the backup area state of the backup data storage area is determined to determine the data reading source, and the latest valid data is parsed out, comprising:

5. The method of claim 1, wherein the method is simulated EEPROM smart management. ​ acquiring a backup area state of the backup data storage area when power-on initialization is detected; when the backup area state is that valid backup data exists, reading the latest data from the backup data storage area preferentially; when the backup area state is that the valid backup data does not exist, circularly traversing an index area of the data storage area, and locating and reading the latest valid data by reading the latest index value.

6. The method of claim 1, wherein the method is simulated EEPROM smart management. The acquiring the backup area state of the backup data storage area when power-on initialization is detected comprises: acquiring a backup area index of the backup data storage area when power-on initialization is detected, and obtaining backup area data according to the backup area index; judging whether the latest valid backup data is saved in the backup data storage area according to the backup area data, and determining the backup area state of the backup data storage area according to a judgment result.

7. The method of claim 1, wherein the method is simulated EEPROM smart management. The automatically switching to a next erasable area when writing is abnormal, and optimizing the erasable area according to a data length of the target write data and a flash minimum erasing unit comprises: acquiring the next erasable area when writing is abnormal, and automatically switching to the next erasable area until data writing is successful; after detecting that data writing is successful, updating a storage address of the target write data to a rewrite data address corresponding to an index value of last data; when data erasing, acquiring a flash minimum erasing unit of the flash memory, and acquiring a data length of the target write data, and taking a maximum value according to the data length and the flash minimum erasing unit; determining an erasing range according to the maximum erasing length, and optimizing the erasable area according to the erasing range, and performing an erasing operation in the erasable area.

8. An analog EEPROM smart management device, characterized by, The analog EEPROM intelligent management device comprises: a division and construction module, configured to divide the flash memory into a data storage area and a backup data storage area, and to construct a data index structure and a data storage structure; a power-on and data reading module, configured to determine a data reading source according to a backup area state of the backup data storage area when power-on initialization is detected, and to parse the latest valid data; a data writing module, configured to, when target write data is detected, judge data change and handle overflow through CRC check; a writing and erasing module, configured to, when writing is abnormal, automatically switch to a next erasable area, and optimize the erasable area according to a data length of the target write data and a flash minimum erasing unit.

9. An analog EEPROM smart management device, characterized in that, The analog EEPROM intelligent management device comprises a memory, a processor, and an analog EEPROM intelligent management program stored in the memory and executable on the processor, the analog EEPROM intelligent management program being configured to implement steps of the analog EEPROM intelligent management method in any one of claims 1 to 7.

10. A storage medium, characterized by The storage medium has an analog EEPROM intelligent management program stored thereon, the analog EEPROM intelligent management program being executable by a processor to implement steps of the analog EEPROM intelligent management method in any one of claims 1 to 7.

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