GPU (Graphics Processing Unit) chip, ray tracing method, graphics card and computer equipment

Abstract

The embodiment of the invention discloses a GPU chip, a ray tracing method, a graphics card and computer equipment, and relates to the field of GPU graphic rendering. The GPU chip comprises a GPU core, an on-chip cache and a cache controller, the on-chip cache is used for storing ray tracing data required by ray tracing calculation; the GPU core is used for sending a data reading instruction to the cache controller; the cache controller is used for reading the ray tracing data from the on-chip cache based on the data reading instruction and sending the ray tracing data to the GPU core; and the GPU core is used for executing ray tracing calculation based on the ray tracing data. By adopting the GPU chip provided by the invention, a large amount of occupation of a GPU core in ray tracing calculation can be avoided, and a relatively high data access speed is achieved.

Description

Technical Field

[0001] This application relates to the field of GPU graphics rendering, and in particular to a GPU chip, a ray tracing method, a graphics card, and a computer device. Background Technology

[0002] Ray tracing is a technique that simulates the propagation of light rays and their interaction with objects to generate realistic rendering effects. The ray tracing process typically requires storing a large amount of data related to ray tracing calculations, such as node data of nodes in the Bounding Volume Hierarchy (BVH). The efficiency of storing and accessing this ray tracing data directly affects rendering performance.

[0003] In related technologies, ray tracing data is typically stored in registers within the GPU core, or in on-chip GPU memory.

[0004] However, the above solutions have significant drawbacks. Storing ray tracing data in registers within the GPU core would result in heavy GPU core usage, significantly reducing the performance of multi-ray parallel computing. Storing ray tracing data in on-chip GPU memory presents high access latency issues, and high-frequency data read / write operations can easily create memory access bottlenecks, leading to reduced GPU computing resource utilization and hindering the real-time performance of ray tracing. Summary of the Invention

[0005] This application provides a GPU chip, a ray tracing method, a graphics card, and a computer device. The technical solution is as follows: On one hand, embodiments of this application provide a GPU chip, the GPU chip including: a GPU core, on-chip cache, and cache controller; The on-chip cache is used to store the ray tracing data required for ray tracing calculations; The GPU core is used to send data read instructions to the cache controller; The cache controller is configured to read the ray tracing data from the on-chip cache based on the data read instruction, and send the ray tracing data to the GPU core; The GPU core is used to perform ray tracing calculations based on the ray tracing data.

[0006] On the other hand, embodiments of this application provide a ray tracing method applied to a GPU chip, the GPU chip including: a GPU core, an on-chip cache, and a cache controller; the method includes: The on-chip cache stores the ray tracing data required for ray tracing calculations. The GPU core sends a data read command to the cache controller. Based on the data read instruction, the ray tracing data is read from the on-chip cache through the cache controller, and the ray tracing data is sent to the GPU core; Based on the ray tracing data, ray tracing calculations are performed through the cache controller.

[0007] On the other hand, embodiments of this application provide a graphics card, which includes a GPU chip and video memory as described above.

[0008] On the other hand, embodiments of this application provide a computer device including a graphics card as described above.

[0009] In this embodiment, the newly added on-chip cache is used to store the ray tracing data required for ray tracing calculations. Since the on-chip cache differs from video memory and registers in the GPU core, when the GPU core sends a data read instruction to the cache controller, the cache controller reads the ray tracing data from the on-chip cache based on the instruction and sends the ray tracing data to the GPU core, enabling the GPU core to perform ray tracing calculations based on the ray tracing data. On one hand, compared to storing ray tracing data in registers within the GPU core in related technologies, this application avoids excessive GPU core usage by storing ray tracing data in the on-chip cache, thereby improving the efficiency of multi-ray parallel computing. On the other hand, compared to storing ray tracing data in video memory in related technologies, the on-chip cache has faster access speed and lower power consumption, thus achieving improved ray tracing calculation performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of ray tracing calculation provided in an exemplary embodiment of this application; Figure 2 This is a schematic diagram of a graphics card structure provided in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of a GPU chip provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram illustrating the allocation of corresponding cache space for a thread bundle, provided by an exemplary embodiment of this application. Figure 5 This is a schematic diagram illustrating the release of cache space provided in an exemplary embodiment of this application; Figure 6 This is a schematic diagram illustrating the creation of a new free entry after releasing cache space, provided by an exemplary embodiment of this application; Figure 7 This is a schematic diagram illustrating the updating of the free entry corresponding to the free cache space after releasing the cache space, provided by an exemplary embodiment of this application. Figure 8 This is a schematic diagram illustrating the updating of the free entry corresponding to the free cache space after releasing the cache space, provided by another exemplary embodiment of this application; Figure 9 This is a flowchart of a ray tracing method provided in an exemplary embodiment of this application; Figure 10 This is a structural block diagram of a ray tracing device provided in an exemplary embodiment of this application; Figure 11 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0013] First, the terms used in the embodiments of this application will be introduced.

[0014] Ray tracing: Light originates from a light source, passes through objects for reflection or refraction, and then enters the human eye. However, forward tracing is extremely inefficient due to the large number of light rays (only a small portion of the light rays actually enter the human eye). Therefore, ray tracing technology uses inverse tracing: starting from the observer (such as a camera or human eye), a virtual ray is emitted to each pixel in the image. The ray propagates through the scene, and when it encounters an object, it splits into reflected light, refracted light, etc., based on the material properties. When the ray finally reaches the light source, the brightness and color of the path are calculated and accumulated onto the corresponding pixel to form the final image.

[0015] Hardware ray tracing and software ray tracing: Ray tracing methods include hardware ray tracing and software ray tracing. Hardware ray tracing refers to the use of a dedicated ray tracing unit (RTU) to perform ray tracing. The RTU is a hardware module within the GPU chip specifically designed for ray tracing. Software ray tracing, on the other hand, does not rely on dedicated ray tracing hardware. It relies entirely on software algorithms to simulate the physical behavior of light propagation and reflection, thereby generating realistic lighting and shadow effects. In other words, ray tracing calculations are performed by software (SW). Generally, SW uses a compute kernel for simulation and compute shaders to implement ray tracing. The ray tracing method provided in this application belongs to software ray tracing.

[0016] Bounding Volume Hierarchy (BVH): When calculating which object a ray intersects with in a 3D scene, BVH is an accelerated algorithm that quickly eliminates invalid collision detection and significantly reduces the amount of ray calculation by creating "hierarchical bounding boxes" for objects in the 3D scene. BVH organizes all objects in the entire 3D scene into a hierarchical structure of "large bounding box → medium bounding box → small bounding box → individual object" to perform ray tracing calculations.

[0017] In related technologies, when calculating which object a ray intersects with in a 3D scene, it's necessary to find the intersection point closest to the ray's origin (i.e., the observer, such as a human eye or camera) within the Bounding Volume Hierarchy (BVH). A BVH contains many nodes, such as nodes corresponding to bounding boxes at various levels, or leaf nodes at the lowest level (corresponding to a small triangular region fitted to a particular object in the scene). Therefore, during ray tracing, a stack is typically used to store the data for each node.

[0018] See Figure 1 , Figure 1 This is a schematic diagram of ray tracing calculation provided in an exemplary embodiment of this application.

[0019] like Figure 1 As shown, taking BVH as a quadtree as an example, each node contains 4 nodes in the next level. The traversal process during ray tracing calculation is as follows.

[0020] Starting from the root node, find the first hit (intersecting with the ray) node 1, and push the remaining four nodes 2, 3, and 4 onto the stack. Then jump to the hit node 1.

[0021] Continuing to test the nodes below node 1, we find that node 7 hit, so we also push node 8 onto the stack.

[0022] Continuing to test node 7, we found that node 23 hit, so we pushed node 24 onto the stack.

[0023] Continuing with testing node 23, it was found that none of the subsequent nodes actually hit the triangle. Therefore, node 24 was popped from the stack.

[0024] Continuing to test node 24, it was found that the triangle it contained did not hit, so node 8 was popped from the stack.

[0025] Continue testing node 8, and find that the triangle it contains has not been hit, so continue popping node 2 from the stack.

[0026] Continuing to test node 2, we found that nodes 10, 11, and 12 were all hit, so we pushed nodes 12 and 11 onto the stack in turn.

[0027] Continuing to test node 10, we found that nodes 26, 27, and 28 were all hit, so we pushed nodes 28 and 27 onto the stack in turn.

[0028] Continuing to test node 26, we found that nodes 41, 42, and 43 were all hit, so we pushed nodes 43 and 42 onto the stack in turn.

[0029] Continue testing node 41, and so on, until you reach node 8193, and then push node 8194 onto the stack.

[0030] Continue testing the triangle 5 contained in node 8193, find a hit, update the current state, and record Triangle5.

[0031] Pop node 8194 from the stack, test node 8194 contains triangle 6, find hit, compare with triangle 5, if triangle 6 is closer to the observer, update the current state and record triangle 6.

[0032] Continue testing in this way until all possible triangles that could be hit have been tested, and the nearest triangle is found.

[0033] In software ray tracing, SolidWorks typically uses a Compute Kernel to simulate the process, and compute shaders to implement the above steps. Below is the stack data structure commonly used by compute shaders.

[0034] / / The traversal data structure used by the Kernel #define STACK_SIZE 64 / / stack size struct TraversalStack { uint32 stackpointer; / / Stack pointer uint32 numEntries; / / Number of stack entries int data[STACK_SIZE]; / / Stack data }; Each ray uses the aforementioned data structure during traversal, where `data` represents the stack data written to the stack. As described above, the shader needs to frequently write and read nodes from this stack, performing push and pop operations. Therefore, the amount of data accessed by each ray to the stack is enormous. Figure 1 For example, suppose BVH has 5 layers and contains 1024 * 1024 triangles. In the worst case, finding a triangle requires searching the box node 5 times. Each search requires storing 3 nodes, and each node needs to store a node index and a node type, totaling 8 bytes. Therefore, the memory size required to read each triangle is: accessBytesPerTriangle = 3 nodes * 8 bytes * 5 times = 120 bytes Similarly, considering the worst-case traversal, which involves traversing every triangle before finding the nearest one, the reading of a ray would be: accessBytesPerRay = 120 bytes * 1024 * 1024 = 120 MB Considering a typical 1080p resolution (1920 * 1080), containing 1920 * 1080 = 2,073,600 rays, the number of stack accesses for a single traversal of the entire screen is: accessBytesPerTraversal=120MB*2073600=243000GB This is clearly an extremely large volume of data access.

[0035] In related technologies, compilers handle the node stack in the following two ways: (1) The stack is placed on the registers within the GPU core, with a portion of the registers reserved for stack use. This approach results in a large amount of register usage. Assuming a core has 1024*32 registers and each warp contains 32 rays, multiple warps can use a maximum of 1024 registers simultaneously. Assuming a stack uses only 64 registers and the shader itself requires 64 registers, this requires 128 registers. The stack limitation means that this core can only run a maximum of 1024 / 128=8 warps simultaneously, while a typical core can run 96 warps, which is a huge waste for the GPU core.

[0036] (2) Putting the stack on the GPU memory can greatly reduce the use of registers and increase the number of warps that a core can run at the same time. However, this will cause a huge access to the GPU memory. Since the access speed to the memory is relatively slow, it will lead to a serious performance drop.

[0037] To address the aforementioned issues, this application introduces an on-chip cache that stores the ray tracing data (i.e., stack data) required for ray tracing calculations. This avoids occupying registers and accessing the on-chip GPU memory, thereby improving performance and reducing power consumption.

[0038] See Figure 2 , Figure 2 This is a schematic diagram of a graphics card structure provided in an exemplary embodiment of this application.

[0039] like Figure 2 As shown, the graphics card 200 mainly consists of a GPU chip 210 and video memory 220. The GPU chip 210 integrates an on-chip cache 201 and a GPU core 202: the on-chip cache 201 stores ray tracing data required for ray tracing calculations (such as ray tracing BVH nodes, traversal stack information, etc.) to improve data access efficiency; the GPU core 202 is the core computing unit that performs graphics rendering, ray tracing, and other computational tasks; and the video memory 220 serves as a large-capacity storage module to hold the data required by the GPU chip.

[0040] Among them, the on-chip cache 201 is a new hardware module added in this application for software ray tracing, and the on-chip cache 201 is different from the registers in the GPU core 202 and also different from the video memory 220.

[0041] It should be noted that the above embodiments only illustrate the general architecture of a graphics card. This structure may include more or fewer components, or combine certain components. This embodiment does not limit this.

[0042] See Figure 3 , Figure 3 This is a schematic diagram of a GPU chip provided in an exemplary embodiment of this application.

[0043] like Figure 3 As shown, the GPU chip 310 includes: a GPU core 303, an on-chip cache 301, and a cache controller 302.

[0044] The on-chip cache 301 is different from the video memory and the registers in the GPU core. For example, the video memory is the on-chip GPU memory, while the on-chip cache 301 is an on-chip cache located on the GPU chip. Therefore, the access speed of the GPU core to the on-chip cache 301 is higher than the access speed to the video memory.

[0045] Optionally, the on-chip cache can be an L2-level on-chip cache on the GPU chip, or an on-chip cache of any other possible storage level, such as an L3-level on-chip cache.

[0046] Optionally, the on-chip cache is SRAM (Static Random Access Memory) or other types of on-chip storage media, such as eDRAM (Embedded Dynamic Random Access Memory).

[0047] Optionally, the on-chip cache can adopt a circular buffer structure or other types of buffer structures, such as a block buffer structure, a queue buffer structure, etc.

[0048] In some embodiments, the on-chip cache is used to store ray tracing data required for ray tracing calculations.

[0049] Optionally, ray tracing data includes node data in the Bounding Volume Hierarchy (BVH), such as the node index and node type.

[0050] Optionally, ray tracing data can also be called stack data.

[0051] In some embodiments, the GPU core may pre-write ray tracing data into an on-chip cache before performing ray tracing calculations on the rays. For example, the GPU core may pre-send a data write instruction to the cache controller, which then writes the ray tracing data indicated by the data write instruction into the on-chip cache.

[0052] In some embodiments, the GPU core is used to send data read instructions to the cache controller.

[0053] For example, when the GPU core begins performing ray tracing calculations on the light rays, the GPU core sends a data read instruction to the cache controller.

[0054] Optionally, the data read instruction may include the read address and the read length.

[0055] Optionally, the data read instruction may also include the register address of a register in the GPU core.

[0056] In some embodiments, the cache controller is used to read ray tracing data from the on-chip cache based on data read instructions and send the ray tracing data to the GPU core.

[0057] Optionally, the cache controller is used to read ray tracing data with a read length from the on-chip cache starting from the read address in the data read instruction, and write the ray tracing data into the register indicated by the register address in the data read instruction; the GPU core reads the ray tracing data from the register.

[0058] In some embodiments, the GPU core is used to perform ray tracing calculations based on ray tracing data.

[0059] For example, in the ray tracing calculation performed by the GPU core, the GPU core determines whether the ray intersects with the bounding box corresponding to the node based on the node data indicated by the ray tracing data. If the ray intersects with the bounding box corresponding to the node, it continues to read the child node information of the node and push it onto the traversal stack until the leaf node is traversed. Then, based on the node data corresponding to the leaf node, it performs the intersection calculation of the ray and the triangle corresponding to the leaf node, thereby completing the geometric traversal and intersection detection process of a single ray.

[0060] In summary, since the newly added on-chip cache in this application is used to store the ray tracing data required for ray tracing calculations, and the on-chip cache is different from the video memory and registers in the GPU core, when the GPU core sends a data read instruction to the cache controller, the cache controller reads the ray tracing data from the on-chip cache based on the data read instruction and sends the ray tracing data to the GPU core, so that the GPU core can perform ray tracing calculations based on the ray tracing data. On the one hand, compared with the related technologies that store ray tracing data in the registers in the GPU core, this application can avoid a large occupation of the GPU core by storing ray tracing data through on-chip cache, thereby improving the efficiency of multi-ray parallel computing. On the other hand, compared with the related technologies that store ray tracing data in video memory, the on-chip cache has a faster access speed and lower power consumption, thus achieving a performance improvement in ray tracing calculations.

[0061] In some embodiments, the GPU core can be used to run different warps.

[0062] In some embodiments, the on-chip cache is allocated to different cache spaces corresponding to different thread bundles.

[0063] The cache space stores the ray tracing data required for performing ray tracing calculations on multiple rays corresponding to a thread bundle.

[0064] As an example only, a GPU core can be used to run thread bundle 1, thread bundle 2, ... thread bundle 16 simultaneously.

[0065] Optionally, a single warp can correspond to multiple rays. For example, one warp can correspond to 32 rays.

[0066] For example only, the on-chip cache contains cache space 1 corresponding to thread bundle 1 (e.g., cache space with addresses 0-1000), which is used to store ray tracing data required for performing ray tracing calculations on rays 1 to 32; the on-chip cache contains cache space 2 corresponding to thread bundle 2 (e.g., cache space with addresses 1001-2000), which is used to store ray tracing data required for performing ray tracing calculations on rays 33 to 64.

[0067] In some embodiments, the GPU core is used to send data read instructions corresponding to the thread bundle to the cache controller.

[0068] Optionally, the data read instruction includes the read address in the on-chip cache, the read length, and the register address of the register.

[0069] Optionally, the data read instruction can also be called the LDS (Local Data Share) instruction, which is the instruction to read ray tracing data from the on-chip cache.

[0070] For illustrative purposes only, a data read command can be represented as follows.

[0071] LDS Dst, Offset, Size.

[0072] The LDS instruction, or Data Read instruction, is used to read ray tracing data from the on-chip cache and write it to a register in the GPU core. Dst represents the register address. Offset represents the offset relative to the starting address of the allocated on-chip cache (equivalent to the read address). Size represents the length of the ray tracing data to be read (equivalent to the read length).

[0073] In some embodiments, the cache controller is used to read the ray tracing data corresponding to the thread bundle from the cache space corresponding to the thread bundle in the on-chip cache based on the data read instruction corresponding to the thread bundle, and send the ray tracing data to the GPU core.

[0074] Optionally, the cache controller is used to read ray tracing data from the on-chip cache based on data read instructions and write the ray tracing data to registers in the GPU core.

[0075] Optionally, the cache controller is used to read ray tracing data with a read length from the read address in the on-chip cache based on a data read instruction, and write the ray tracing data into the register corresponding to the register address in the GPU core.

[0076] In some embodiments, the GPU core is used to perform ray tracing calculations on multiple rays corresponding to a thread bundle based on ray tracing data.

[0077] Optionally, the GPU core is used to read ray tracing data from registers and perform ray tracing calculations.

[0078] To ensure that different thread bundles correspond to different cache spaces, in some embodiments, the GPU core needs to pre-control the cache controller to allocate corresponding cache spaces for different thread bundles.

[0079] In some embodiments, the GPU core is used to send allocation instructions corresponding to thread bundles to the cache controller.

[0080] In one possible implementation, the GPU core includes a Warp Resource Manager (allocation management unit) for allocating cache space corresponding to thread bundles.

[0081] In some embodiments, the allocation management unit is used to determine the cache capacity corresponding to the thread bundle and send an allocation instruction containing the thread bundle identifier and the cache capacity to the cache controller.

[0082] Optionally, the allocation management unit in the GPU core is used to determine the first cache capacity corresponding to the thread bundle.

[0083] For example, the GPU core determines the cache capacity corresponding to the cache space to be 1000 through Warp Resource Manager.

[0084] Optionally, the allocation management unit in the GPU core is used to send allocation instructions containing thread bundle identifiers and cache capacity to the cache controller.

[0085] Optionally, the GPU core sends allocation instructions corresponding to thread bundles to the cache controller via the Warp Resource Manager.

[0086] The allocation instruction is used to indicate the allocation of cache space for the thread bundle.

[0087] Optionally, the allocation instructions include the thread bundle identifier and the cache capacity.

[0088] Among them, the thread bundle identifier can also be called the warp ID, and the cache capacity can be called the warp size.

[0089] In some embodiments, the cache controller is used to allocate cache space for thread bundles from the on-chip cache based on allocation instructions.

[0090] Optionally, the cache controller is used to determine a cache space that meets the cache capacity from the free cache space of the on-chip cache based on the cache capacity in the allocation instruction.

[0091] Optionally, the cache controller contains a record table, which is used to record free cache space.

[0092] In one possible implementation, the cache controller can look up free cache space that meets the cache capacity from the record table and allocate cache space from the free cache space.

[0093] Optionally, the cache controller is used to allocate cache space for the thread bundle corresponding to the thread bundle identifier based on the thread bundle identifier in the allocation instruction.

[0094] Optionally, the record table can be used to record the cache space allocated for thread bundles.

[0095] Optionally, the cache controller is used to update free cache space based on cache space.

[0096] For example, if the original free cache space in the record table is the cache space with addresses 0-10000 (in the initial state, the entire on-chip cache is free cache space), and the first allocation instruction indicates that the first cache capacity of the first cache space is 1000, then the cache controller will divide the cache space with addresses 0-1000 into the first cache space and update the free cache space to the cache space with addresses 1001-10000.

[0097] See Figure 4 , Figure 4 This is a schematic diagram illustrating the allocation of corresponding cache space for a thread bundle, provided by an exemplary embodiment of this application.

[0098] like Figure 4As shown, the GPU chip includes an on-chip cache 410, a cache controller 420, and a GPU core 430.

[0099] Among them, the on-chip cache 410 is the L2 level on-chip cache (SRAM) on the GPU chip, and the on-chip cache adopts a circular buffer structure, that is, the on-chip cache SRAM is connected end to end in the form of a ring buffer.

[0100] The capacity of the on-chip cache can be determined by those skilled in the art based on actual needs. Since the purpose of setting up an on-chip cache is to reduce register usage and avoid placing stack data in video memory, those skilled in the art can determine the on-chip cache capacity based on the maximum number of warps that the GPU core can run simultaneously. For example, if the maximum number of running warps is 128, and each ray requires 64 registers to store stack data, then the on-chip cache would need 128 warps * 64 registers * 32 threads per warp = 1024 KB = 1 MB.

[0101] In some embodiments, in the memory hierarchy architecture of a GPU chip, the memory hierarchy of the on-chip cache is lower than that of the registers in the GPU core, and the memory capacity of the on-chip cache is higher than that of the registers.

[0102] Optionally, the on-chip cache can be an L2-level on-chip cache on the GPU chip, or an on-chip cache of any other possible storage level, such as an L3-level on-chip cache.

[0103] Optionally, the on-chip cache is SRAM (Static Random Access Memory) or other types of on-chip storage media, such as eDRAM (Embedded Dynamic Random Access Memory).

[0104] Optionally, the on-chip cache can adopt a circular buffer structure or other types of buffer structures, such as a block buffer structure, a queue buffer structure, etc.

[0105] The on-chip cache 410 is shared by different thread bundles running on the GPU core. The on-chip cache 410 has already allocated corresponding cache spaces for thread bundles warp#1, warp#2, warp#3, warp#4, warp#5, warp#6, warp#7, warp#8, warp#9, warp#10, warp#11, and warp#12. The remaining free cache spaces include empty#1, empty#2, empty#3, empty#4, and empty#5. The cache controller 420 records the start pointer and length of each of these five free cache spaces in a record table.

[0106] GPU core 430 includes allocation management unit 431. When it is necessary to allocate corresponding cache space for a new thread bundle (such as warp#13), allocation management unit 431 first determines the cache capacity (such as 200) corresponding to the thread bundle, and then sends the thread bundle allocation instruction to cache controller 420.

[0107] The allocation instruction includes the thread bundle identifier (e.g., warp#13) and the cache capacity (e.g., 200).

[0108] In some embodiments, the cache controller 420 allocates corresponding cache space to the thread bundle based on allocation instructions.

[0109] Optionally, the cache controller 420 determines the cache space that meets the cache capacity from the various free cache spaces recorded in the record table and allocates it to the thread bundle.

[0110] For example only, if the starting address of empty#4 is 1000, the length is 500, and the cache capacity is 200, then empty#4 meets the cache capacity requirement. The cache controller 420 allocates cache space from empty#4 (e.g., starting address 1000, length 200) and updates empty#4. The updated empty#4 then has a starting address of 1201 and a length of 300.

[0111] In one possible scenario, the cache controller is used to send a successful allocation notification for the thread bundle to the GPU core after allocating cache space for the thread bundle from the on-chip cache based on the allocation instruction.

[0112] For example, if there is sufficient cache space in the free cache space to meet the cache capacity, the cache controller allocates cache space for the thread bundle and sends a successful allocation notification for the thread bundle to the allocation management unit in the GPU core.

[0113] Optionally, the allocation success notification corresponding to the thread bundle includes the thread bundle identifier (warp ID), such as warp#13.

[0114] In one possible scenario, the cache controller is used to send an allocation failure notification corresponding to the thread bundle to the GPU core when the capacity of the free cache space is insufficient to meet the cache capacity.

[0115] For example, if the length of each free cache interval recorded by the cache controller 420 in the record table is less than the cache capacity (e.g., 200), the cache controller 420 sends an allocation failure notification corresponding to the thread bundle to the allocation management unit 431.

[0116] Optionally, the allocation failure notification corresponding to the thread bundle includes the thread bundle identifier (warp ID), such as warp#13.

[0117] In some embodiments, the GPU core is configured to resend the allocation instruction to the cache controller if it receives an allocation failure notification corresponding to a thread bundle and a preset time period has elapsed.

[0118] Optionally, the preset duration can be a duration pre-set by the GPU core, such as 0.5s.

[0119] For example, after 0.5 seconds, some thread bundles will have completed their ray tracing calculations, and the cache space corresponding to the thread bundles will be released. At this time, there may be a cache space in the free cache space that meets the cache capacity.

[0120] In this embodiment, the allocation management unit in the GPU core can control the cache controller to allocate cache space sufficient for the thread bundle by sending thread bundle allocation instructions to the cache controller. This allows the ray tracing data corresponding to the thread bundle to be written into the cache space, providing the prerequisite for reading ray tracing data from the cache space during subsequent ray tracing calculations. After allocating cache space for the thread bundle, the cache controller updates the free cache space based on the allocated cache space, achieving accurate maintenance and management of the free cache space.

[0121] After allocating corresponding cache space for a thread beam, the GPU core can control the writing of the ray tracing data corresponding to the thread beam into the cache space for subsequent reading.

[0122] In some embodiments, the GPU core is used to send data write instructions to the cache controller.

[0123] The data write command is used to instruct the writing of ray tracing data.

[0124] Optionally, the GPU core is used to send data write instructions corresponding to the thread bundle to the cache controller.

[0125] In some embodiments, a cache controller is configured to write ray tracing data to an on-chip cache based on a data write instruction.

[0126] Optionally, a cache controller is used to write ray tracing data to the cache space corresponding to the thread bundle based on data write instructions.

[0127] Optionally, the data write command includes the ray tracing data to be written, the write address, and the write length.

[0128] Optionally, the data write command can also be called the Store to Shared (STS) command.

[0129] For illustrative purposes only, a data write command can be represented as follows.

[0130] STS Offset, Data, Size.

[0131] The STS instruction, or data write instruction, is used to write ray tracing data to the on-chip cache. Offset represents the offset relative to the starting address of the allocated on-chip cache (equivalent to the write address). Data represents the ray tracing data to be written. Size represents the length of the ray tracing data to be written (equivalent to the write length).

[0132] In some embodiments, the cache controller is used to write the ray tracing data to be written in the data writing instruction into the on-chip cache, which has a write length starting from the write address.

[0133] For example, the cache controller writes the node data to be written in thread bundle wrap#13 into a cache space with a length of 100, starting from the write address of the cache space corresponding to wrap#13 in the on-chip cache, where the length of the node data to be written is 100.

[0134] After ray tracing data is written to the cache space, the GPU core can read the ray tracing data from the on-chip cache through the cache controller when the data needs to be read, based on the Data Reading (LDS) instruction, to perform ray tracing calculations.

[0135] The following section describes the software modifications.

[0136] The software modifications include compiler changes. The shader no longer needs `data` in the stack definition; it only needs `stackpointer` to point to the stack location and `numEntries` to represent the total number of items pushed onto the stack.

[0137] As an example only, the traversal data structure used by the Kernel (i.e., the data structure for ray tracing data) can be represented in the following form.

[0138] struct TraversalStack { uint32 stackpointer; uint32 numEntries; }; In this case, the definition of the stack no longer needs int data[STACK_SIZE] to store ray tracing data.

[0139] In terms of instructions, it can be implemented as follows, with an example illustrating the reading of the stack.

[0140] / / Shader code: struct TraversalStack { uint32 stackpointer; uint32 numEntries;}; } uint32 nodeIndex = stack[stackpointer]; uint32 nodeType = stack[stackpointer+1]; / / Assembly code Mov Temp0 stackpointer / / Temp0 represents the stack address of the stackpointer. Mov Temp1 1 Add Temp2 Temp0 Temp1 / / Temp1 represents the stack address of stackpointer+1 LDS Temp3 Temp0, 4 / / The node index is stored in SRAM[stackpointer] and read out into Temp3 LDS Temp4 Temp2, 4 / / Node type is stored in SRAM at location [stackpointer+1], and read out and put into Temp4 Here, Temp represents a register in the GPU core, and stackpointer represents the stack pointer.

[0141] After the ray tracing calculations for a thread bundle are completed, the cache space corresponding to the thread bundle in the on-chip cache needs to be released so that other thread bundles can utilize the cache space in the future.

[0142] In some embodiments, the GPU core is used to send a release instruction (Free instruction) corresponding to the thread bundle to the cache controller after performing ray tracing calculations on multiple rays corresponding to the thread bundle.

[0143] The release instruction is used to instruct the release of the cache space corresponding to the thread bundle.

[0144] In one possible implementation, the GPU core includes a Warp Resource Manager (allocation management unit) for allocating and releasing cache space corresponding to thread bundles.

[0145] Optionally, the allocation management unit in the GPU core is used to send release instructions corresponding to thread bundles to the cache controller.

[0146] Optionally, the release instruction includes the thread bundle identifier corresponding to the thread bundle.

[0147] In some embodiments, the cache controller is used to release the cache space corresponding to the thread bundle from the on-chip cache based on a release instruction.

[0148] For example, the cache controller releases the cache space corresponding to the thread bundle based on the thread bundle identifier contained in the release instruction, and uses it as free cache space.

[0149] See Figure 5 , Figure 5 This is a schematic diagram illustrating the release of cache space provided in an exemplary embodiment of this application.

[0150] like Figure 5 As shown, the GPU chip includes an on-chip cache 510, a cache controller 520, and a GPU core 530.

[0151] After performing ray tracing calculations on the multiple rays corresponding to the thread bundle, the allocation management unit 531 in the GPU core 530 sends a release instruction corresponding to the thread bundle to the cache controller 520.

[0152] The cache controller 520 releases the cache space corresponding to the thread bundle from the on-chip cache based on the release instruction and updates the free cache space.

[0153] Optionally, after releasing the cache space, the cache controller 520 may send a release success notification to the allocation management unit 531.

[0154] Regarding the specific method of releasing the cache space corresponding to the thread bundle and updating the free cache space, in some embodiments, the cache controller is used to create a new free entry if there is no adjacent free cache space after the cache space is released.

[0155] The newly added free entries are used to record the cache space after it has been released.

[0156] Optionally, the new free entry may include the starting address and length information of the freed cache space.

[0157] See Figure 6 , Figure 6 This is a schematic diagram illustrating the creation of a new free entry after releasing cache space, provided by an exemplary embodiment of this application.

[0158] like Figure 6 As shown, the cache space corresponding to warp#3 in the on-chip cache does not have an adjacent free cache space (its adjacent cache space has been allocated to the cache spaces corresponding to warp#2 and warp#4). Therefore, the cache controller creates a new free entry empty#6 to record the freed cache space.

[0159] Optionally, the new free entry may include the starting address and length information of the freed cache space.

[0160] In some embodiments, the cache controller is used to update the free entry corresponding to the free cache space when there is an adjacent free cache space after the cache space is released.

[0161] The updated free entries are used to record the space after the freed cache space is merged with the adjacent free cache space.

[0162] See Figure 7 , Figure 7 This is a schematic diagram illustrating the updating of the free entry corresponding to the free cache space after releasing the cache space, provided by an exemplary embodiment of this application.

[0163] like Figure 7 As shown, the cache space corresponding to thread warp#11 in the on-chip cache has adjacent free cache spaces (including empty#3 and empty#2). Therefore, the cache controller updates the free entries of empty#3 and empty#2.

[0164] The updated scope of the original empty#2 entry record is expanded to include the cache spaces corresponding to the original empty#2, original empty#3, and original warp#11. The original empty#3 entry is deleted after the update, so that the cache spaces corresponding to the original empty#2, original empty#3, and original warp#11 are all merged into the new cache space corresponding to empty#2.

[0165] See Figure 8 , Figure 8 This is a schematic diagram illustrating the updating of the free entry corresponding to the free cache space after releasing the cache space, provided by another exemplary embodiment of this application.

[0166] like Figure 8 As shown, the cache space corresponding to warp#1 in the on-chip cache has an adjacent free cache space (empty#4). Therefore, the cache controller updates the free entry of empty#4.

[0167] In this update, the scope of the original empty entry record for empty#4 is expanded to include the cache space corresponding to the original empty#4 and the original warp#1, to show that the cache space corresponding to the original empty#4 and the original warp#1 has been merged into the new cache space corresponding to empty#4.

[0168] In this embodiment, by releasing the cache space corresponding to the thread bundle in the on-chip cache, and creating a new free entry when there is no adjacent free cache space after the release, and updating the free entry corresponding to the free cache space when there is an adjacent free cache space after the release, other thread bundles that are executed subsequently can utilize the cache space, thereby improving the utilization rate of the on-chip cache.

[0169] See Figure 9 , Figure 9 This is a flowchart of a ray tracing method provided in an exemplary embodiment of this application.

[0170] In some embodiments, the method is applied to a GPU chip, which includes a GPU core, an on-chip cache, and a cache controller.

[0171] On-chip cache differs from video memory and registers within the GPU core. For example, video memory is on-chip GPU memory, while on-chip cache is cache located on the GPU chip itself. Therefore, the GPU core can access the on-chip cache at a faster speed than it can access video memory.

[0172] In some embodiments, in the memory hierarchy architecture of a GPU chip, the memory hierarchy of the on-chip cache is lower than that of the registers in the GPU core, and the memory capacity of the on-chip cache is higher than that of the registers.

[0173] Optionally, the on-chip cache can be an L2-level on-chip cache on the GPU chip, or an on-chip cache of any other possible storage level, such as an L3-level on-chip cache.

[0174] Optionally, the on-chip cache is SRAM (Static Random Access Memory) or other types of on-chip storage media, such as eDRAM (Embedded Dynamic Random Access Memory).

[0175] Optionally, the on-chip cache can adopt a circular buffer structure or other types of buffer structures, such as a block buffer structure, a queue buffer structure, etc.

[0176] The method includes the following steps.

[0177] Step 901: Store the ray tracing data required for ray tracing calculations in the on-chip cache.

[0178] Optionally, ray tracing data includes node data in the Bounding Volume Hierarchy (BVH), such as the node index and node type.

[0179] Optionally, ray tracing data can also be called stack data.

[0180] In some embodiments, the GPU core may pre-write ray tracing data into an on-chip cache before performing ray tracing calculations on the rays. For example, the GPU core may pre-send a data write instruction to the cache controller, which then writes the ray tracing data indicated by the data write instruction into the on-chip cache.

[0181] Step 902: Send a data read command to the cache controller via the GPU core.

[0182] For example, when the GPU core begins performing ray tracing calculations on the light rays, the GPU core sends a data read instruction to the cache controller.

[0183] Optionally, the data read instruction may include the read address and the read length.

[0184] Optionally, the data read instruction may also include the register address of a register in the GPU core.

[0185] Step 903: Based on the data read instruction, read the ray tracing data from the on-chip cache through the cache controller and send the ray tracing data to the GPU core.

[0186] Optionally, the cache controller is used to read ray tracing data with a read length from the on-chip cache starting from the read address in the data read instruction, and write the ray tracing data into the register indicated by the register address in the data read instruction; the GPU core reads the ray tracing data from the register.

[0187] Step 904: Based on the ray tracing data, perform ray tracing calculations through the GPU core.

[0188] For example, in the ray tracing calculation performed by the GPU core, the GPU core determines whether the ray intersects with the bounding box corresponding to the node based on the node data indicated by the ray tracing data. If the ray intersects with the bounding box corresponding to the node, it continues to read the child node information of the node and push it onto the traversal stack until the leaf node is traversed. Then, based on the node data corresponding to the leaf node, it performs the intersection calculation of the ray and the triangle corresponding to the leaf node, thereby completing the geometric traversal and intersection detection process of a single ray.

[0189] In summary, since the newly added on-chip cache in this application is used to store the ray tracing data required for ray tracing calculations, and the on-chip cache is different from the video memory and registers in the GPU core, when the GPU core sends a data read instruction to the cache controller, the cache controller reads the ray tracing data from the on-chip cache based on the data read instruction and sends the ray tracing data to the GPU core, so that the GPU core can perform ray tracing calculations based on the ray tracing data. On the one hand, compared with the related technologies that store ray tracing data in the registers in the GPU core, this application can avoid a large occupation of the GPU core by storing ray tracing data through on-chip cache, thereby improving the efficiency of multi-ray parallel computing. On the other hand, compared with the related technologies that store ray tracing data in video memory, the on-chip cache has a faster access speed and lower power consumption, thus achieving a performance improvement in ray tracing calculations.

[0190] See Figure 10 , Figure 10 This is a structural block diagram of a ray tracing device provided in an exemplary embodiment of this application. The device includes: Storage module 1101 is used to store ray tracing data required for ray tracing calculations via on-chip cache; The read module 1002 is used to send data read commands to the cache controller through the GPU core; The reading module 1002 is also used to read ray tracing data from the on-chip cache through the cache controller based on the data reading instruction, and send the ray tracing data to the GPU core; The computing module 1003 is used to perform ray tracing calculations through the GPU core based on ray tracing data.

[0191] Optionally, the on-chip cache is allocated to different cache spaces corresponding to different thread bundles, and the ray tracing data stored in the cache space is the data required to perform ray tracing calculations on multiple rays corresponding to the thread bundle; The reading module 1002 is used to: send the data reading instruction corresponding to the thread bundle to the cache controller through the GPU core; The reading module 1002 is configured to: read the ray tracing data corresponding to the thread bundle from the cache space corresponding to the thread bundle in the on-chip cache based on the data reading instruction corresponding to the thread bundle through the cache controller, and send the ray tracing data to the GPU core; The computing module 1003 is used to: perform ray tracing calculations on multiple rays corresponding to the thread bundle based on the ray tracing data through the GPU core.

[0192] Optionally, the device further includes a release module, configured to: after performing ray tracing calculations on multiple rays corresponding to the thread bundle via the GPU core, send a release instruction corresponding to the thread bundle to the cache controller, wherein the release instruction is used to instruct the release of the cache space corresponding to the thread bundle; The release module is used to: release the cache space corresponding to the thread bundle in the on-chip cache based on the release instruction through the cache controller.

[0193] Optionally, the release module is used to: through the cache controller, if there is no adjacent free cache space after the release, create a new free entry, the new free entry being used to record the cache space after the release; Optionally, the release module is used to: update the free entry corresponding to the free cache space when there is an adjacent free cache space after the release, through the cache controller, and the updated free entry is used to record the space after the release of the cache space and the free cache space are merged.

[0194] Optionally, the device further includes an allocation module for: sending an allocation instruction corresponding to the thread bundle to the cache controller through the GPU core, the allocation instruction being used to instruct the allocation of cache space for the thread bundle; The allocation module is configured to: allocate cache space for the thread bundle from the on-chip cache based on the allocation instruction via the cache controller.

[0195] Optionally, the allocation instruction includes a thread bundle identifier and a cache capacity; the allocation module is used for: The cache controller determines the cache space that meets the cache capacity from the free cache space of the on-chip cache based on the cache capacity in the allocation instruction. The cache controller allocates cache space to the thread bundle corresponding to the thread bundle identifier based on the thread bundle identifier in the allocation instruction. The cache controller updates the free cache space based on the cache space.

[0196] Optional, allocate module, for: The cache controller sends an allocation failure notification corresponding to the thread bundle to the GPU core when the capacity of the free cache space is insufficient to meet the cache capacity requirement. When the GPU core receives the allocation failure notification corresponding to the thread bundle and a preset time has elapsed, it resends the allocation instruction to the cache controller.

[0197] Optionally, the GPU core includes an allocation management unit; and an allocation module, used for: The allocation management unit determines the cache capacity corresponding to the thread bundle and sends an allocation instruction containing the thread bundle identifier and the cache capacity to the cache controller.

[0198] Optional, allocate module, for: After allocating the cache space for the thread bundle from the on-chip cache based on the allocation instruction, the cache controller sends a successful allocation notification for the thread bundle to the GPU core.

[0199] Optionally, the device further includes a data writing unit for: The GPU core sends a data write instruction corresponding to the thread bundle to the cache controller, and the data write instruction is used to indicate the writing of the ray tracing data; The cache controller writes the ray tracing data into the cache space corresponding to the thread bundle based on the data write instruction.

[0200] Optionally, the data writing instruction includes the ray tracing data to be written, the write address, and the write length; the data writing unit is used for: The cache controller is used to write the ray tracing data to be written in the data writing instruction into the on-chip cache, starting from the write address and having the write length in the cache space.

[0201] Optionally, the read module 1002 is used for: The cache controller reads the ray tracing data from the on-chip cache based on the data read instruction, and writes the ray tracing data into the register in the GPU core. The GPU core reads the ray tracing data from the register and performs ray tracing calculations.

[0202] Optionally, the data read instruction includes the read address in the on-chip cache, the read length, and the register address of the register; the read module 1002 is used for: The cache controller reads ray tracing data with the specified length from the read address in the on-chip cache based on the data read instruction, and writes the ray tracing data into the register corresponding to the register address in the GPU core.

[0203] Optionally, the on-chip cache is an L2 level on-chip cache on the GPU chip, and the on-chip cache adopts a circular buffer structure.

[0204] Optionally, in the storage hierarchy architecture of the GPU chip, the storage hierarchy of the on-chip cache is lower than that of the registers in the GPU core, and the storage capacity of the on-chip cache is higher than that of the registers.

[0205] In some embodiments, this application also provides a graphics card, which includes a GPU chip and video memory as described in any of the above embodiments.

[0206] In some embodiments, this application also provides a computer device equipped with a graphics card as described above.

[0207] See Figure 11 , Figure 11 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application.

[0208] Specifically, the computer device 1100 includes a system bus 1101, a graphics card 1102, and other devices 1105. The graphics card 1102 includes a GPU chip 1103 and video memory 1104. The GPU chip 1103 includes a GPU core, on-chip cache, and a cache controller.

[0209] Optionally, other devices 1105 include system memory consisting of random access memory and read-only memory, a basic input / output (I / O) system that facilitates information transfer between various devices within the computer, and a mass storage device for storing the operating system, applications, and other program modules. The basic input / output system includes a display for showing information and input devices such as a mouse and keyboard for user input. Both the display and the input devices are connected to the processing unit via an input / output controller connected to the system bus 1101. The basic input / output system may also include an input / output controller for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller also provides output to a display screen, printer, or other types of output devices.

[0210] The mass storage device is connected to the processing unit via a mass storage controller connected to the system bus 1101. The mass storage device and its associated computer-readable media provide non-volatile storage for the computer device 1100. That is, the mass storage device may include computer-readable media such as a hard disk or drive.

[0211] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The aforementioned system memory and mass storage devices can be collectively referred to as memory.

[0212] The memory stores one or more programs, which are configured to be executed by one or more processing units. The one or more programs contain instructions for implementing the methods described above, and the processing units execute the one or more programs to implement the methods provided in the various method embodiments described above.

[0213] According to various embodiments of this application, the computer device 1100 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 1100 can be connected to a network via a network interface unit connected to the system bus 1101, or it can use a network interface unit to connect to other types of networks or remote computer systems.

[0214] The memory further includes one or more programs stored in the memory, and the one or more programs include steps performed by a computer device in the methods provided in the embodiments of this application.

[0215] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A GPU chip, comprising: The GPU chip comprises a GPU core, an on-chip cache and a cache controller; The on-chip cache is configured to store ray tracing data required for ray tracing calculation; The GPU core is configured to send a data read instruction to the cache controller; The cache controller is configured to read the ray tracing data from the on-chip cache based on the data read instruction and send the ray tracing data to the GPU core; The GPU core is configured to perform ray tracing calculation based on the ray tracing data.

2. The GPU chip of claim 1, wherein, The on-chip cache is allocated to different cache spaces corresponding to different thread bundles, and the ray tracing data stored in the cache spaces is data required for performing ray tracing calculation on a plurality of rays corresponding to the thread bundles; The GPU core is configured to send the data read instruction corresponding to the thread bundle to the cache controller; The cache controller is configured to read the ray tracing data corresponding to the thread bundle from the cache space corresponding to the thread bundle in the on-chip cache based on the data read instruction corresponding to the thread bundle, and send the ray tracing data to the GPU core; The GPU core is configured to perform ray tracing calculation on a plurality of rays corresponding to the thread bundle based on the ray tracing data.

3. The GPU chip of claim 2, wherein The GPU core is configured to send a release instruction corresponding to the thread bundle to the cache controller after completing the ray tracing calculation on a plurality of rays corresponding to the thread bundle, and the release instruction is used to instruct to release the cache space corresponding to the thread bundle; The cache controller is configured to release the cache space corresponding to the thread bundle in the on-chip cache based on the release instruction.

4. The GPU chip of claim 3, wherein The cache controller is configured to create a new free entry to record the released cache space in a case that there is no adjacent free cache space in the released cache space; The cache controller is configured to update a free entry corresponding to the free cache space in a case that there is adjacent free cache space in the released cache space, and the updated free entry is used to record the space after the released cache space and the free cache space are combined.

5. The GPU chip of claim 2, wherein The GPU core is configured to send an allocation instruction corresponding to the thread bundle to the cache controller, and the allocation instruction is used to instruct to allocate the cache space for the thread bundle; The cache controller is configured to allocate the cache space for the thread bundle from the on-chip cache based on the allocation instruction.

6. The GPU chip of claim 5, wherein, The allocation instruction comprises a thread bundle identifier and a cache capacity; The cache controller is configured to determine the cache space satisfying the cache capacity from free cache spaces of the on-chip cache based on the cache capacity in the allocation instruction; The allocation instruction comprises a thread bundle identifier and a cache capacity; The cache controller is configured to determine the cache space satisfying the cache capacity from free cache spaces of the on-chip cache based on the cache capacity in the allocation instruction; The cache controller is configured to allocate the cache space for the thread bundle corresponding to the thread bundle identifier based on the thread bundle identifier in the allocation instruction. The cache controller is configured to update the free cache space based on the cache space.

7. The GPU chip of claim 6, wherein The cache controller is configured to send an allocation failure notification corresponding to the thread bundle to the GPU core in a case where the capacity of the free cache space does not satisfy the cache capacity. The GPU core is configured to resend the allocation instruction to the cache controller in a case where the allocation failure notification corresponding to the thread bundle is received and a preset time length is reached.

8. The GPU chip of claim 6, wherein, The GPU core comprises an allocation management unit. The allocation management unit is configured to determine the cache capacity corresponding to the thread bundle and send the allocation instruction comprising the thread bundle identifier and the cache capacity to the cache controller.

9. The GPU chip of claim 5, wherein The cache controller is configured to send an allocation success notification corresponding to the thread bundle to the GPU core after allocating the cache space for the thread bundle from the on-chip cache based on the allocation instruction.

10. The GPU chip of claim 5, wherein The GPU core is configured to send a data write instruction corresponding to a thread bundle to the cache controller, the data write instruction being used to instruct to write the ray tracing data. The cache controller is configured to write the ray tracing data into the cache space corresponding to the thread bundle based on the data write instruction.

11. The GPU chip of claim 10, wherein, The data write instruction comprises the ray tracing data to be written, a write address, and a write length. The cache controller is configured to write the ray tracing data to be written in the data write instruction into the cache space with the write length from the write address in the on-chip cache.

12. The GPU chip of claim 1, wherein The cache controller is configured to read the ray tracing data from the on-chip cache based on the data read instruction and write the ray tracing data into the register in the GPU core. The GPU core is configured to read the ray tracing data in the register and perform ray tracing calculation.

13. The GPU chip of claim 12, wherein, The data read instruction comprises a read address in the on-chip cache, a read length, and a register address of the register. The cache controller is configured to read the ray tracing data with the read length from the read address in the on-chip cache based on the data read instruction and write the ray tracing data into the register corresponding to the register address in the GPU core.

14. The GPU chip of any one of claims 1 to 13, wherein, The on-chip cache is an L2 level on-chip cache on the GPU chip, and the on-chip cache adopts a ring buffer structure.

15. The GPU chip of any one of claims 1 to 13, wherein In a memory hierarchy architecture of the GPU chip, the on-chip cache is lower in memory hierarchy than a register in the GPU core, and the on-chip cache is higher in memory capacity than the register.

16. A ray tracing method, characterized by, The method is applied to a GPU chip, which comprises a GPU core, an on-chip cache and a cache controller, and the method comprises: storing, by the on-chip cache, ray tracing data required for ray tracing calculation; sending, by the GPU core, a data reading instruction to the cache controller; based on the data reading instruction, reading, by the cache controller, the ray tracing data from the on-chip cache and sending the ray tracing data to the GPU core; based on the ray tracing data, performing, by the GPU core, ray tracing calculation.

17. A graphics card, comprising: The graphics card comprises the GPU chip as claimed in any one of claims 1 to 15 and a display memory.

18. A computer device, comprising: The computer device comprises the graphics card as claimed in claim 17.

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