Bms parallel addressing method, device, equipment, storage medium and product

Abstract

The application discloses a BMS parallel machine addressing method, device, equipment, storage medium and product, relates to the technical field of battery management system, and the method comprises the following steps: sending an initialization instruction to a BMS module, so that the BMS module enters a waiting addressing state; determining a host unit from the BMS module, and allocating a host address to the host unit; sending an addressing instruction to the host unit, so that the host unit generates a coding signal containing the host address; sequentially transmitting the coding signal among the remaining BMS modules, and taking the BMS module receiving the coding signal as a slave unit; and based on an address allocation rule and the coding signal, sequentially allocating corresponding slave addresses to each slave unit. Compared with the existing manual code dialing mode, the application realizes dynamic address allocation by automatically generating and sequentially transmitting the coding signal, thereby realizing full automation of the addressing process, effectively avoiding address conflicts, and significantly improving system deployment efficiency and scalability.

Description

Technical Field

[0001] This application relates to the field of battery management system technology, and in particular to a BMS parallel addressing method, apparatus, device, storage medium and product. Background Technology

[0002] In energy storage systems, to meet the ever-increasing demand for power supply capacity, multiple battery packs are often connected in parallel, each equipped with a battery management system (BMS). In this multi-BMS parallel operation scenario, a unique address must be assigned to each BMS to achieve ordered master-slave communication and centralized management.

[0003] Currently, the traditional method relies on manual DIP switches for hardware address settings. Before paralleling, operators must manually switch each physical DIP switch on each BMS module in a preset sequence to set its address. When expanding the system, the addresses of all related modules must be manually readjusted to avoid conflicts. This traditional method is cumbersome and time-consuming; the workload of manual configuration increases exponentially with the system size. Secondly, it is highly susceptible to human error leading to duplicate or incorrect addresses, causing communication conflicts and system instability. Furthermore, subsequent maintenance and troubleshooting heavily rely on manual address verification, resulting in low efficiency and high costs.

[0004] Therefore, how to achieve automatic and accurate allocation of BMS parallel addresses is an urgent problem to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a BMS parallel addressing method, apparatus, device, storage medium, and product, aiming to solve the technical problem of how to achieve automatic and accurate allocation of BMS parallel addresses.

[0006] To achieve the above objectives, this application proposes a BMS parallel addressing method. The method is applied to a BMS addresser, which is connected to both the BMS module and the device to be powered. The method includes:

[0007] Send an initialization command to the BMS module to put the BMS module into an addressable state;

[0008] The host unit is determined from the BMS module, and a host address is assigned to the host unit;

[0009] Send an addressing instruction to the host unit so that the host unit generates an encoded signal containing the host address;

[0010] The encoded signal is transmitted sequentially among the remaining BMS modules, and the BMS module that receives the encoded signal is used as a slave unit.

[0011] Based on the address allocation rules and the encoded signal, each slave unit is sequentially assigned a corresponding slave address.

[0012] In one embodiment, the step of determining the host unit from the BMS module and assigning a host address to the host unit includes:

[0013] Obtain the status information of the BMS module that is in the pending addressing state;

[0014] The status information is analyzed according to a preset priority order to determine the host unit from the BMS module;

[0015] Send an address allocation instruction to the host unit to allocate a host address to the host unit.

[0016] In one embodiment, the step of analyzing the state information according to a preset priority order includes:

[0017] Obtain the current device information of the device to be powered;

[0018] Based on the current device information, the BMS units within the BMS module are sorted by priority weight according to a preset priority order.

[0019] The host unit is determined from the BMS units according to the priority weight sorting.

[0020] In one embodiment, after the step of determining the host unit from the BMS module, the method further includes:

[0021] Monitor the connection status between the host unit and the device to be powered;

[0022] If a change in the connection status is detected, then based on the preset priority order and the updated connection status, it is determined whether the host unit needs to be re-determined.

[0023] If so, then based on the updated connection status, the step of determining the host unit from the BMS module is re-executed.

[0024] In one embodiment, the step of sequentially assigning corresponding slave addresses to each of the slave units based on the address allocation rules and the encoded signal includes:

[0025] The received encoded signal is decoded to obtain the preceding address information;

[0026] Based on the preceding address information and the address allocation rules, the candidate address of the slave unit is determined;

[0027] Determine whether the candidate slave address conflicts with an address already assigned to another slave unit;

[0028] If it is determined that there is no conflict, the candidate slave address is determined as the slave address of the current slave unit.

[0029] In one embodiment, after the step of sequentially assigning corresponding slave addresses to each of the slave units, the method further includes:

[0030] Conflict monitoring is performed on each of the slave device addresses.

[0031] If an address conflict is detected in the slave address, the state of the slave unit with the address conflict is reset to the addressing pending state;

[0032] The host unit is resent the addressing start command to generate a new slave address for the slave unit that is in the addressing pending state.

[0033] Furthermore, to achieve the above objectives, this application also proposes a BMS parallel addressing device, the device comprising:

[0034] An initialization module is used to send initialization commands to the BMS module so that the BMS module enters the addressing state.

[0035] The host address allocation module is used to determine the host unit from the BMS module and allocate a host address to the host unit;

[0036] The instruction sending module is used to send an addressing instruction to the host unit so that the host unit generates an encoded signal containing the host address;

[0037] The slave unit allocation module is used to transmit the encoded signal sequentially among the remaining BMS modules, and to designate the BMS module that receives the encoded signal as a slave unit.

[0038] The slave address allocation module is used to sequentially allocate corresponding slave addresses to each of the slave units based on the address allocation rules and the encoded signal.

[0039] In addition, to achieve the above objectives, this application also proposes a BMS parallel addressing device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the BMS parallel addressing method as described above.

[0040] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the BMS parallel addressing method described above.

[0041] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the BMS parallel addressing method described above.

[0042] This application provides a BMS parallel addressing method, apparatus, device, storage medium, and product. The method is applied to a BMS addresser, which is connected to a BMS module and a device to be powered. The method includes: sending an initialization command to the BMS module to put the BMS module into an addressing state; determining a master unit from the BMS module and assigning a master address to the master unit; sending an addressing command to the master unit to generate an encoded signal containing the master address; transmitting the encoded signal sequentially among the remaining BMS modules, and designating the BMS module that receives the encoded signal as a slave unit; and assigning a corresponding slave address to each slave unit sequentially based on address allocation rules and the encoded signal.

[0043] This application first sends an initialization command to the BMS module, putting it into an addressing-ready state. Then, it identifies the master unit from the BMS module and assigns a master address to it. Next, it sends an addressing command to the master unit, causing it to generate an encoded signal containing the master address. This encoded signal is then sequentially transmitted among the remaining BMS modules, with the BMS module receiving the encoded signal becoming a slave unit. Finally, based on the address allocation rules and the encoded signal, each slave unit is sequentially assigned a corresponding slave address. Compared to existing manual dialing methods, this application achieves dynamic address allocation by automatically generating and sequentially transmitting encoded signals, thus fully automating the addressing process, effectively avoiding address conflicts, and significantly improving system deployment efficiency and scalability. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating an embodiment of the BMS parallel addressing method of this application.

[0047] Figure 2 This is a flowchart illustrating Embodiment 2 of the BMS parallel addressing method of this application;

[0048] Figure 3 This is a flowchart illustrating Embodiment 3 of the BMS parallel addressing method of this application;

[0049] Figure 4 This is a schematic diagram of the module structure of the BMS parallel addressing device according to an embodiment of this application;

[0050] Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the BMS parallel addressing method in the embodiments of this application.

[0051] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0052] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0053] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0054] The main solution of this application embodiment is as follows: In the field of battery management system technology, in energy storage systems, to meet the ever-increasing demand for power supply capacity, it is often necessary to operate multiple battery packs in parallel, and each battery pack is equipped with a battery management system (BMS). In this multi-BMS parallel operation scenario, a unique address must be assigned to each BMS to achieve master-slave ordered communication and centralized management.

[0055] Currently, the traditional method relies on manual DIP switches for hardware address settings. Before paralleling, operators must manually switch each physical DIP switch on each BMS module in a preset sequence to set its address. When expanding the system, the addresses of all related modules must be manually readjusted to avoid conflicts. This traditional method is cumbersome and time-consuming; the workload of manual configuration increases exponentially with the system size. Secondly, it is highly susceptible to human error leading to duplicate or incorrect addresses, causing communication conflicts and system instability. Furthermore, subsequent maintenance and troubleshooting heavily rely on manual address verification, resulting in low efficiency and high costs.

[0056] This application first sends an initialization command to the BMS module to put it into an addressing-ready state. Then, it identifies the master unit from the BMS module and assigns a master address to it. Next, it sends an addressing command to the master unit, causing it to generate an encoded signal containing the master address. This encoded signal is then passed sequentially among the remaining BMS modules, with the BMS module receiving the encoded signal becoming a slave unit. Finally, based on the address allocation rules and the encoded signal, each slave unit is assigned a corresponding slave address in sequence. Compared to existing manual dialing methods, this application achieves dynamic address allocation by automatically generating and sequentially transmitting encoded signals, thus fully automating the addressing process, effectively avoiding address conflicts, and significantly improving system deployment efficiency and scalability.

[0057] It should be noted that the executing entity in the following embodiments can be a BMS parallel addressing device, or a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a BMS parallel addressing device capable of performing the above functions. This embodiment does not specifically limit it in this way. The following uses a BMS parallel addressing device (hereinafter referred to as the device) as the executing entity to describe this embodiment and the following embodiments.

[0058] Based on this, this application proposes a dialogue method according to a first embodiment, please refer to... Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the BMS parallel addressing method of this application, which includes steps S10 to S50:

[0059] Step S10: Send an initialization command to the BMS module so that the BMS module enters the addressing state.

[0060] It should be noted that the BMS addresser can be any hardware module or software logic unit with logic control and communication management functions, such as a dedicated control board built on an ARM Cortex-M series microcontroller. This addresser acts as the system's control center, coordinating the entire addressing process. The BMS module can be any hardware module with battery status monitoring, protection, and communication functions, such as a BMS circuit board integrating voltage acquisition, temperature detection, and a CAN bus interface. Each BMS module can contain one or more BMS units, responsible for managing a battery pack or battery array. The device to be powered can be a load or device that requires power from the battery system managed by the BMS module, such as an inverter in an energy storage system, an electric drive system in an electric vehicle, or a backup power supply for a communication base station.

[0061] Understandably, an initialization command can be a specific control command generated and issued by the BMS addresser. The essential function of the initialization command is to trigger the receiver (i.e., the BMS module) to execute a series of predefined reset and preparation operations. For example, this command could be a Modbus RTU protocol data frame containing a specific function code (such as 0x01) and clear parameters, broadcast via the RS-485 bus.

[0062] The address-pending state is a specific internal logical state that a BMS module enters after successfully receiving and executing initialization instructions. In this state, the address identifiers used for network communication are considered undefined or invalid (e.g., the address register is cleared to 0), and the module is ready to respond to subsequent addressing procedures. For example, the microcontroller program inside the module might set a status flag to ADDR_PENDING and begin listening for specific addressing commands on the bus.

[0063] In its implementation, the BMS addresser first broadcasts or sends a specific initialization command to all connected BMS modules in the network via its connected communication bus (e.g., RS-485 bus or CAN bus). This command instructs each BMS module to reset its internal logic state and prepare to accept subsequent address allocation operations. Upon receiving the command, each BMS module clears its current address configuration (whether old or invalid) or marks it as pending overwrite, entering a pending addressing state. In this state, the BMS module's address has not yet been finalized, and it is ready to respond to subsequent master-slave determination and address allocation commands.

[0064] Step S20: Determine the host unit from the BMS module and assign a host address to the host unit.

[0065] It should be noted that the host unit can be a specific unit elected from all BMS modules in the addressing-pending state. The host unit can be any BMS module with master control functionality; it may be hardware-independently identical to other modules, but its logical role is designated as master. The host address is a unique logical identifier assigned to the host unit for identification within the network. In a common implementation, the host address can be a predefined fixed value, such as the decimal number 1, to distinguish it from subsequently assigned slave addresses.

[0066] In its implementation, the BMS addresser first requests or collects status information from all BMS modules in the addressing-pending state. This status information contains key parameters that determine which module is more suitable to act as the host, such as whether the BMS module is physically connected to an inverter or a specific type of communication port. The BMS addresser internally stores a preset priority order, for example, modules connected to inverters have the highest priority, followed by modules connected to debugging ports. Based on this order, the BMS addresser analyzes and compares the status information reported by all BMS modules, selecting the module with the highest priority and designating it as the host unit for this addressing process. Once the host unit is determined, the BMS addresser sends an address allocation instruction to this selected host unit. Upon receiving this instruction, the host unit sets its internal communication address to the pre-agreed host address, for example, by writing the value 1 to its address register, thus formally establishing its host identity and network identifier.

[0067] Step S30: Send an addressing instruction to the host unit so that the host unit generates an encoded signal containing the host address.

[0068] It should be noted that an addressing instruction can be a specific control command sent by the BMS addresser to the host unit. The essential function of this addressing instruction is to trigger the module already designated as the host unit to begin executing address encoding and signal generation operations. For example, an addressing instruction can be a serial communication message containing a start automatic addressing command code, sent to the host unit via the CAN bus.

[0069] Understandably, the encoded signal can be a specific physical signal carrying address information generated by the BMS module, which is identified as the host unit. The encoded signal can be any form of signal that modulates digital information onto electrical characteristics. For example, the encoded signal can be a pulse-width modulation (PWM) waveform, where information is encoded by the duration of high-level pulses; in another implementation, it can be an amplitude- or frequency-modulated serial digital signal.

[0070] In the specific implementation, after the host unit is determined and its host address is set, the BMS addresser sends an addressing instruction to the specific host unit via the communication link. Upon receiving this addressing instruction, the host unit's internal control program is activated. The program first reads the set host address value from the storage unit. Then, the program calls the signal encoder to convert the host address value into a corresponding encoded signal according to the signal generation algorithm pre-installed in the firmware. For example, the encoding algorithm can map each binary bit of the address value to a series of electrical pulses of a specific width. Finally, the host unit, through its signal output drive circuit, applies this encoded signal waveform representing the host address to the communication lines connected to other BMS units.

[0071] Step S40: The encoded signal is transmitted sequentially among the remaining BMS modules, and the BMS module that receives the encoded signal is designated as a slave unit.

[0072] It should be noted that the remaining BMS modules can be all BMS modules in the addressing-pending state that have not yet been identified as master units. Sequential transmission can be a serial transmission process where encoded signals are transmitted from one module to the next adjacent module along a pre-defined physical communication link that connects the BMS modules in series. For example, this sequential transmission can be achieved by connecting the communication output ports (e.g., DN_OP) of each module to the communication input ports (e.g., UP_IN) of the next module in a daisy-chain manner. The slave unit can be any remaining BMS module that successfully receives the encoded signal during the sequential transmission process.

[0073] In the specific implementation, after the host unit outputs the encoded signal waveform on the communication link, the signal first reaches the first BMS module physically connected directly to the host unit. The input detection circuit of this BMS module continuously monitors the line status. Once a level change matching the characteristics of the encoded signal is detected, the module's firmware determines that it has received a valid addressing signal. Subsequently, the module changes its internal logic state from "pending addressing" to "slave unit." This means that the module has clarified its subordinate role and is ready to decode the received encoded signal to obtain address information. During this process, the encoded signal itself continues to be transmitted along the physical link to the next BMS module, thus creating conditions for the identification of subsequent potential slave units. This step automatically completes the identification and role assignment of the first slave unit through the inherent sequence of the physical link and active signal monitoring.

[0074] Step S50: Based on the address allocation rules and the encoded signal, assign corresponding slave addresses to each slave unit in sequence.

[0075] It should be noted that the address allocation rule can be a predefined set of logic or algorithms that guides the calculation and determination of the unique address of a slave unit based on coded signal information. The address allocation rule can be any deterministic address generation logic; for example, a common rule is the sequential increment rule, where the address of each subsequent slave unit is one greater than the address of the previous device. The slave address can be a unique logical identifier assigned to each slave unit according to the address allocation rule, used to distinguish it from the master unit and other slave units in the network. For example, the slave address of the first slave unit might be 2, the second might be 3, and so on.

[0076] In the specific implementation, the first BMS module identified as a slave unit first decodes the received encoded signal. The decoding process is the reverse of the generation process. For example, by measuring the duration of the high-level pulse, the waveform is restored to a binary bit stream, thus obtaining the host address value carried in the encoded signal. Next, the slave unit calls its internally stored address allocation rules. Assuming the rule is a sequential incrementing rule, the slave unit takes the decoded host address value (e.g., 1) as input, performs an increment operation, and calculates its own candidate address (e.g., 2). Then, this calculated address value is written to the slave unit's internal address register, thus being officially assigned as the slave address. After completing its own address allocation, the slave unit can generate a new encoded signal based on its new slave address and pass it to the next module on the link. The next module repeats the above decoding, rule calculation, and address allocation process, and so on, until all slave units have obtained a unique slave address.

[0077] This embodiment first sends an initialization command to the BMS module to put it into an addressing-ready state. Then, it identifies the master unit from the BMS module and assigns a master address to it. Next, it sends an addressing command to the master unit, causing it to generate an encoded signal containing the master address. The encoded signal is then passed sequentially among the remaining BMS modules, with the BMS module receiving the encoded signal designated as a slave unit. Finally, based on the address allocation rules and the encoded signal, each slave unit is assigned a corresponding slave address in sequence. Compared to existing manual dialing methods, this embodiment achieves dynamic address allocation by automatically generating and sequentially transmitting encoded signals, thus fully automating the addressing process, effectively avoiding address conflicts, and significantly improving system deployment efficiency and scalability.

[0078] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description and will not be repeated hereafter. On this basis, a second embodiment of the BMS parallel addressing method of this application is proposed. Please refer to... Figure 2 , Figure 2 This is a flowchart illustrating Embodiment 2 of the BMS parallel addressing method of this application. To obtain status information, such as... Figure 2 As shown, in this embodiment, the step of determining the host unit from the BMS module and assigning a host address to the host unit includes:

[0079] Step S201: Obtain the status information of the BMS module in the addressing pending state.

[0080] It should be noted that status information can be a set of data reported by a BMS module in the addressing-pending state, reflecting its current status. Status information can be any set of data that can characterize a specific attribute or connection status of the module, such as a set of data frames containing external device connection status flags. Specifically, status information may include a Boolean value (True / False) indicating whether the inverter is connected, and a Boolean value indicating whether a RS-232 communication port is connected.

[0081] In the implementation, after a BMS module enters the addressing state, the BMS addresser sends a status query command to all BMS modules in this state via the communication bus. Upon receiving the query command, each BMS module's internal firmware collects the module's current hardware connection status. For example, the firmware reads the voltage levels of the detection pins connected to the inverter and the detection pins connected to the RS-232 communication interface, converting these physical states into logical values. Then, the BMS module assembles these logical values ​​into a status information data packet according to a predefined communication protocol format and replies to the BMS addresser via the communication bus. The BMS addresser sequentially receives and stores the status information replies from each BMS module.

[0082] Step S202: Analyze the status information according to a preset priority order to determine the host unit from the BMS module.

[0083] It should be noted that the preset priority order can be a set of predefined rules stored in the BMS addresser, used to compare and sort different attributes contained in the status information to determine which BMS module is more suitable to act as the host. The preset priority order can be any defined and comparable set of rules. For example, a set of rules could be: Rule 1: Modules connected to the inverter have priority over all other modules; Rule 2: If no module is connected to the inverter, then the module connected to the RS-232 communication port has priority.

[0084] In its implementation, the BMS addresser, after receiving the status information reported by all BMS modules, begins executing its analysis logic. This analysis logic follows a preset priority order. The BMS addresser first iterates through all status information, checking the attribute of whether an inverter is connected. If only one BMS module has this attribute true, that module is immediately designated as the master unit. If multiple BMS modules have this attribute true, one can be selected based on additional rules (such as random selection or based on module ID). If no module is connected to the inverter, the BMS addresser proceeds according to the next rule in the preset priority order, such as checking for a connection to a RS-232 communication port, and so on, until a BMS module that meets the criteria is selected based on the rules.

[0085] Step S203: Send an address allocation instruction to the host unit to allocate a host address to the host unit.

[0086] It should be noted that an address allocation command can be a command containing specific address data sent by the BMS addresser to a designated host unit. This address allocation command can be any communication message used to configure the address of the target device, such as a Modbus write command frame containing a function code for setting the address and address parameter 1.

[0087] In its implementation, once the BMS addresser identifies the host unit based on the analysis results, it generates an address allocation instruction. This instruction explicitly contains the host address value to be allocated to the host unit, such as the value 1. The BMS addresser sends this instruction to the identified host unit via the communication bus. Upon receiving this instruction, the host unit's communication interface parses it using its internal firmware, recognizing it as an address setting command and extracting the address value. The firmware then writes this address value, for example, 1, into a dedicated address storage area or address register in the module's internal non-volatile memory. After this writing is complete, the host unit logically and officially acquires host address 1. Its identity as a network host is thus permanently or semi-permanently established through software configuration, replacing the traditional physical setting method using manual DIP switches.

[0088] Furthermore, in order to determine the host unit, in this embodiment, the step of analyzing the status information according to a preset priority order includes:

[0089] Step S2021: Obtain the current device information of the device to be powered.

[0090] It should be noted that the device to be powered can be a load device that requires power from a battery system managed by the BMS module. The device to be powered can be any type of electrical load or device that needs to interact with the BMS system, such as an inverter in an energy storage system (e.g., a GoodWe GW5000-NS inverter), or a RS-232 communication interface device used for commissioning and monitoring. Current device information can be data regarding the current connection relationship and device type between the device to be powered and the BMS module. Current device information can include connection status identifiers such as "connected inverter" or "connected RS-232 communication," as well as specific device type identifiers.

[0091] In practical implementation, to execute more precise host unit determination logic, the BMS addresser needs to know what external devices each BMS module is specifically connected to. The BMS addresser can obtain this current device information in two main ways. The first way is active querying: the BMS addresser sends a specific query command to each BMS module, requesting the module to report the connection status of its external ports (such as inverter interfaces, RS-232 communication interfaces). The BMS module determines whether a device is connected by detecting the physical level or communication handshake signal of the corresponding port and replies with this status as part of the current device information to the BMS addresser. The second way is that the BMS module directly includes this current device information in its initial reported status information. By collecting this information, the BMS addresser can know whether each BMS module is connected to an inverter, a RS-232 communication device, or not connected to a specific external device, thus providing accurate input data for the next step of prioritizing based on device type.

[0092] Step S2022: Based on the current device information, sort the BMS units in the BMS module according to the preset priority order.

[0093] It should be noted that priority weight sorting can be a process of calculating and assigning a quantified value (weight) representing the priority of each BMS unit according to a preset priority order, and then arranging all BMS units in descending or ascending order based on this value. Priority weight sorting can be implemented using any comparable numerical mapping algorithm. For example, a simple implementation is to assign a weight value of 3 to connected inverters, a weight value of 2 to connected RS-232 communication, and a weight value of 1 to no connection. Then, the corresponding weight value is calculated based on the aforementioned current device information of each BMS unit and compared.

[0094] In its implementation, the BMS addresser, after obtaining the current device information of each BMS unit, begins executing a sorting algorithm. The algorithm iterates through the current device information of each BMS unit. For each unit, the algorithm converts its device connection type into a specific priority weight value according to the mapping rules defined in the preset priority order. For example, if the preset rule defines the weight for connecting to an inverter as the highest level (e.g., value 100) and connecting to RS-232 communication as the second highest level (e.g., value 50), then when the current device information of a BMS unit shows that it is connected to an inverter, that unit is assigned a weight value of 100. After assigning weights to all units, the BMS addresser sorts all BMS units from highest to lowest according to their assigned weight values, generating an ordered list. This list visually reflects the order of suitability of all candidate units to become host units, with the unit with the highest weight value at the beginning of the list.

[0095] Step S2023: Determine the host unit from the BMS units according to the priority weight sorting.

[0096] In its implementation, after prioritizing and sorting the BMS units, the BMS addresser obtains an ordered list, with the highest-weighted BMS unit at the top. The BMS addresser's decision logic directly extracts the first-ranked BMS unit from this sorted list. For example, if the sorted list shows unit A (weight 100, connected to an inverter) at the top and unit B (weight 50, connected to RS-232 communication) at the bottom, the BMS addresser will select unit A as the master unit. If multiple BMS units have the same highest weight (e.g., two units connected to inverters, both with a weight of 100), the BMS addresser can specify one of these parallel units as the final master unit based on preset supplementary rules (such as selecting the module with the smaller physical address, or random selection).

[0097] Furthermore, in order to monitor the connection status between the host unit and the device to be powered, in this embodiment, after the step of determining the host unit from the BMS module, the method further includes:

[0098] Step S21: Monitor the connection status between the host unit and the device to be powered.

[0099] It should be noted that monitoring can be a periodic or continuous check and read operation performed by the BMS addresser to determine the status of a specific target. Monitoring can be achieved through any interactive method capable of obtaining target status information, such as periodically sending query commands and waiting for responses. Connection status can refer to the connectivity of the physical or logical link between the host unit and the device to be powered. Connection status can be a binary logical value, such as connection active or connection disconnected.

[0100] In its implementation, after the host unit is identified and put into operation, the BMS addresser initiates a monitoring task. This task periodically (e.g., every second) sends a connection status query command to the current host unit. Upon receiving the command, the host unit immediately checks its hardware connection status with external ports such as the inverter interface or the RS-232 communication interface. This check can be performed by reading the level of a dedicated connection detection pin or by attempting a brief communication handshake with the external device. The host unit then encapsulates the check result (i.e., the current connection status, such as a normal inverter connection or no response from the RS-232 communication port) in a reply message and sends it back to the BMS addresser. By continuously receiving and parsing these replies, the BMS addresser monitors in real time whether the connection between the host unit and key external devices remains normal.

[0101] Step S22: If a change in the connection status is detected, determine whether it is necessary to re-determine the host unit based on the preset priority order and the updated connection status.

[0102] It should be noted that changes in connection status can be detected through monitoring steps, indicating a change in the connection status between the host unit and the device to be powered compared to the previous monitoring result. For example, the change could be from an active connection to a disconnected connection, or from an unconnected connection to a connected connection. The updated connection status can be the monitored connection status information reflecting the latest actual situation, serving as input data for a new round of judgment.

[0103] In its implementation, when the BMS addresser detects a change in the connection status reported by a master unit (e.g., the master unit reports that its connection to the inverter has been lost), the BMS addresser records this new situation as the updated connection status. Subsequently, the BMS addresser invokes the internally stored preset priority order rules and, in conjunction with this updated connection status, performs a logical evaluation to determine whether the current master unit should still be the master. For example, the preset rule states that the module connected to the inverter has the highest master priority. During the determination, the system checks whether the current master unit is still connected to the inverter in the updated connection status. If it is no longer connected, and another slave unit in the network is now connected to the inverter, then according to the rules, the current master unit may no longer have the highest priority; therefore, the conclusion is that the master unit needs to be re-determined.

[0104] Step S23: If yes, then based on the updated connection status, re-execute the step of determining the host unit from the BMS module.

[0105] In its implementation, once the BMS addresser concludes that the host unit needs to be re-determined based on its judgment logic, it immediately triggers a complete re-determination process. First, the BMS addresser collects status information from all relevant BMS modules based on the latest connection status (i.e., the updated connection state) and any other necessary status information. Then, the BMS addresser analyzes and sorts the collected information reflecting the latest network status using the same preset priority order rules. Based on the new sorting results, the BMS addresser determines a new host unit from all candidate modules that best matches the current network situation. For example, if the original host unit loses its highest priority due to disconnection from the inverter, and another original slave unit is now connected to the inverter, the re-determination process will select this new slave unit as the new host unit.

[0106] Based on the first and / or second embodiments of this application, in the third embodiment of this application, the content that is the same as or similar to that in embodiments one and two above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 3 , Figure 3 This is a flowchart illustrating Embodiment 3 of the BMS parallel addressing method of this application. To determine the slave address corresponding to each slave unit, such as... Figure 3 As shown, in this embodiment, the step of sequentially assigning corresponding slave addresses to each slave unit based on the address allocation rules and the encoded signal includes:

[0107] Step S501: Decode the received encoded signal to obtain the preceding address information.

[0108] It should be noted that decoding can be a signal processing procedure in which the slave unit reverse-engineers the received encoded signal to recover the original address data. Decoding can be performed by any circuit or logic module capable of recognizing specific waveform characteristics and converting them into digital information. For example, a timer module equipped with input capture functionality within the slave unit (such as the TIMx timer in the STM32 series microcontrollers) can perform decoding by measuring the precise duration of high-level pulses.

[0109] Precedence address information can be the address value representing the network device that sent the signal (i.e., the preceding device) that is restored from the encoded signal through the decoding process. The preceding address information can be a specific number; for example, if the preceding device is the host, the preceding address information is host address 1; if the preceding device is the first slave, the preceding address information might be slave address 2.

[0110] In the implementation, when the slave unit detects a waveform matching the characteristics of the encoded signal at its communication input, it initiates the decoding process. The signal processing unit inside the slave unit (such as a timer module) precisely measures the duration of each high-level pulse in the encoded signal. For example, if the signal processing unit records a high-level pulse lasting 10 milliseconds, it interprets the pulse as a bit 1 according to a predefined decoding rule corresponding to the encoding rule (e.g., 10 milliseconds represents binary 1); if a pulse lasting 5 milliseconds is measured, it is interpreted as a bit 0. After sequentially interpreting all pulses into a binary bit stream, the signal processing unit combines and verifies them according to the same frame format as during encoding, ultimately reconstructing a complete address value. This reconstructed address value is the address of the preceding device (the predecessor device) that generated this encoded signal, and is therefore called the predecessor address information.

[0111] Step S502: Determine the candidate address of the slave unit based on the preceding address information and the address allocation rules.

[0112] It should be noted that the address allocation rule can be a predefined set of deterministic logic used to derive the next new address from a known address. The address allocation rule can be any mathematical or logical operation rule; for example, the sequential increment rule is an operation rule that adds 1 to the input address value. The candidate address can be an address value to be allocated to the current slave unit, calculated based on the preceding address information and the above address allocation rule. The candidate address can be an intermediate result that has not been finally verified; for example, if the preceding address information is 1 and the rule is sequential increment, then the candidate address is 2.

[0113] In the specific implementation, after the slave unit successfully decodes and obtains the preceding address information (e.g., the value 1), its internal processor will call the stored address allocation rule. Assuming the rule is an ascending order rule, the processor will perform an addition operation: adding the value (1) of the preceding address information to the increment constant (1). The result is the value 2, and the processor will temporarily store this value 2 as a candidate address.

[0114] Step S503: Determine whether the candidate slave address conflicts with an address already assigned to other slave units.

[0115] It should be noted that a conflict can occur when the value of a candidate slave address is exactly the same as the address value that has already been assigned to another slave unit in the current addressing process.

[0116] In the actual implementation, after a slave unit calculates its candidate slave address (e.g., the value 3), it does not immediately adopt this address. The slave unit or the BMS addresser coordinating this process needs to maintain a dynamic list that records all slave addresses that have been officially allocated during the current round of allocation. For example, if the first slave unit has been allocated address 2 and the second slave unit has been allocated address 3, the list would be [2, 3]. The current slave unit (let's say the third one) compares its candidate address (let's say 4) with each record in this list. The logic for the check is: whether the candidate address 4 is equal to any existing value (2 or 3) in the list. If it is equal, it is considered a conflict; if it is not equal to any existing value, it is considered a non-conflict.

[0117] Step S504: If it is determined that there is no conflict, then the candidate slave address is determined as the slave address of the current slave unit.

[0118] In practical implementation, once the system (such as the slave unit itself or the BMS addresser) completes conflict determination and concludes that there is no conflict, it performs an address confirmation operation. The value of the candidate slave address is written to a fixed area within the current slave unit's internal non-volatile memory (such as EEPROM or Flash memory) specifically designated for storing communication addresses. For example, the candidate address value 4 is written to a specific address offset in the memory. After the write operation is complete, the value changes from a candidate state to the current slave unit's official, permanent slave address. Subsequently, the current slave unit will use this address as its source address or destination identifier when conducting network communication.

[0119] Furthermore, in order to quickly resolve address conflicts in slave units, this embodiment, after the step of sequentially assigning corresponding slave addresses to each of the slave units, further includes:

[0120] Step S51: Perform conflict monitoring on each of the slave addresses.

[0121] In its implementation, after completing address allocation for all slave units and entering the normal communication phase, the BMS addresser initiates a background monitoring task. This task periodically (e.g., every 5 seconds) sends address query requests to all slave units in the network. Upon receiving a request, each slave unit sends back its stored slave address as a response message. The BMS addresser collects all responses, obtaining a current list containing the addresses of all online slave units. Subsequently, the BMS addresser performs a deduplication algorithm on this list, for example, sorting the list and checking if adjacent elements are identical. If two or more response messages contain the same address value, an address conflict is determined to have occurred.

[0122] Step S52: If an address conflict is detected in the slave address, the state of the slave unit with the address conflict is reset to the address-pending state.

[0123] In its implementation, when the BMS addresser determines an address conflict through conflict detection (e.g., finding that two slave units report address 3), the BMS addresser first precisely identifies the specific slave units involved in the conflict (e.g., unit X and unit Y). Then, the BMS addresser sends a forced state reset instruction to each of these identified slave units with address conflicts. This instruction commands the target slave unit to perform the following operations: first, erase or invalidate the current slave address (e.g., address 3) stored in its internal memory; second, switch the operating state of its internal state machine from slave mode back to addressable state. After this operation, the logical identity of these slave units in the network is cleared, and they become blank nodes again.

[0124] Step S53: Resend the addressing start command to the host unit to regenerate the slave address for the slave unit in the addressing state.

[0125] In the specific implementation, after the BMS addresser successfully resets the conflicting slave unit to the addressable state, in order to reallocate the correct and unique address to these blank units, the BMS addresser sends an addressing start command to the current master unit. Upon receiving this command, the master unit generates an encoded signal containing its host address, just as it did during initial addressing, and injects this signal into the communication link. At this point, the slave units in the network are divided into two categories: one category consists of units with normal addresses that are unaffected; these ignore or forward this signal but do not change their own addresses. The other category consists of units in the addressable state. These units in the addressable state will listen to, receive, and decode the encoded signal, just as they would when first joining the network. Then, they calculate a new candidate address according to the address allocation rules, and after passing conflict verification, establish the new address as their slave address.

[0126] This application also provides a BMS parallel addressing device, please refer to... Figure 4 The device includes:

[0127] Initialization module 10 is used to send an initialization command to the BMS module so that the BMS module enters the addressing state;

[0128] The host address allocation module 20 is used to determine the host unit from the BMS module and allocate a host address to the host unit;

[0129] The instruction sending module 30 is used to send an addressing instruction to the host unit so that the host unit generates an encoded signal containing the host address;

[0130] Slave unit allocation module 40 is used to transmit the encoded signal sequentially among the remaining BMS modules, and to designate the BMS module that receives the encoded signal as a slave unit;

[0131] The slave address allocation module 50 is used to sequentially allocate corresponding slave addresses to each of the slave units based on the address allocation rules and the encoded signal.

[0132] The BMS parallel addressing apparatus provided in this application, employing the BMS parallel addressing method in the above embodiments, can solve the technical problem of how to achieve automatic and accurate allocation of BMS parallel addresses. Compared with the prior art, the beneficial effects of the BMS parallel addressing apparatus provided in this application are the same as those of the BMS parallel addressing method provided in the above embodiments, and other technical features in the BMS parallel addressing apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0133] This application provides a BMS parallel addressing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the BMS parallel addressing method in the above embodiment 1.

[0134] The following is for reference. Figure 5 This document illustrates a structural schematic diagram of a BMS parallel addressing device suitable for implementing embodiments of this application. The BMS parallel addressing device in these embodiments may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 5 The BMS parallel addressing device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0135] like Figure 5As shown, the BMS parallel addressing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the BMS parallel addressing device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the BMS parallel addressing device to communicate wirelessly or wiredly with other devices to exchange data. Although BMS parallel addressing devices with various systems are shown in the figures, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0136] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0137] The BMS parallel addressing device provided in this application, employing the BMS parallel addressing method in the above embodiments, can solve the technical problem of how to achieve automatic and accurate allocation of BMS parallel addresses. Compared with the prior art, the beneficial effects of the BMS parallel addressing device provided in this application are the same as those of the BMS parallel addressing method provided in the above embodiments, and other technical features in this BMS parallel addressing device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0138] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0139] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0140] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the BMS parallel addressing method in the above embodiments.

[0141] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0142] The aforementioned computer-readable storage medium may be included in the BMS parallel addressing device; or it may exist independently and not be assembled into the BMS parallel addressing device.

[0143] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by the BMS parallel addressing device, the BMS parallel addressing device causes the following: it sends an initialization instruction to the BMS module to put the BMS module into an addressable state; it determines a master unit from the BMS module and assigns a master address to the master unit; it sends an addressing instruction to the master unit to generate an encoded signal containing the master address; it transmits the encoded signal sequentially among the remaining BMS modules and designates the BMS module that receives the encoded signal as a slave unit; and it assigns a corresponding slave address to each slave unit sequentially based on the address allocation rules and the encoded signal.

[0144] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0146] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0147] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described BMS parallel addressing method, thereby solving the technical problem of how to achieve automatic and accurate allocation of BMS parallel addresses. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the BMS parallel addressing method provided in the above embodiments, and will not be repeated here.

[0148] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the BMS parallel addressing method described above.

[0149] The computer program product provided in this application can solve the technical problem of how to achieve automatic and accurate allocation of BMS parallel addresses. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the BMS parallel addressing method provided in the above embodiments, and will not be repeated here.

[0150] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A BMS parallel addressing method, characterized in that, The method is applied to a BMS addresser, which is connected to both a BMS module and a device to be powered. The method includes: Send an initialization command to the BMS module to put the BMS module into an addressable state; The host unit is determined from the BMS module, and a host address is assigned to the host unit; Send an addressing instruction to the host unit so that the host unit generates an encoded signal containing the host address; The encoded signal is transmitted sequentially among the remaining BMS modules, and the BMS module that receives the encoded signal is used as a slave unit. Based on the address allocation rules and the encoded signal, each slave unit is sequentially assigned a corresponding slave address; The step of determining the host unit from the BMS module and assigning a host address to the host unit includes: Obtain the status information of the BMS module in the addressing state. The status information includes a Boolean value indicating whether the inverter has been connected, or a Boolean value indicating whether the 232 communication port has been connected. The status information is analyzed according to a preset priority order to determine the host unit from the BMS modules. The preset priority order is that the BMS module connected to the inverter takes priority over all other BMS modules. If no BMS module is connected to the inverter, the BMS module connected to the 232 communication port takes priority over all other BMS modules. Send an address allocation instruction to the host unit to allocate a host address to the host unit.

2. The method as described in claim 1, characterized in that, The step of analyzing the state information according to a preset priority order includes: Obtain the current device information of the device to be powered; Based on the current device information, the BMS units within the BMS module are sorted by priority weight according to a preset priority order. The host unit is determined from the BMS units according to the priority weight sorting.

3. The method as described in claim 1, characterized in that, After the step of determining the host unit from the BMS module, the method further includes: Monitor the connection status between the host unit and the device to be powered; If a change in the connection status is detected, then based on the preset priority order and the updated connection status, it is determined whether the host unit needs to be re-determined. If so, then based on the updated connection status, the step of determining the host unit from the BMS module is re-executed.

4. The method as described in claim 1, characterized in that, The step of sequentially assigning corresponding slave addresses to each slave unit based on the address allocation rules and the encoded signal includes: The received encoded signal is decoded to obtain the preceding address information; Based on the preceding address information and the address allocation rules, the candidate address of the slave unit is determined; Determine whether the candidate slave address conflicts with an address already assigned to another slave unit; If it is determined that there is no conflict, the candidate slave address is determined as the slave address of the current slave unit.

5. The method as described in claim 1, characterized in that, After the step of sequentially assigning corresponding slave addresses to each of the slave units, the method further includes: Conflict monitoring is performed on each of the slave device addresses; If an address conflict is detected in the slave address, the state of the slave unit with the address conflict is reset to the addressing pending state; The host unit is resent the addressing start command to generate a new slave address for the slave unit that is in the addressing pending state.

6. A BMS parallel addressing device, characterized in that, The device includes: An initialization module is used to send initialization commands to the BMS module so that the BMS module enters the addressing state. The host address allocation module is used to determine the host unit from the BMS module and allocate a host address to the host unit; The instruction sending module is used to send an addressing instruction to the host unit so that the host unit generates an encoded signal containing the host address; The slave unit allocation module is used to transmit the encoded signal sequentially among the remaining BMS modules, and to designate the BMS module that receives the encoded signal as a slave unit. The slave address allocation module is used to sequentially allocate corresponding slave addresses to each of the slave units based on the address allocation rules and the encoded signal; The host address allocation module is further configured to acquire the status information of the BMS module in the pending addressing state, the status information including a Boolean value indicating whether it is connected to the inverter, or a Boolean value indicating whether it is connected to the 232 communication port; analyze the status information according to a preset priority order, determine the host unit from the BMS modules, the preset priority order being that the BMS module connected to the inverter takes precedence over all other BMS modules, if no BMS module is connected to the inverter, then the BMS module connected to the 232 communication port takes precedence over all other BMS modules; send an address allocation instruction to the host unit, and allocate a host address to the host unit.

7. A BMS parallel addressing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the BMS parallel addressing method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the BMS parallel addressing method as described in any one of claims 1 to 5.

9. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the BMS parallel addressing method as described in any one of claims 1 to 5.

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