Ultra-high voltage junction field effect transistor device with high lightning surge tolerance and manufacturing method thereof

Abstract

The application provides a super-high-voltage junction field-effect tube device with high lightning surge tolerance and a manufacturing method thereof. The super-high-voltage junction field-effect tube device comprises a substrate, the substrate has a first deep well, a second deep well, a first high-doped well and a second high-doped well, the second high-doped well is in communication with the first deep well and the second deep well; the substrate has a one-well connected with the first high-doped well, the one-well has a first body region formed therein; the substrate has a two-well connected with the second high-doped well, the two-well has a second body region formed therein; the first deep well has a source electrode formed therein, the second deep well has a drain electrode formed therein, the second deep well has an isolation layer formed thereon, and the isolation layer has a gate electrode formed thereon; the first body region is in communication with the gate electrode through a contact hole, the source electrode and the drain electrode each has a contact hole, and the second body region has no contact hole. The application removes the contact hole of the second body region, adds a high-doped well, increases the length of the lightning current path, and improves the lightning surge performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices and processes, specifically relating to an ultra-high voltage junction field-effect transistor device with high lightning surge tolerance and its fabrication method. Background Technology

[0002] Ultra-high voltage junction field-effect transistors (JEFTs) are widely used in LED driver circuits as key high-voltage starting devices for internal circuit startup and power supply due to their high withstand voltage, low turn-off voltage, and good current carrying capacity.

[0003] For LED products, especially those used outdoors, meeting national and international electromagnetic compatibility (EMC) standards is crucial. These standards require products to have a certain level of lightning surge immunity. Specifically, lightning surge testing for LED products involves applying a lightning pulse with a standard voltage or current waveform to the mains power supply. This test aims to simulate the performance of electrical and electronic equipment during circuit startup, shutdown, or when subjected to a lightning strike, ensuring that the product can maintain stable operation when facing surges (impacts). Therefore, the lightning surge performance of ultra-high voltage junction field-effect transistors (JEFTs) is also critical.

[0004] like Figure 1 The diagram shows the structure of an ultra-high voltage junction field-effect transistor (JFET) device fabricated using a 12-layer photomask, comprising a first body region (Bulk1) 101 and a second body region (Bulk2) 102. The first body region (Bulk1) 101 is the main body of the device, directly related to the main electrodes such as the source (Source) 2, drain (Drain) 4, and gate (Gate) 3, playing a dominant role in the normal operating mode of the device, providing current paths and charge storage functions. The second body region (Bulk2) 102 is an additional body region used for electrical isolation, current dissipation, or voltage withstand enhancement.

[0005] When a lightning surge occurs, the instantaneously generated overvoltage and overcurrent will rapidly flow through the drain 4 of the device to the second body region (Bulk2) 102, i.e., the fastest discharge path shown in ① in the figure. Because the amplitude of the lightning overcurrent is large and the concentrated heat generation is rapid, the device cannot absorb this heat in time, which can easily lead to the device burning out and failing. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention proposes an ultra-high voltage junction field-effect transistor device with high lightning surge tolerance and its manufacturing method.

[0007] To achieve the above objectives, according to one aspect of the present invention, an ultra-high voltage junction field-effect transistor device with high lightning surge tolerance is provided, comprising a substrate having a first deep well, a second deep well, a first highly doped well, and a second highly doped well therein, wherein the second highly doped well is connected to the first deep well and the second deep well, respectively.

[0008] The substrate also has a well connected to the first highly doped well, and a first bulk region is formed in the well;

[0009] The substrate also has a second well connected to a second highly doped well, and a second bulk region is formed in the second well;

[0010] A source electrode is formed in the first deep well, a drain electrode is formed in the second deep well, an isolation layer is provided above the second deep well, and a gate electrode is provided on the isolation layer; a second body region is located between the source electrode and the drain electrode.

[0011] The first body region, source, second body region, gate, and drain are isolated from each other by isolation structures.

[0012] The first body region is connected to the gate through a contact hole, the source and drain each have contact holes, and the second body region has no contact holes.

[0013] According to the above scheme, the doping types of the first deep well and the second deep well are opposite to those of the substrate, while the doping types of the first highly doped well, the second highly doped well, the first well, and the second well are the same as those of the substrate.

[0014] According to the above scheme, the first highly doped well is connected to the second deep well; or

[0015] There is a certain distance between the first heavily doped well and the second deep well.

[0016] According to the above scheme, the first deep well and the second deep well are arranged side by side and have the same depth; the width of the second deep well is greater than that of the first deep well; the depth is in the thickness direction of the substrate, and the width is in the direction of the distance between the drain and the source.

[0017] According to the above scheme, the first highly doped well and the second highly doped well are arranged side by side and have the same depth; the depth of the second highly doped well is less than the depth of the second deep well.

[0018] According to the above scheme, there is a certain distance between the first highly doped well and the second highly doped well, so that the lightning current can pass through it and reach the source.

[0019] According to the above scheme, the substrate is a P-type substrate, the first deep well and the second deep well are deep N-type wells, the first highly doped well and the second highly doped well are highly doped P-type wells, the first well and the second well are P-type wells, the first body region and the second body region are P-type heavily doped regions, and the source, gate and drain are N-type heavily doped regions.

[0020] According to the above scheme, the substrate is an N-type substrate, the first deep well and the second deep well are deep P-type wells, the first highly doped well and the second highly doped well are highly doped N-type wells, the first well and the second well are N-type wells, the first body region and the second body region are N-type heavily doped regions, and the source, gate and drain are P-type heavily doped regions.

[0021] According to another aspect of the present invention, a method for fabricating the ultra-high voltage junction field-effect transistor device is provided.

[0022] When forming a highly doped well, a first highly doped well and a second highly doped well are formed respectively; wherein, a certain distance is provided between the first highly doped well and the second highly doped well;

[0023] When forming the contact hole, it is not necessary to form a contact hole in the second body region.

[0024] According to the above method, when forming the first highly doped well, the first highly doped well is connected to the second deep well; or there is a certain distance between the first highly doped well and the second deep well.

[0025] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0026] This invention removes the contact hole in the second body region and adds a first highly doped well. An unexpected effect is that removing the contact hole prevents lightning current from flowing from the drain to the second body region. The added first highly doped well is connected to a well in the first body region. Because there is a certain distance between the first and second highly doped wells, the lightning current flows from the drain through the second deep well, the first deep well, and then between the first and second highly doped wells to reach the source. Since the distance between the source and drain is greater than the distance between the second body region and the drain, the length of the lightning current path is increased, thereby increasing the total resistance. Without increasing the chip area, this increases the device's ability to absorb lightning current, reduces the peak lightning current, and thus improves lightning surge performance. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an existing ultra-high voltage JEFT device.

[0028] Figure 2 This is a schematic diagram of an ultra-high voltage JEFT device according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of the device structure according to another embodiment of the present invention.

[0030] Figure 4 yes Figure 1 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 500V.

[0031] Figure 5 yes Figure 1 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 550V.

[0032] Figure 6 yes Figure 1 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 600V.

[0033] Figure 7 yes Figure 1 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 650V.

[0034] Figure 8 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 500V.

[0035] Figure 9 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 550V.

[0036] Figure 10 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 600V.

[0037] Figure 11 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 650V.

[0038] Figure 12 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 700V.

[0039] Figure 13 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 725V.

[0040] Figure 14 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 750V.

[0041] Figure 15 yes Figure 2 The TCAD result diagram of the device structure shown is corresponding to a lightning strike voltage of 800V.

[0042] Figure 16 yes Figure 1 The diagram shows the relationship between Vd and Id for the device structure when struck by lightning at a voltage of 750V.

[0043] Figure 17 yes Figure 1The diagram shows the relationship between Vd and Is for a lightning strike voltage of 750V.

[0044] Figure 18 yes Figure 1 The diagram shows the relationship between Vd and Ib for the device structure when struck by lightning at a voltage of 750V.

[0045] Figure 19 yes Figure 1 The diagram shows the relationship between Vd and Ig for the device structure when struck by lightning at a voltage of 750V.

[0046] Figure 20 yes Figure 1 The diagram shows the electron current distribution corresponding to the device structure shown.

[0047] Figure 21 yes Figure 1 The hole current distribution diagram corresponding to the device structure shown.

[0048] Figure 22 yes Figure 2 The diagram shows the relationship between Vd and Id for the device structure when struck by lightning at a voltage of 750V.

[0049] Figure 23 yes Figure 2 The diagram shows the relationship between Vd and Is for a lightning strike voltage of 750V.

[0050] Figure 24 yes Figure 1 The diagram shows the relationship between Vd and Ib for the device structure when struck by lightning at a voltage of 750V.

[0051] Figure 25 yes Figure 1 The diagram shows the relationship between Vd and Ig for the device structure when struck by lightning at a voltage of 750V.

[0052] Figure 26 yes Figure 2 The diagram shows the electron current distribution corresponding to the device structure shown.

[0053] Figure 27 yes Figure 2 The hole current distribution diagram corresponding to the device structure shown.

[0054] In the figure: 101-first body region, 102-second body region, 2-source, 3-gate, 4-drain, 5-substrate, 601-first deep well, 602-second deep well, 701-first highly doped well, 702-second highly doped well, 801-first well, 802-second well, 901-contact hole, 10-isolation layer. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0056] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0058] To improve the surge immunity of JEFT devices, the innovative approach of this invention is to increase the length of the lightning current path, thereby increasing the total resistance and thus enhancing the device's ability to absorb lightning current. Specifically, the technical solution involves removing the contact hole in the second bulk region, thereby altering the lightning current path and preventing it from flowing from the drain into the nearby second bulk region. Simultaneously, a new highly doped well is added, connected to a well in the first bulk region. The location and dimensions of this highly doped well are carefully designed to guide the lightning current through the deep well within the bulk, passing between the two highly doped wells, and flowing into the source.

[0059] To achieve the above-mentioned innovative approach, this invention provides a high-voltage junction field-effect transistor (JFET) device with high surge withstand capability. Specifically, the structure includes a substrate containing a first deep well, a second deep well, a first heavily doped well, and a second heavily doped well, wherein the second heavily doped well is connected to both the first and second deep wells. The substrate also contains a well connected to the first heavily doped well, in which a first body region is formed. Furthermore, the substrate contains a second well connected to the second heavily doped well, in which a second body region is formed. A source electrode is formed in the first deep well, and a drain electrode is formed in the second deep well. An isolation layer is located above the second deep well, and a gate electrode is formed on the isolation layer. The second body region is located between the source and drain electrodes. The first body region, source, second body region, gate, and drain electrodes are mutually isolated by isolation structures. The first body region is connected to the gate electrode through contact holes, the source and drain electrodes each have contact holes, and the second body region has no contact holes.

[0060] Furthermore, the doping types of the first deep well and the second deep well are opposite to those of the substrate, while the doping types of the first highly doped well, the second highly doped well, the first well, and the second well are the same as those of the substrate.

[0061] The present invention will be further described below with reference to specific examples and accompanying drawings.

[0062] Example 1:

[0063] This embodiment provides an ultra-high voltage junction field-effect transistor (JFET) device with high lightning surge withstand capability, such as... Figure 2 As shown, the substrate includes a substrate 5, which has a first deep well 601, a second deep well 602, a first highly doped well 701 and a second highly doped well 702, wherein the second highly doped well 702 is connected to the first deep well 601 and the second deep well 602 respectively.

[0064] The substrate 5 also has a first well 801 connected to the first highly doped well 701, and a first body region 101 is formed in the first well 801; the substrate 5 also has a second well 802 connected to the second highly doped well 702, and a second body region 102 is formed in the second well 802.

[0065] A source electrode 2 is formed in a first deep well 601, and a drain electrode 4 is formed in a second deep well 602. An isolation layer 10 is provided above the second deep well 602, and a gate electrode 3 is provided on the isolation layer 10. A second body region 102 is located between the source electrode 2 and the drain electrode 4. In this embodiment, the first body region 101, the source electrode 2, the second body region 102, the gate electrode 3, and the drain electrode 4 are arranged sequentially. The first body region 101, the source electrode 2, the second body region 102, the gate electrode 3, and the drain electrode 4 are isolated from each other by isolation structures.

[0066] The first body region 101 is connected to the gate 3 through a contact hole 901, which is filled with metal to achieve interconnection. The source 2 and drain 4 each have contact holes, which are filled with metal and then led out to the source 2 and drain 4 respectively. The second body region 102 has no contact holes.

[0067] Because the second body region 102 has no contact holes, lightning current cannot pass through the device body from the drain 4 to reach the relatively close second body region 102. Since the newly added first highly doped well 701 is connected to a well 801 in the first body region 101, the first highly doped well 701 is typically located below the first body region 101, or below the first body region 101 and the source 2. By properly setting the position and size of the first highly doped well 701, ensuring a certain distance between it and the second highly doped well 702, the lightning current can be guided to pass through the second deep well 602 within the device body, through the first deep well 601 between the first and second highly doped wells 701, and flow into the source 2.

[0068] The doping types of the first deep well 601 and the second deep well 602 are opposite to those of the substrate 5, while the doping types of the first highly doped well 701, the second highly doped well 702, the first well 801 and the second well 802 are the same as those of the substrate.

[0069] Taking a P-type substrate as an example, substrate 5 is a P-type substrate. Both the first deep well 601 and the second deep well 602 are deep N-wells (DNWs). A deep N-well is a relatively deep N-type doped region formed in a semiconductor substrate, typically used to provide electrical isolation or as a substrate portion for specific devices. It is usually deeper than a conventional N-well and has a higher doping concentration, used to enhance isolation or achieve specific electrical characteristics.

[0070] Both the first highly doped well 701 and the second highly doped well 702 are highly doped P-regions (HPW). A highly doped P-region refers to a region with a high concentration of P-type doping formed in a semiconductor substrate. Such regions are typically used to form low-resistance contact regions or specific device structures, such as P-type diffusion regions or P-type implantation regions.

[0071] Both well 801 and well 802 are P-type wells (PWs). A P-type well is a P-type doped region formed in a semiconductor substrate, typically used to isolate different devices or form specific device structures. The doping concentration of P-type wells is usually lower than that of highly doped P-type regions, primarily used to provide electrical isolation or as part of a device. In this embodiment, well 801 and well 802 are used to form the first body region 101 and the second body region 102.

[0072] In some embodiments, the first deep well 601 and the second deep well 602 are arranged side by side and have the same depth, and can be obtained under the same process. It should be noted that "side by side" means that... Figure 2 The lateral direction; the depth is the thickness direction of substrate 5, i.e. Figure 2 The height direction in the middle.

[0073] In some embodiments, the first highly doped well 701 and the second highly doped well 702 are arranged side by side and have the same depth, and can be obtained under the same process. At the same time, the depth of the first highly doped well 701 and the second highly doped well 702 is less than the depth of the first deep well 601 and the second deep well 602.

[0074] There is a certain distance between the first highly doped well 701 and the second highly doped well 702, allowing the lightning current to pass through and reach the source 2. This distance is such that the two will not come into contact under process conditions. The newly added first highly doped well 701 is only limited in its positional relationship with the second highly doped well 702, and its positional relationship and connection relationship with the first well 801; other aspects are not limited, as long as they do not affect the device's performance. In this embodiment, the first highly doped well 701 is not only located below the first well 801, but is also connected to the first deep well 601, such as... Figure 2 As shown. When the first highly doped well 701 is connected to the first deep well 601, the distance B between the first highly doped well 701 and the first deep well 601 is considered to be negative, representing the length of the connection portion between the first highly doped well 701 and the first deep well 601, i.e. Figure 2 The length of the overlapping portion between the first highly doped well 701 and the first deep well 601.

[0075] In the structure of this embodiment, the path of the lightning current is from... Figure 2 In the diagram, ① becomes ②. Specifically, the leakage path shown in ① is: passing through the second deep well 602 below the drain 4, and then through the second deep well 602 above the second highly doped well 702 to the second well 802, finally reaching the second body region 102. When the second body region 102 no longer has contact holes, the lightning current path changes to ②: passing through the second deep well 602 below the drain 4, and then sequentially passing through the second deep well 602, substrate 5, and first deep well 601 below the second highly doped well 702, and passing through the first deep well 601 between the first highly doped well 701 and the second highly doped well 702 to reach the source 2. As can be seen from the figure, the leakage path shown in ② is significantly longer than the leakage path shown in ①. Therefore, this invention increases the length of the lightning current path and increases the total resistance. Without increasing the chip area, it increases the device's ability to absorb lightning current and reduces the peak lightning current. The structure described in this invention has superior lightning surge performance.

[0076] Taking a certain 500V JEFT device as an example, for Figure 1 The existing technology structure shown and Figure 2 The structure of the present invention shown is subjected to simulation analysis. Figure 1 The TCAD (Technology Computer-Aided Design) results corresponding to the existing technology structure shown are as follows: Figures 4 to 7 The figures show the results for lightning strike voltages of 500V, 550V, 600V, and 650V, respectively. The horizontal axis represents the drain voltage Vd, the vertical axis represents the drain current Id, and BSL is an abbreviation for baseline, representing the simulation curve of the prior art. In this embodiment, it is... Figure 1 The diagram shows the variation of drain current Id with drain voltage Vd under the existing technology structure.

[0077] Figure 2 The TCAD results corresponding to the improved structure of this invention are shown below. Figure 8-15 The figures show the results at lightning strike voltages of 500V, 550V, 600V, 650V, 700V, 725V, 750V, and 800V, respectively. The horizontal axis represents the drain voltage Vd, the vertical axis represents the drain current Id, and B is the distance between the first highly doped well 701 and the first deep well 601. B = -6μm indicates that the first highly doped well 701 and the first deep well 601 are connected, and the length of the connection between them is 6μm. Figure 2 The length of the overlapping portion of the first highly doped well 701 and the first deep well 601 in the lateral direction.

[0078] pass Figures 4-15 The conclusions of the comparative analysis of the structure's resistance to lightning strike voltage are shown in Table 1.

[0079] Table 1

[0080]

[0081] Table 1 shows the corresponding diagrams for the existing technical structures. Figures 4-7 Since the experiment failed at lightning strike voltages of 600V and 650V, it indicates that further increases in lightning strike voltage will also lead to failure. Therefore, experiments were not conducted at lightning strike voltages of 700V and above, and are indicated by "-". As shown in Table 1, the existing technology structure fails at lightning strike voltages of 600V and above, while the structure of this invention withstands lightning strike voltages of at least 700V. Therefore, the structure of this invention exhibits higher lightning strike voltage resistance.

[0082] Continuing with a 500V JEFT device as an example, for Figure 1 The existing technology structure shown and Figure 2 The structure of this invention is shown for comparison with current distribution. At a lightning strike voltage of 750V, Figure 1The current distribution diagram corresponding to the device structure shown is as follows: Figure 16-19 As shown, where Figure 16 yes Figure 1 The diagram shows the relationship between drain voltage Vd and drain current Id for a device structure subjected to a lightning strike voltage of 750V. Figure 17 yes Figure 1 The diagram shows the relationship between drain voltage Vd and source current Is for a device structure subjected to a lightning strike voltage of 750V. Figure 18 yes Figure 1 The diagram shows the relationship between drain voltage Vd and substrate current Ib for a device structure subjected to a lightning strike voltage of 750V. Figure 19 yes Figure 1 The diagram shows the relationship between drain voltage Vd and gate current Ig for a lightning strike voltage of 750V. At a lightning strike voltage of 750V... Figure 1 The distributions of electron current (E current, the current generated by the movement of electrons) and hole current (H current, the current generated by the movement of holes) corresponding to the device structure shown are as follows: Figure 20 and Figure 21 As shown in the figure, the horizontal axis is Figure 1 The device structure shown is positioned laterally, with the x-coordinate 0 point being the midpoint of the second body region 102, and the y-coordinate being... Figure 1 The depth direction of the device structure shown, i.e. Figure 1 The height direction, with the ordinate 0 point representing the substrate surface direction, i.e. Figure 1 The lower surfaces of the first body region 101 and the second body region 102.

[0083] When the lightning strike voltage is 750V, Figure 2 The current distribution diagram corresponding to the device structure shown is as follows: Figure 22-25 As shown, where Figure 22 yes Figure 2 The diagram shows the relationship between drain voltage Vd and drain current Id for a device structure subjected to a lightning strike voltage of 750V. Figure 23 yes Figure 2 The diagram shows the relationship between drain voltage Vd and source current Is for a device structure subjected to a lightning strike voltage of 750V. Figure 24 yes Figure 1 The diagram shows the relationship between drain voltage Vd and substrate current Ib for a device structure subjected to a lightning strike voltage of 750V. Figure 25 yes Figure 1 The diagram shows the relationship between drain voltage Vd and gate current Ig for a lightning strike voltage of 750V. At a lightning strike voltage of 750V... Figure 2 The electron current distribution and hole current distribution corresponding to the device structure shown are as follows: Figure 26 and Figure 27 As shown in the figure, the horizontal axis is Figure 2The device structure shown is positioned laterally, with the x-coordinate 0 point being the midpoint of the second body region 102, and the y-coordinate being... Figure 2 The depth direction of the device structure shown, i.e. Figure 2 The height direction, with the ordinate 0 point representing the substrate surface direction, i.e. Figure 2 The lower surfaces of the first body region 101 and the second body region 102.

[0084] Through the Figures 16-27 The comparison clearly shows that the structure of the present invention can change the lightning current path and reduce the peak value of the lightning current.

[0085] It should be noted that, in the above comparison, the difference between the structure of the present invention and the structure of the prior art is limited to removing the contact hole in the second body region and adding a first highly doped well. Other structural parameters such as shape, position, connection relationship and size are the same.

[0086] In some embodiments, the substrate is an N-type substrate, and this scheme is still applicable, except that the specific type of doping will be set according to the substrate. Specifically, when the substrate is an N-type substrate, the first deep well and the second deep well are deep P-type wells, the first heavily doped well and the second heavily doped well are heavily doped N-type wells, the first well and the second well are N-type wells, the first body region and the second body region are heavily doped N-type regions, and the source, gate and drain are heavily doped P-type regions.

[0087] According to another aspect of the present invention, this embodiment also provides a method for fabricating the ultra-high voltage junction field-effect transistor device. The other steps of the present invention are consistent with conventional steps, except that when forming the highly doped wells, a first highly doped well 701 and a second highly doped well 702 are formed respectively; wherein a certain distance is provided between the first highly doped well 701 and the second highly doped well 702, this distance ensuring that subsequent processes will not connect the two highly doped wells. Furthermore, when forming the contact hole, it is not necessary to form a contact hole in the second body region 102.

[0088] Of course, in this embodiment, in order to make the first highly doped well 701 and the first deep well 601 form a partially overlapping region, attention needs to be paid to the formation region and position of the first highly doped well 701 when forming the first highly doped well 701 and the second highly doped well 702.

[0089] Example 2:

[0090] The structure and principle of this embodiment are basically the same as those of Embodiment 1, such as... Figure 3As shown, the substrate includes a substrate 5, which has a first deep well 601, a second deep well 602, a first heavily doped well 701, and a second heavily doped well 702, wherein the second heavily doped well 702 is connected to both the first deep well 601 and the second deep well 602. The substrate 5 also has a first well 801 connected to the first heavily doped well 701, in which a first body region 101 is formed; and a second well 802 connected to the second heavily doped well 702, in which a second body region 102 is formed.

[0091] A source electrode 2 is formed in a first deep well 601, and a drain electrode 4 is formed in a second deep well 602. An isolation layer 10 is provided above the second deep well 602, and a gate electrode 3 is provided on the isolation layer 10. A second body region 102 is located between the source electrode 2 and the drain electrode 4. In this embodiment, the first body region 101, the source electrode 2, the second body region 102, the gate electrode 3, and the drain electrode 4 are arranged sequentially. The first body region 101, the source electrode 2, the second body region 102, the gate electrode 3, and the drain electrode 4 are isolated from each other by isolation structures.

[0092] The first body region 101 is connected to the gate 3 through a contact hole 901, which is filled with metal to achieve interconnection. The source 2 and drain 4 each have contact holes, which are filled with metal and then led out to the source 2 and drain 4 respectively. The second body region 102 has no contact holes.

[0093] Because the second body region 102 has no contact holes, lightning current cannot pass through the device body from the drain 4 to reach the relatively close second body region 102. Since the newly added first highly doped well 701 is connected to a well 801 in the first body region 101, the first highly doped well 701 is typically located below the first body region 101, or below the first body region 101 and the source 2. By properly setting the position and size of the first highly doped well 701, ensuring a certain distance between it and the second highly doped well 702, the lightning current can be guided to pass through the second deep well 602 within the device body, through the first deep well 601 between the first and second highly doped wells 701, and flow into the source 2.

[0094] Continue as Figure 3 As shown, the difference from Embodiment 1 is that the first highly doped well 701 in this embodiment is only located below the first well 801 and does not contact the first deep well 601. That is, the distance B between the first highly doped well 701 and the first deep well 601 is a positive value.

[0095] Similarly, this embodiment also provides a method for fabricating the ultra-high voltage junction field-effect transistor device. The other steps of this invention are consistent with conventional steps, except that when forming the highly doped wells, a first highly doped well 701 and a second highly doped well 702 are formed respectively. A certain distance is maintained between the first highly doped well 701 and the second highly doped well 702, ensuring that subsequent processes will not connect the two highly doped wells. Furthermore, when forming the contact hole, it is not necessary to form a contact hole in the second body region 102.

[0096] Of course, in this embodiment, in order to ensure that the first highly doped well 701 and the first deep well 601 do not overlap, that is, that there is a certain distance between them, attention needs to be paid to the formation area and position of the first highly doped well 701 when forming the first highly doped well 701 and the second highly doped well 702.

[0097] It should be noted that the above embodiments only provide a cross-sectional view along the depth direction of the device structure. The structure in other view directions is not limited; it only requires removing the contact hole in the second body region and adding a first highly doped well. Removing the contact hole in the second body region prevents lightning current from flowing from the drain to the second body region. Adding a first highly doped well connected to the first body region and at a certain distance from the second highly doped well allows the lightning current to pass from the drain through the second deep well, the first deep well, and between the first and second highly doped wells to reach the source. By adopting the structure of this invention, the distance between the source and drain is greater than the distance between the second body region and the drain, thus increasing the length of the lightning current path and consequently increasing the total resistance. Without increasing the chip area, this increases the device's ability to absorb lightning current, reduces the peak lightning current, and ultimately improves lightning surge performance.

[0098] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0099] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high lightning surge withstand voltage super junction field effect transistor device, characterized by: The substrate has a first high-doped well, a first deep well and a second deep well arranged in sequence, and further has a second high-doped well in communication with the first deep well and the second deep well respectively; The substrate further has a first well connected with the first high-doped well, and the first well has a first body region formed therein; The substrate further has a second well connected with the second high-doped well, and the second well has a second body region formed therein; The first deep well has a source electrode formed therein, the second deep well has a drain electrode formed therein, and the second deep well has an isolation layer formed thereon, and the isolation layer has a gate electrode formed thereon; the second body region is located between the source electrode and the drain electrode; The first body region, the source electrode, the second body region, the gate electrode and the drain electrode are isolated from each other by isolation structures respectively; The first body region is in communication with the gate electrode through a contact hole, the source electrode and the drain electrode each has a contact hole, and the second body region has no contact hole; The first deep well and the second deep well have a doping type opposite to that of the substrate, and the first high-doped well, the second high-doped well, the first well and the second well have a doping type same as that of the substrate; The first high-doped well and the second high-doped well have a certain distance therebetween, and the lightning stroke current passes through the distance to reach the source electrode.

2. The super-junction field effect transistor device of claim 1, wherein: The first high-doped well is connected with the first deep well; or The first high-doped well has a certain distance from the first deep well.

3. The super-junction field effect transistor device of claim 1, wherein: The first deep well and the second deep well are arranged side by side and have the same depth; the second deep well has a width greater than that of the first deep well; the depth is in the thickness direction of the substrate, and the width is in the distance direction between the drain electrode and the source electrode.

4. The super-junction field effect transistor device of claim 1, wherein: The first high-doped well and the second high-doped well are arranged side by side and have the same depth; the second high-doped well has a depth less than that of the second deep well.

5. The super-junction field effect transistor device according to any one of claims 1 to 4, wherein: The substrate is a P-type substrate, the first deep well and the second deep well are deep N-type wells, the first high-doped well and the second high-doped well are high-doped P-type wells, the first well and the second well are P-type wells, the first body region and the second body region are P-type heavily doped regions, and the source electrode, the gate electrode and the drain electrode are N-type heavily doped regions.

6. The super-junction field effect transistor device according to any one of claims 1 to 4, wherein: The substrate is an N-type substrate, the first deep well and the second deep well are deep P-type wells, the first high-doped well and the second high-doped well are high-doped N-type wells, the first well and the second well are N-type wells, the first body region and the second body region are N-type heavily doped regions, and the source electrode, the gate electrode and the drain electrode are P-type heavily doped regions.

7. A manufacturing method of the super-high-voltage junction field effect transistor device according to any one of claims 1 to 6, characterized in that: When the high-doped well is formed, the first high-doped well and the second high-doped well are formed respectively; and a certain distance is provided between the first high-doped well and the second high-doped well; When the contact hole is formed, the contact hole of the second body region is not formed.

8. The method of claim 7, wherein the step of forming the super junction field effect transistor device further comprises the step of: When the first high-doped well is formed, the first high-doped well is connected with the first deep well; or the first high-doped well has a certain distance from the first deep well. ​

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