Capacitor, circuit board assembly, chip and electronic equipment

Abstract

The embodiment of the invention provides a capacitor, a circuit board assembly, a chip and electronic equipment, and relates to the technical field of capacitors. The capacitor comprises a substrate, the surface of the substrate is provided with a plurality of cellular areas arranged in an array mode, each cellular area comprises at least three groove arrays, each groove array comprises a plurality of grooves arranged side by side, and the arrangement directions of the grooves of any two groove arrays intersect and do not coincide. Therefore, the stress distribution on the substrate can be improved, and the reliability of the capacitor can be improved.

Description

Technical Field

[0001] This application relates to the field of capacitor technology, and in particular to a capacitor, circuit board assembly, chip, and electronic device. Background Technology

[0002] Capacitors can function as energy storage, filtering, bypassing, coupling, and decoupling devices. For example, silicon capacitors use silicon as both the substrate and dielectric, and are manufactured using semiconductor processes. In related technologies, the surface of the capacitor substrate has an array of trenches, with multiple trenches spaced apart. A dielectric layer is formed on the inner walls of the trenches and the surface of the substrate, and an electrode layer is formed on the surface of the dielectric layer away from the substrate, forming a substrate-dielectric-electrode capacitor structure. However, because the trenches are elongated, stress is introduced into the trenches after the dielectric layer is formed. This uneven stress distribution on the substrate leads to stress concentration areas, reducing the reliability of the capacitor. Summary of the Invention

[0003] This application provides a capacitor, circuit board assembly, chip, and electronic device that can improve stress distribution on a substrate and enhance the reliability of the capacitor.

[0004] A first aspect of this application provides a capacitor comprising a substrate, the surface of which has a plurality of cell regions arranged in an array. Each cell region includes at least three trench arrays, and each trench array includes a plurality of trenches arranged side by side, wherein the arrangement directions of the trenches in any two trench arrays intersect but do not overlap.

[0005] The capacitor provided in this application embodiment arranges multiple trenches in at least three different directions to form at least three trench arrays. The trench arrangement directions of any two trench arrays are different, which can distribute the total stress on the substrate in multiple directions. This reduces the stress on the substrate in a single direction, reduces the average stress on the substrate, and creates better stress dispersion characteristics. This reduces substrate warpage and / or cracking, improves substrate reliability, and thus improves capacitor reliability. Furthermore, during the semiconductor manufacturing process, this stress dispersion characteristic prevents wafer warpage or cracking, improving product yield. Additionally, when a high-dielectric-constant dielectric material is deposited in the trenches, the stress introduced by the dielectric material is less than the upper limit of the stress that the silicon pillars can withstand, allowing the capacitor to increase its capacitance value by using a high-dielectric-constant dielectric material. Moreover, it improves process compatibility, allowing the use of processes that are not available in conventional technologies to deposit high-dielectric-constant dielectric materials in the trenches. Finally, the lower stress on the substrate in a single direction prevents the dielectric material from separating from the substrate and / or the silicon pillars from cracking, ensuring that the capacitor's performance is not degraded or that the capacitor does not fail, and preventing long-term reliability issues.

[0006] In some possible implementations, the included angle between the arrangement directions of multiple trenches in two adjacent trench arrays in the cell region is 360° / N, where N is the number of trench arrays. This ensures that the included angle between the arrangement directions of multiple trenches in two adjacent trench arrays is the same, resulting in uniform deformation throughout the substrate. This further improves the stress distribution on the substrate and enhances the reliability of the capacitor.

[0007] In some possible implementations, at least two trench arrays in the cell region have the same number of trenches.

[0008] In some possible implementations, at least two trenches in at least one trench array in the cell region have the same length.

[0009] By controlling the arrangement of multiple trench arrays in the cell region, the number of trenches in the trench array, and the length of the multiple trenches in the trench array, the stress on the substrate in a single direction can be further reduced, the stress distribution on the substrate can be improved, and this helps to increase the capacitance density of the capacitor. Here, capacitance density refers to the capacitance that a capacitor can provide per unit area.

[0010] In some possible implementations, the cell region is polygonal in shape, with 2N sides, where N is the number of trench arrays.

[0011] In some possible implementations, the shape of the cellular region is a regular polygon.

[0012] In some possible implementations, the cell region is quadrilateral in shape.

[0013] In some possible implementations, the cell region is square in shape.

[0014] In this way, the shape of the cell region is a polygon or quadrilateral with 2N sides, which can improve the area utilization of the substrate, increase the number of cell regions, and help to further improve the capacitance density of the capacitor.

[0015] In some possible implementations, the capacitor also includes a dielectric layer and an electrode layer, with the dielectric layer covering the inner walls of the trench and the surface of the substrate, and the electrode layer covering the surface of the dielectric layer.

[0016] In this way, in addition to supporting structures such as dielectric and electrode layers, the substrate can also function as an electrode to form a capacitor structure of substrate-dielectric-electrode layer.

[0017] In some possible implementations, the capacitor further includes a dielectric group and an electrode group. The dielectric group includes a plurality of dielectric layers arranged along the thickness direction of the substrate, and the electrode group includes a plurality of electrode layers arranged along the thickness direction of the substrate. The dielectric layers and electrode layers are arranged alternately. The dielectric layer closest to the substrate in the dielectric group is located between the substrate and the electrode layer closest to the substrate in the electrode group. The dielectric layer closest to the substrate in the dielectric group covers the surface of the substrate and the inner wall of the trench.

[0018] In this way, besides supporting structures such as dielectric and electrode layers, the substrate can also function as an electrode, forming a capacitor structure consisting of at least two sequentially arranged loop groups. Each loop group includes a dielectric layer and an electrode layer, with the dielectric layer in the loop group closest to the substrate located between the substrate and the electrode layer. Furthermore, the more dielectric layers a capacitor has, the higher its capacitance density.

[0019] In some possible implementations, the capacitor is a silicon capacitor, and the substrate material includes silicon.

[0020] In this way, silicon capacitors can be manufactured using semiconductor processes, such as deep trench (DTC) technology, which can reduce the distance between the capacitor's electrodes and increase capacitance density. Additionally, the thickness of the capacitor can be reduced.

[0021] A second aspect of this application provides a circuit board assembly including a circuit board and a capacitor as described in any of the first aspects, the capacitor being connected to the circuit board.

[0022] A third aspect of this application provides a chip that includes a capacitor as described in any of the first aspects.

[0023] A fourth aspect of this application provides an electronic device that includes a capacitor as described in any of the first aspects. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0025] Figure 2 This is a cross-sectional schematic diagram of a capacitor provided in an embodiment of this application;

[0026] Figure 3 A cross-sectional schematic diagram of another capacitor provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of a three-dimensional structure of a substrate provided in an embodiment of this application;

[0028] Figure 5 for Figure 4 A top view of the substrate shown;

[0029] Figure 6 for Figure 5 Enlarged view within the dashed box;

[0030] Figure 7 This is a top view of a capacitor in traditional technology.

[0031] Figure 8 A top view schematic diagram of another substrate provided in an embodiment of this application;

[0032] Figure 9 for Figure 8 Enlarged view within the dashed box;

[0033] Figure 10 A top view schematic diagram of another substrate provided in an embodiment of this application;

[0034] Figure 11 for Figure 10 A schematic diagram of the hair growth within the dashed box;

[0035] Figure 12 A top view schematic diagram of another substrate provided in an embodiment of this application;

[0036] Figure 13 for Figure 12 Enlarged view within the dashed box;

[0037] Figure 14 This is a schematic diagram of the first manufacturing process of a capacitor provided in an embodiment of this application;

[0038] Figure 15 This is a schematic diagram of the second fabrication process of the capacitor provided in an embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100. Display screen;

[0041] 200, Mid-frame;

[0042] 300, back cover;

[0043] 400, battery;

[0044] 500. Circuit board assembly;

[0045] 600. Circuit board;

[0046] 700. Capacitor;

[0047] 710. Substrate; 711. Cell region;

[0048] 720, Trench array; 720A, First trench array; 720B, Second trench array; 720C, Third trench array; 720D, Fourth trench array;

[0049] 730. Trench;

[0050] 740, Dielectric layer; 750, Electrode layer; 760, Doped polysilicon layer; 770, Passivation layer; 780, Metal interconnect layer;

[0051] A1, First direction; A2, Second direction; A3, Third direction; A4, Fourth direction. Detailed Implementation

[0052] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0053] This application provides an electronic device that can be a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, a communication electronics product, or a medical device product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronics products include base stations, routers, satellite communication equipment, and optical network equipment, etc. Medical device products include implantable devices (such as pacemakers), wearable health monitoring devices (such as blood pressure monitors), and diagnostic devices (such as MRI or CT scanners).

[0054] This application does not impose any special limitations on the specific form of the above-described electronic device. For ease of explanation, the following description uses an electronic device as an example. Figure 1 The following explanation uses a mobile phone as an example. Figure 1This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0055] like Figure 1 As shown, the electronic device may include components such as a display screen 100, a mid-frame 200, a back cover 300, a battery 400, and a circuit board assembly 500. The back cover 300 and the display screen 100 are located on opposite sides of the mid-frame 200, forming an accommodating space with the mid-frame 200. The accommodating space houses components such as the battery 400, the circuit board assembly 500, and a camera module.

[0056] The display screen 100 can be a liquid crystal display (LCD), an organic light emitting diode (OLED) display screen, a micro LED display screen, a mini LED display screen, etc., and the application is not limited in this regard.

[0057] The circuit board assembly 500 may include a circuit board 600, a system-on-chip (SOC), an RF chip, a capacitor 700, resistors, etc. The circuit board 600 may be a printed circuit board (PCB). The circuit board 600 is used to carry the SOC, RF chip, capacitor 700, resistors, etc., and is electrically connected to them.

[0058] It should be noted that, in addition to its application on circuit board 600, capacitor 700 can also be used in chips or other types of circuits. A chip, also known as a semiconductor chip, can be a collection of integrated circuits fabricated on an integrated circuit substrate 710 using integrated circuit board technology. Chips can include, but are not limited to, application processor chips, video processor chips, communication chips, control chips, artificial intelligence chips, radio frequency chips, or system-on-a-chip (SoC) integrating any multiple functions of the above.

[0059] For example, capacitor 700 can be a silicon capacitor, also known as a silicon-based capacitor or silicon-based capacitor device. The substrate 710 of the silicon capacitor is made of silicon material. That is, the silicon capacitor uses silicon material as both the substrate 710 and the dielectric. Silicon material has good stability and is not easily affected by temperature, AC / DC voltage, etc., resulting in lower equivalent series resistance (ESR) and equivalent series inductance (ESL) for the silicon capacitor. This allows for achieving the corresponding impedance with fewer capacitors and lower capacitance values. Furthermore, silicon capacitors are manufactured using semiconductor processes, which can significantly reduce the distance between the capacitor terminals and greatly increase capacitance density. Simultaneously, semiconductor processes are based on wafer fabrication, allowing for extremely small thicknesses in silicon capacitors.

[0060] In some embodiments, the silicon capacitors provided in this application can be manufactured using deep trench (DTC) technology for semiconductors, so that the silicon capacitors can also be deep trench capacitors.

[0061] It should be noted that, in addition to silicon, the substrate 710 of capacitor 700 can also be made of other materials that can be manufactured by semiconductor processes, which will not be listed here.

[0062] Figure 2 This is a cross-sectional schematic diagram of a capacitor provided in an embodiment of this application. Figure 3 This is a cross-sectional schematic diagram of another capacitor provided in an embodiment of this application.

[0063] See Figure 2 As shown, the capacitor 700 may include a substrate 710 and a stacked assembly. The surface of the substrate 710 has trenches 730, and the stacked assembly covers the surface of the substrate 710 and the inner walls of the trenches 730. The stacked assembly and the substrate 710 constitute a capacitor structure. The stacked assembly may include a dielectric assembly and an electrode assembly. The dielectric assembly includes a plurality of dielectric layers 740 spaced apart along the thickness direction of the substrate 710, for example... Figure 2 As shown, the number of dielectric layers 740 can be three; of course, the number of dielectric layers 740 can also be less than or more than three. The electrode assembly includes a plurality of electrode layers 750 spaced apart along the thickness direction of the substrate 710, for example... Figure 2As shown, the number of electrode layers 750 can be three, although there can be more or fewer than three. The number of dielectric layers 740 is the same as the number of electrode layers 750, and the dielectric layers 740 and electrode layers 750 are arranged alternately. The dielectric layer 740 closest to the substrate 710 in the dielectric group is located between the substrate 710 and the electrode layer 750 closest to the substrate 710 in the electrode group. The dielectric layer 740 closest to the substrate 710 in the dielectric group covers the surface of the substrate 710 and the inner wall of the trench 730.

[0064] In addition to supporting structures such as the dielectric layer 740 and the electrode layer 750, the substrate 710 can also function as an electrode, forming a capacitor structure consisting of at least two sequentially arranged loop groups. Each loop group includes the dielectric layer 740 and the electrode layer 750, with the dielectric layer 740 in the loop group closest to the substrate 710 located between the substrate 710 and the electrode layer 750. Furthermore, the more dielectric layers 740 there are in the capacitor 700, the greater the capacitance density of the capacitor 700.

[0065] It should be noted that, in addition to being composed of multiple dielectric layers 740 and multiple electrode layers 750, in some embodiments, such as... Figure 3 As shown, the stack may also include a dielectric layer 740 and an electrode layer 750. In this case, the dielectric layer 740 covers the surface of the substrate 710 and the inner wall of the trench 730, and the electrode layer 750 covers the surface of the dielectric layer 740 away from the substrate 710, forming a capacitor structure of substrate 710-dielectric layer 740-electrode layer 750.

[0066] The dielectric layer 740 can be made of one or more materials such as nitrides, oxides, and oxynitrides. Furthermore, the dielectric layer 740 can be formed using chemical vapor deposition (CVD), derivative CVD processes, or other deposition processes. Derivative CVD processes can include low-pressure chemical vapor deposition (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or any combination thereof.

[0067] The electrode layer 750 is made of a conductive material, such as doped polycrystalline silicon, metal, or metal compound. The electrode layer 750 can also be formed by chemical vapor deposition or other deposition processes.

[0068] It should be noted that, in addition to the substrate 710 and the stacked assembly, the capacitor 700 also has other devices, such as a doped polysilicon layer 760, a metal interconnect layer 780, and metal electrodes. The doped polysilicon layer 760 is used to cover the surface of the stacked assembly and fill the trenches 730, so that the trenches 730 and the surrounding area form a void-free structure. The metal interconnect layer 780 is electrically connected to the electrode layer 750 in each trench 730, and the metal electrodes are electrically connected to the metal interconnect layer 780, serving as the interface of the capacitor 700.

[0069] Figure 4 This is a three-dimensional structural diagram of a substrate provided in an embodiment of this application. Figure 5 for Figure 4 The diagram shows a top view of the substrate. Figure 6 for Figure 5 Enlarged schematic diagram within the dashed box.

[0070] like Figure 4 As shown, there are multiple trenches 730 located on the same surface of the substrate 710. Each trench 730 is a strip-shaped structure with a length greater than its width. For example, the length of a trench 730 can be 400 nm, but other lengths are also possible. Furthermore, the depth of each trench 730 can be 7–10 μm, but it can also be less than 7 μm or more than 10 μm.

[0071] Figure 7 This is a top view of a capacitor in traditional technology.

[0072] In traditional technologies, such as Figure 7 As shown, a plurality of trench arrays 820 are disposed on the surface of the substrate 800, and the plurality of trench arrays 820 are arranged along a first direction (e.g., Figure 7 The trench array 820 includes trenches arranged side-by-side and spaced apart along the second direction (e.g., in the Y direction), and each trench array 820 includes trenches along the second direction (e.g., in the Y direction). Figure 7 Multiple trenches 830 arranged side-by-side and spaced apart (in the X direction). After a dielectric material is deposited in the trenches 830, the dielectric material compresses the sidewalls (or silicon pillars 840) between adjacent trenches 830, applying stress to the silicon pillars 840 (e.g., ...). Figure 7 As shown by the middle arrow, the stress distribution pattern on the entire substrate 800 resembles a "I" shape, with the stress mainly concentrated in the second direction. However, this stress distribution can easily lead to warping and / or cracking of the substrate 800. Furthermore, during the semiconductor manufacturing process of capacitors, this stress can also easily cause wafer warping or cracking, reducing product yield.

[0073] in addition, Figure 7The trench design in the traditional technology shown also has process compatibility issues, resulting in a bottleneck effect in capacitance improvement. Specifically, assuming... Figure 7 The silicon pillar 840 in the trench has an upper stress limit of A. If the stress generated on the silicon pillar 840 after depositing dielectric material in the trench 830 is less than A, then the process range for depositing dielectric material is narrowed. Furthermore, the range of dielectric constants of the dielectric material corresponding to a process that creates stress less than A in the trench 830 is also determined. Therefore, the process for depositing dielectric material and / or the dielectric constant of the dielectric material are both limited. For example, if a process that creates stress less than A is used to deposit a dielectric material with a high dielectric constant in the trench 830, problems such as failure to grow or breakage during growth may occur, making it impossible to use a high dielectric constant dielectric material to increase the capacitance value of the capacitor. Alternatively, a process can be used to grow a dielectric material with a high dielectric constant, but the resulting stress will be greater than A, which is also unsuitable.

[0074] also, Figure 7 In the conventional technology shown, the stress on the substrate 800 is mainly concentrated in one direction, which can easily lead to the separation of the dielectric material from the silicon pillar 840, or cracks in the dielectric material or the silicon pillar 840, resulting in reduced capacitor performance or failure and reduced long-term reliability of the capacitor.

[0075] In view of this, embodiments of this application provide a new trench design, in which the trench 730 extends in multiple directions, dispersing the stress on the substrate 710 in multiple directions, forming better stress dispersion characteristics, which helps to reduce substrate 710 warpage, and can also reduce wafer warpage, improve process compatibility and the uniformity and repeatability of subsequent surface processing processes, and improve long-term reliability.

[0076] Figure 8 This is a top view schematic diagram of another substrate provided in an embodiment of this application. Figure 9 for Figure 8 Enlarged schematic diagram within the dashed box.

[0077] Specifically, the surface of the substrate 710 provided in this application embodiment has a plurality of cell regions 711 arranged in an array, for example... Figure 8 As shown, the number of cell regions 711 can be nine, although it can also be more or less than nine. Each cell region 711 includes at least three trench arrays 720, for example... Figure 6 As shown, each cell region 711 can include three trench arrays 720. Of course, the number of trench arrays 720 can also be more than three, for example... Figure 9 As shown, the number of trench arrays 720 can be four. Each trench array 720 includes multiple trenches 730 arranged side by side, for example... Figure 6As shown, each trench array 720 may include seven trenches 730 arranged side by side and spaced apart. Of course, the number of trenches 730 in the trench array 720 may be less than or more than seven.

[0078] The arrangement directions of the multiple trenches 730 in any two trench arrays 720 intersect but do not overlap. In some embodiments, such as Figure 6 As shown, the cell region 711 may include a first trench array 720A, a second trench array 720B, and a third trench array 720C. A plurality of trenches 730 in the first trench array 720A are arranged side by side along a first direction A1, a plurality of trenches 730 in the second trench array 720B are arranged side by side along a second direction A2, and a plurality of trenches 730 in the third trench array 720C are arranged side by side along a third direction A3. Any two of the first direction A1, the second direction A2, and the third direction A3 intersect but are not perpendicular.

[0079] Or in other embodiments, such as Figure 9 As shown, the cell region 711 may also include four trench arrays 720, namely a first trench array 720A, a second trench array 720B, a third trench array 720C, and a fourth trench array 720D. The trenches 730 of the first trench array 720A are arranged along a first direction A1, the trenches 730 of the second trench array 720B are arranged along a second direction A2, the trenches 730 of the third trench array 720C are arranged along a third direction A3, and the trenches 730 of the fourth trench array 720D are arranged along a fourth direction. Any two of the first direction A1, the second direction A2, the third direction A3, and the fourth direction A4 intersect but are not perpendicular.

[0080] like Figure 6 As shown, multiple trenches 730 in the three trench arrays 720 are arranged along the first direction A1, the second direction A2, and the third direction A3, respectively. Only one trench array 720 is provided in each direction, and multiple trenches 730 in multiple trench arrays 720 are not arranged in the same direction. After the dielectric material is deposited in the trenches 730, stress will be formed in the first direction A1, the second direction A2, and the third direction A3. That is to say, the stress on the substrate 710 is mainly distributed in these three directions. At this time, the stress distribution pattern of the substrate 710 is similar to a "trident" structure. The total stress on the substrate 710 does not change, so the total stress on the substrate 710 will be evenly distributed in these three directions. Therefore, compared with the stress of the substrate 800 in the conventional technology, which is mainly concentrated in one direction, the trench design provided in this application can distribute the stress on the substrate 710 in multiple directions, thereby reducing the stress on the substrate 710 in a single direction, thus reducing the average stress on the substrate 710, and thus forming better stress dispersion characteristics.

[0081] Therefore, by distributing the stress on the substrate 710 in multiple directions, with each direction corresponding to a trench array 720, the stress distribution on the substrate 710 can be improved, reducing warpage and / or cracking of the substrate 710, increasing its reliability, and thus improving the reliability of the capacitor 700. Furthermore, during the semiconductor manufacturing process of the capacitor 700, this stress dispersion characteristic will not cause wafer warpage or cracking, improving product yield. Additionally, when a high-dielectric-constant dielectric material is deposited within the trench 730, the stress introduced by the dielectric material is less than the upper limit of the stress that the silicon pillar can withstand, allowing the capacitor 700 to have a higher capacitance value by using a high-dielectric-constant dielectric material. Moreover, it also improves process compatibility, enabling the use of processes that are not available in conventional technologies, allowing the deposition of high-dielectric-constant dielectric materials within the trench 730 without dielectric material breakage. Finally, the substrate 710 has low stress in a single direction, the dielectric material will not separate from the substrate 710 and / or the silicon pillar will not crack, the performance of the capacitor 700 will not be reduced or the capacitor 700 will not fail, thus improving the long-term reliability of the capacitor 700.

[0082] In some possible implementations, the included angle between the arrangement directions of multiple trenches 730 of two adjacent trench arrays 720 in the cell region 711 can be 360° / N, where N is the number of trench arrays 720, for example... Figure 6 As shown, there are three trench arrays 720. The arrangement direction of the trenches 730 in the first trench array 720A is the first direction A1, and the arrangement direction of the trenches 730 in the second trench array 720B is the second direction A2. The angle between the first direction A1 and the second direction A2 is 120°. Therefore, the angle between the arrangement directions of the trenches 730 in two adjacent trench arrays 720 is the same, and the arrangement direction of the trenches 730 in the multiple trench arrays 720 is uniformly distributed, resulting in uniform deformation of the substrate 710 and further improving stress distribution.

[0083] It should be noted that the arrangement direction of the multiple trenches 730 in the multiple trench arrays 720 can be non-uniform, in addition to being uniformly distributed. For example... Figure 9 As shown, the trenches 730 of the first trench array 720A are arranged along the first direction A1, the trenches 730 of the second trench array 720B are arranged along the second direction A2, the trenches 730 of the third trench array 720C are arranged along the third direction A3, and the trenches 730 of the fourth trench array 720D are arranged along the fourth direction A4. At this time, the angle between the first direction A1 and the second direction A2 is 90°, the angle between the second direction A2 and the third direction A3 is 45°, the angle between the third direction A3 and the fourth direction A4 is 90°, and the angle between the fourth direction A4 and the first direction A1 is 45°.

[0084] Figure 10 This is a top view schematic diagram of another substrate provided in an embodiment of this application. Figure 11 for Figure 10 A schematic diagram of the large-scale development within the dashed box.

[0085] In some possible implementations, at least two trench arrays 720 in the cell region 711 have the same number of trenches 730, for example... Figure 6 As shown, each of the three trench arrays 720 includes seven trenches 730, and the number of trenches 730 in the three trench arrays 720 is the same. The number of trenches 730 in all trench arrays 720 in the cell region 711 is the same.

[0086] Of course, the number of trenches 730 in the trench array 720 within the cell region 711 can be partially the same, for example... Figure 11 As shown, the cell region 711 includes three trench arrays 720, two of which each include five trenches 730, and the remaining trench array 720 includes nine trenches 730.

[0087] In some possible implementations, at least two trenches 730 of at least one trench array 720 in the cell region 711 have the same length, for example... Figure 6 As shown, the cell region 711 includes three trench arrays 720, and any two trenches 730 in each trench array 720 have the same length. However, the number of trench arrays 720 with the same trench length can also be part of a plurality of trench arrays 720 in the cell region 711.

[0088] In summary, by controlling the arrangement of the multiple trench arrays 720 in the cell region 711, the number of trenches 730 in the trench array 720, and the length of the multiple trenches 730 in the trench array 720, the stress on the substrate 710 in a single direction can be further reduced, the stress distribution on the substrate 710 can be further improved, and this helps to increase the capacitance density of the capacitor 700. Here, capacitance density refers to the capacitance that the capacitor 700 can provide per unit area.

[0089] In some possible implementations, the cell region 711 is polygonal in shape, and the number of sides of the cell region 711 is 2N, where N is the number of trench arrays 720.

[0090] In some embodiments, the shape of the cell region 711 can be a regular polygon, for example, the shape of the cell region 711 can be a regular hexagon (e.g., Figure 6 As shown), a regular octagon (such as...) Figure 9 (as shown). In other embodiments, the shape of the cell region 711 may not be a regular polygon, for example... Figure 11 As shown, the shape of cell region 711 can be a non-regular hexagon.

[0091] See also Figure 6 As shown, when the cell region 711 is a regular hexagon, the cell region 711 can include three parallelogram sub-regions, and each sub-region has a groove array 720 inside. In this way, the multiple grooves 730 of each groove array 720 have the same length.

[0092] Figure 12 This is a top view schematic diagram of another substrate provided in an embodiment of this application. Figure 13 for Figure 12 Enlarged schematic diagram within the dashed box.

[0093] In some other possible implementations, the cell region 711 can also be quadrilateral, for example... Figure 12 As shown, the shape of cell region 711 can be a square. Of course, in addition to a square, the shape of cell region 711 can also be a quadrilateral of other shapes, such as a rhombus.

[0094] In summary, the shape of the cell region 711 as a polygon or quadrilateral with 2N sides can improve the area utilization of the substrate 710, increase the number of cell regions 711, and help to further improve the capacitance density of the capacitor 700.

[0095] It should be noted that the shape of the cell region 711 is not limited to the types described above, and can also be other shapes. Furthermore, the arrangement and number of the multiple trench arrays 720 within the cell region 711 are not limited to the types described above, and can also be other arrangements and numbers. In addition, besides being quadrilaterals or 2N-sided polygons, the shape of the cell region 711 can also be a polygon such as a triangular or M-sided polygon, where M = 2N-1.

[0096] Furthermore, the capacitor 700 provided in this application embodiment can be manufactured using any process in the prior art, and no specific limitations are imposed here. The following example illustrates the fabrication method of the capacitor 700.

[0097] Figure 14 This is a schematic diagram of the first fabrication process of a capacitor provided in an embodiment of this application. Figure 15 This is a schematic diagram of the second fabrication process of the capacitor provided in an embodiment of this application.

[0098] This application also provides a method for manufacturing a capacitor 700, which may include the following steps:

[0099] S01, Multiple trenches 730 are formed in an array on the wafer.

[0100] Specifically, according to Figure 5 The trench design serves as a photoresist mask, allowing the photoresist mask (such as...) to be placed... Figure 14 The photoresist on the substrate 710 (as shown in G in B1) is coated onto the surface of the wafer. A stepper lithography machine is used for exposure and development to form a patterned or arrayed patterned structure from the photoresist on the substrate 710 surface. Then, a deep etching machine is used to etch the substrate, forming trenches 730 as shown in the figure on the wafer surface, resulting in... Figure 14 The structure shown in B1. Finally, the photoresist on the wafer surface is removed using an organic solvent or a dry stripping device.

[0101] The trench 730 can be 400 nm long and approximately 7-10 μm deep. Of course, the length and depth of the trench 730 can also be other dimensions, and no specific restrictions are imposed here.

[0102] It should be noted that, in addition to providing... Figure 5 In addition, it can also be other designs, such as Figure 10 or Figure 12 The groove design is shown.

[0103] S02, forming electrode layer 750 and dielectric layer 740.

[0104] Specifically, a dielectric material is deposited inside the trench 730 through a deposition process to form a dielectric layer 740, such as aluminum oxide, silicon dioxide, or silicon nitride. Specifically, a chemical vapor deposition (CVD) device, such as an ALD or PCVD thin film deposition device, can be used to deposit the dielectric material inside the trench 730. Electrode materials can be deposited using ALD, magnetron sputtering, or reactive magnetron sputtering equipment to form an electrode layer 750.

[0105] In some embodiments, when the number of dielectric layer 740 and electrode layer 750 is one, the dielectric layer 740 is first formed on the inner wall of trench 730 and the surface of wafer, and then the electrode layer 750 is formed on the surface of dielectric layer 740 facing away from wafer, so that a capacitor structure including substrate 710-dielectric layer 740-electrode layer 750 is formed between electrode layer 750 and substrate 710.

[0106] Alternatively, in some embodiments, when both the dielectric layer 740 and the electrode layer 750 are multiple layers, the dielectric layer 740 is first formed on the inner wall of the trench 730 and the surface of the wafer, and then the electrode layer 750 is formed on the surface of the dielectric layer 740 facing away from the wafer. Then, the dielectric layer 740 and the electrode layer 750 are formed cyclically in the order of dielectric layer 740 followed by electrode layer 750, so that a capacitor structure of substrate 710-dielectric layer 740-electrode layer 750 is formed between the electrode layer 750 and the substrate 710 for n cycles. For example... Figure 14 As shown in B2, there are three dielectric layers 740 and three electrode layers 750, which can form three cycles.

[0107] S03, forming a doped polycrystalline silicon layer 760.

[0108] Specifically, an LPCVD device can be used to deposit doped polysilicon on the surface of the structure obtained in step S02 until the trenches 730 are completely filled, forming a pore-free structure in the trenches 730 and their surrounding area. High-temperature annealing is then used to activate the doping properties of the polysilicon, resulting in... Figure 14 The structure shown in B2.

[0109] S04, exposing electrode layer 750 and substrate 710.

[0110] Specifically, a pre-designed pattern can be used as a photoresist mask. This photoresist mask is coated onto the wafer, and then exposed and developed using a photolithography machine such as a contact lithography machine or a stepper lithography machine to form a patterned or arrayed patterned structure from the photoresist on the wafer surface. Following this, methods such as dry etching or wet etching are used to remove the doped polysilicon layer 760 in specific areas of the wafer surface until the electrode layer 750 is exposed, resulting in... Figure 14 The structure shown in B4. When there are multiple electrode layers 750, the electrode layers 750 can be exposed in different regions.

[0111] Similarly, a pre-designed pattern can be used as a photoresist mask. This photoresist mask is coated onto the wafer, and then exposed and developed using a lithography machine such as a contact lithography machine or a stepper lithography machine to form a patterned or arrayed patterned structure from the photoresist on the wafer surface. However, using methods such as dry etching or wet etching, the dielectric layer 740 in specific areas of the surface is removed until the substrate 710 is exposed, resulting in... Figure 14 The structure shown in B4.

[0112] S04, forming a passivation layer 770.

[0113] Specifically, a passivation layer 770, with a thickness on the order of hundreds of micrometers, can be grown on the wafer surface using LPCVD or PECVD chemical vapor deposition equipment for insulation and isolation. Then, using a pre-designed pattern as a photoresist mask, the photoresist mask is coated onto the wafer. The photoresist on the wafer surface is then patterned or arrayed using a photolithography machine such as a contact lithography machine or a stepper lithography machine. Finally, the passivation layer 770 in specific areas of the surface is removed using dry etching or wet etching methods until the polysilicon, electrode layer 750, and substrate 710 are exposed, yielding the desired product. Figure 14 The structure shown in B5.

[0114] S05, Forming a metal interconnect layer 780.

[0115] Specifically, in step S04, metal is deposited on the wafer surface of the structure obtained. A photoresist mask is applied to the wafer, and a patterned or arrayed patterned structure is formed at the source and drain electrodes through exposure and development. Metal etching is then performed on the wafer surface using appropriate equipment to form a metal interconnect layer 780. This allows the individual cells on the wafer to be interconnected, resulting in... Figure 14 The structure shown in B6. Here, a cell can be understood as the structure where capacitor 700 is located within cell region 711.

[0116] S06. Prepare a metal electrode that is electrically connected to the metal interconnect layer 780.

[0117] Specifically, metal electrodes can be fabricated according to the corresponding patterning scheme.

[0118] S07. The wafer is cut to obtain multiple capacitors 700.

[0119] Specifically, a laser stealth dicing device can be used to cut the wafer into multiple capacitors 700.

[0120] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0121] The devices or elements referred to in the embodiments of this application or implied herein must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of this application. In the description of the embodiments of this application, "a plurality of" means two or more, unless otherwise precisely specified.

[0122] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the present application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0123] The term "multiple" in this article refers to two or more. The term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Furthermore, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects; in formulas, the character " / " indicates a "division" relationship between the preceding and following related objects.

[0124] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0125] It is understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

Claims

1. A capacitor (700) characterized by, The capacitor (700) comprises a substrate (710), a surface of the substrate (710) has a plurality of cell regions (711) arranged in an array, each of the cell regions (711) comprises at least three groove arrays (720), each of the groove arrays (720) comprises a plurality of grooves (730) arranged side by side, and the arrangement directions of the plurality of grooves (730) of any two groove arrays (720) intersect and do not coincide.

2. The capacitor (700) according to claim 1, characterized in that An included angle between the arrangement directions of the plurality of grooves (730) of any two adjacent groove arrays (720) in the cell region (711) is 360° / N, and the N is the number of the groove arrays (720).

3. The capacitor (700) according to claim 1 or 2, characterized in that The number of the grooves (730) of at least two groove arrays (720) in the cell region (711) is the same.

4. The capacitor (700) according to any one of claims 1 to 3, characterized in that The lengths of at least two grooves (730) of at least one groove array (720) in the cell region (711) are the same.

5. The capacitor (700) according to any one of claims 1 to 4, characterized in that The cell region (711) is polygonal, and the number of sides of the cell region (711) is 2N, and the N is the number of the groove arrays (720).

6. The capacitor (700) according to claim 5, characterized in that The cell region (711) is regular polygonal.

7. The capacitor (700) according to any one of claims 1 to 4, characterized in that The cell region (711) is quadrilateral.

8. The capacitor (700) according to claim 7, characterized by The cell region (711) is square.

9. The capacitor (700) according to any one of claims 1 to 8, characterized in that The capacitor (700) further comprises a dielectric layer (740) and an electrode layer (750), the dielectric layer (740) covers the inner walls of the grooves (730) and the surface of the substrate (710), and the electrode layer (750) covers the surface of the dielectric layer (740).

10. The capacitor (700) according to any one of claims 1 to 8, characterized in that The capacitor (700) further comprises a dielectric group and an electrode group, the dielectric group comprises a plurality of dielectric layers (740) arranged along the thickness direction of the substrate (710), the electrode group comprises a plurality of electrode layers (750) arranged along the thickness direction of the substrate (710), the dielectric layers (740) and the electrode layers (750) are arranged alternately, the dielectric layer (740) closest to the substrate (710) in the dielectric group is located between the substrate (710) and the electrode layer (750) closest to the substrate (710) in the electrode group, and the dielectric layer (740) closest to the substrate (710) in the dielectric group covers the surface of the substrate (710) and the inner walls of the grooves (730).

11. The capacitor (700) according to any one of claims 1 to 10, characterized in that The capacitor (700) is a silicon capacitor (700), and the material of the substrate (710) comprises a silicon material.

12. A circuit board assembly (500), characterized by The capacitor (700) is connected to the circuit board (600).

13. A chip, characterized by The capacitor (700) is connected to the circuit board (600).

14. An electronic device, comprising: The capacitor (700) is connected to the circuit board (600).

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