Test circuit and circuit test method

Abstract

The invention provides a test circuit and a circuit test method, the test circuit and the circuit test method are applied to a to-be-tested circuit, the to-be-tested circuit comprises a pseudo-random vector generator and K scan chains, the test circuit comprises a random constant generator, a low power consumption controller and a first multiplexer, and the random constant generator is used for generating a first test vector; the low-power-consumption controller is used for generating a low-power-consumption control signal, and the low-power-consumption control signal is used for setting each scanning chain as a low-power-consumption scanning chain or a non-low-power-consumption scanning chain according to the correlation degree between each scanning chain in the K scanning chains and a fault in the circuit to be tested; the first multiplexer is used for inputting a first test vector for the first scan chain under the condition that the first scan chain is a low-power-consumption scan chain, or inputting a second test vector for the first scan chain under the condition that the first scan chain is a non-low-power-consumption scan chain, and the second test vector is a random binary sequence. The test circuit provided by the invention can reduce the power consumption of circuit test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a test circuit and a circuit test method. BACKGROUND

[0002] A complementary metal oxide semiconductor (CMOS) circuit is a widely used digital logic circuit technology, which is composed of N-type and P-type metal oxide semiconductor field effect transistors (MOSFETs). In an ideal case, the static power consumption of a CMOS circuit is very low, but when the logic value changes, the power consumption of the CMOS circuit will increase, and if the frequency of the logic value changes increases, the power consumption will also increase.

[0003] When testing a circuit, the logic value in the scan cell needs to be changed constantly to locate the position of the fault, and the power consumption of the circuit also increases. SUMMARY

[0004] The present application provides a test circuit and a circuit test method, which can reduce the power consumption of circuit testing.

[0005] In a first aspect, a test circuit is provided, which is applied to a to-be-tested circuit, the to-be-tested circuit comprising a pseudo random pattern generator (PRPG) and K scan chains, the test circuit being connected with the PRPG and the K scan chains, K>1, the test circuit comprising: a random constant generator configured to generate a first test vector, a number of consecutive 0s or a number of consecutive 1s in the first test vector accounting for more than a preset threshold in the first test vector; a low-power consumption controller connected with the PRPG and configured to generate a low-power consumption control signal, the low-power consumption control signal being used to set each scan chain in the K scan chains to a low-power consumption scan chain or a non-low-power consumption scan chain according to an association degree of the each scan chain with a fault in the to-be-tested circuit; and a first multiplexer connected with the random constant generator, the low-power consumption controller and the K scan chains, and configured to input the first test vector to a first scan chain in a case where the first scan chain is a low-power consumption scan chain, or input a second test vector to the first scan chain in a case where the first scan chain is a non-low-power consumption scan chain, the first scan chain being any one of the K scan chains, and the second test vector being a random binary sequence.

[0006] The application provides a test circuit, which can set each scan chain as a low-power scan chain or a non-low-power scan chain according to the relevance of the scan chain and a fault in a to-be-tested circuit, so as to reduce the power consumption of circuit test and improve the fault coverage of the circuit.

[0007] In some possible implementation manners, the first test vector can be all 0 or all 1, or the proportion of the number of continuous 0 or the number of continuous 1 in the first test vector is high. Exemplarily, the first test vector can be “0000000000”, “1111111111”, “0000000001111111111111111”, “11111111111111011” and the like, and the preset threshold can be 50%.

[0008] In some possible implementation manners, the higher the relevance of the scan chain and the fault in the to-be-tested circuit, the higher the probability that the scan chain is set as the non-low-power scan chain; or the lower the relevance of the scan chain and the fault in the to-be-tested circuit, the higher the probability that the scan chain is set as the low-power scan chain; or the higher the relevance of the scan chain and the fault in the to-be-tested circuit, the lower the probability that the scan chain is set as the low-power scan chain; or the lower the relevance of the scan chain and the fault in the to-be-tested circuit, the lower the probability that the scan chain is set as the non-low-power scan chain.

[0009] In some possible implementation manners, the first multiplexer can be connected with the PRPG, and the second test vector can be provided by the PRPG to the first multiplexer.

[0010] With reference to the first aspect, in some implementation manners of the first aspect, the test circuit further includes a phase shifter connected with the first multiplexer and configured to generate the second test vector.

[0011] In some possible implementation manners, the first multiplexer can be connected with the phase shifter, and the second test vector can be provided by the phase shifter to the first multiplexer.

[0012] The application provides a test circuit, which can input a second test vector provided by a phase shifter into a scan chain in a case where the scan chain is a non-low-power scan chain. The phase shifter can drive more scan chains and reduce the linear correlation between the scan chains.

[0013] In some possible implementation manners of the first aspect, the low-power controller comprises at least K output ports, the at least K output ports are connected to the first multiplexer, K output ports of the at least K output ports correspond to the K scan chains one by one, and logic values output by the K output ports belong to the low-power control signals, wherein a first output port corresponds to the first scan chain, the first output port is one of the K output ports, and in a case where a logic value output by the first output port is a first value, the first scan chain is a non-low-power scan chain, or in a case where the logic value output by the first output port is a second value, the first scan chain is a low-power scan chain, the first value is 0 and the second value is 1, or the first value is 1 and the second value is 0.

[0014] Exemplarily, a kth output port corresponds to a kth scan chain, 1≤k≤K. In a case where the kth output port outputs a first value, the kth scan chain is a non-low-power scan chain; in a case where the kth output port outputs a second value, the kth scan chain is a low-power scan chain.

[0015] In some possible application scenarios, the first output port outputs 1, and the first scan chain is a non-low-power scan chain; the first output port outputs 0, and the first scan chain is a low-power scan chain.

[0016] The application provides a test circuit, output ports and scan chains correspond to each other, and a scan chain can be set to be a low-power scan chain or a non-low-power scan chain by an output value of an output port according to an association degree of the scan chain and a fault in a to-be-tested circuit, so that the circuit fault coverage can be improved while reducing the circuit test power consumption.

[0017] In some possible implementation manners of the first aspect, the low-power controller further comprises a first register and a plurality of activation circuits, at least part of the plurality of activation circuits are connected to the pseudo-random vector generator, the plurality of activation circuits are connected to the K output ports through the first register, the first register is used to store logic values output by the plurality of activation circuits and remains unchanged in a preset period, each of the K output ports corresponds to at least one activation circuit, and a first activation circuit is used to control a probability of outputting the first value by the first output port through the first register, the first activation circuit is an activation circuit corresponding to the first output port.

[0018] In some possible application scenarios, the activation circuit can be an output line connected with the PRPG, a combinational logic circuit, or a fixed logic value outputter. The output line connected with the PRPG outputs the first value with a probability of 50%, and the fixed logic value outputter is used to fix the output of 0 or 1. Exemplarily, the first activation circuit is a combinational logic circuit, which can be a multi-input AND gate, each input of the multi-input AND gate being provided by the PRPG. In the case of two inputs of the AND gate, the probability of the first activation circuit outputting the first value can be 0.5*0.5=0.25; in the case of three inputs of the AND gate, the probability of the first activation circuit outputting the first value can be 0.5*0.5*0.5=0.125.

[0019] It should be understood that the plurality of activation circuits can be connected with the K output ports through one first register or through a plurality of first registers, which is not limited in the present application.

[0020] Exemplarily, in the case where the first output port corresponds to one first activation circuit, the probability of the first output port outputting the first value is equal to the probability of the first activation circuit outputting the first value, and the logic value output by the first output port is the logic value output by the first activation circuit. In the case where the first output port corresponds to two first activation circuits, the probability of the first output port outputting the first value can be equal to the product of the probabilities of the two first activation circuits outputting the first value, and the logic value output by the first output port is the product of the logic values output by the two first activation circuits.

[0021] The present application provides a test circuit provided with a plurality of activation circuits to control the probability of an output port outputting a first value, which can set a scan chain as a low-power-consumption scan chain or a non-low-power-consumption scan chain according to the relevance of the scan chain to a fault in a circuit to be tested, thereby reducing the power consumption of circuit testing and improving the coverage of circuit faults.

[0022] In combination with the first aspect, in some implementations of the first aspect, the low-power-consumption controller further includes an activation circuit selector and a second multiplexer, the second multiplexer being connected with the activation circuit selector and the plurality of activation circuits, the activation circuit selector outputting a plurality of selection values corresponding to the plurality of activation circuits one by one, and the second multiplexer being configured to output the logic value output by the first activation circuit according to a first selection value output by the activation circuit selector, the first selection value being one of the plurality of selection values and corresponding to the first activation circuit.

[0023] Each of the plurality of activation circuits corresponds to an activation rate, and the activation rate is used to represent a probability that the scan chain is set as a non-low power consumption scan chain. The plurality of selection values output by the activation circuit selector correspond to the plurality of activation circuits one by one, that is, the plurality of selection values output by the activation circuit selector correspond to the plurality of activation rates one by one.

[0024] Exemplarily, the low power consumption controller includes three activation circuits, the selection value 00 corresponds to the first activation circuit and the first activation rate, the selection value 01 corresponds to the second activation circuit and the second activation rate, and the selection value 10 corresponds to the third activation circuit and the third activation rate. When the first selection value is 00, the second multiplexer outputs the logic value output by the first activation circuit, and the probability that the logic value output by the first activation circuit is the first value is equal to the first activation rate.

[0025] In some possible implementation manners, the activation circuit selector can be implemented by at least one shift register, or the activation circuit selector can be implemented by at least one shift register and a shift controller. The shift register is used to output the selection value or part of the logic value in the selection value, and the shift controller is used to control the logic value output by the shift register and the output time.

[0026] The application provides a test circuit, which is provided with an activation circuit selector, and the probability that a scan chain is set as a non-low power consumption scan chain can be controlled by a selection value output by the activation circuit selector. The test circuit can be multiplexed in a plurality of different to-be-tested circuits, and has strong generalization ability.

[0027] With reference to the first aspect, in some implementation manners of the first aspect, the first register includes a second register and a third register, the first value output by the first output port is a result of an AND operation of a third value output by the second register and a fourth value output by the third register, and the probability that the first output port outputs the first value is equal to a probability that the second register outputs the third value multiplied by a probability that the third register outputs the fourth value.

[0028] Exemplarily, the third value is 1, the fourth value is 0, and the first value is 0. The probability that the second register outputs the third value is 0.5, the probability that the third register outputs the fourth value is 1, and the probability that the first output port outputs the first value is equal to 0.5.

[0029] The application provides a test circuit, which can adopt a two-dimensional structure to arrange output ports, so that the area overhead of the test circuit is reduced.

[0030] With reference to the first aspect, in some implementation manners of the first aspect, the first fault correlation degree is proportional to the probability that the first scan chain is a non-low power consumption scan chain, and the first fault correlation degree is a correlation degree between the first scan chain and a fault in the to-be-tested circuit.

[0031] The higher the first fault correlation degree is, the higher the probability that the first scan chain is set as a non-low-power-consumption scan chain is.

[0032] The application provides a test circuit, which can set each scan chain as a low-power-consumption scan chain or a non-low-power-consumption scan chain according to the correlation degree of the scan chain and a fault in a to-be-tested circuit, so as to reduce the power consumption of circuit testing and improve the fault coverage of the circuit.

[0033] With reference to the first aspect, in some implementations of the first aspect, the correlation degree of the first scan chain and the fault in the to-be-tested circuit includes the number of times that the first scan chain is determined to be related to the fault in the to-be-tested circuit.

[0034] The higher the first fault correlation degree is, the higher the probability that the first scan chain is set as a non-low-power-consumption scan chain is.

[0035] In some possible application scenarios, a weight can be set for each scan chain, and the correlation degree of the first scan chain and the fault in the to-be-tested circuit includes the weight of the first scan chain. The higher the weight of the first scan chain is, the higher the first fault correlation degree is, and the higher the probability that the first scan chain is set as a non-low-power-consumption scan chain is.

[0036] The application provides a test circuit, which can set each scan chain as a low-power-consumption scan chain or a non-low-power-consumption scan chain according to the correlation degree of the scan chain and a fault in a to-be-tested circuit, so as to reduce the power consumption of circuit testing and improve the fault coverage of the circuit.

[0037] With reference to the first aspect, in some implementations of the first aspect, the correlation degree of the first scan chain and the fault in the to-be-tested circuit is obtained by analyzing circuit fault information, and the circuit fault information includes a result obtained by testing or analyzing the to-be-tested circuit by using a test vector of logic built-in self test (LBIST) or a test vector of automatic-test-pattern-generation (ATPG).

[0038] The application provides a test circuit, which obtains circuit fault information in a test environment of LBIST or ATPG, and ensures the accuracy of the correlation degree of the scan chain and the fault.

[0039] In conjunction with the first aspect, in some implementations of the first aspect, the K scan chains correspond to n scan chain groups, the n scan chain groups correspond one-to-one with n preset activation rates, and the i-th activation rate among the n preset activation rates is used to represent the probability that all scan chains in the i-th scan chain group are set as non-low-power scan chains, 1≤i≤n, 1<n≤K.

[0040] For example, the circuit under test has 10 scan chains C1 to C10. Scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2 to C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9 to C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0041] This application provides a test circuit that can set the activation rate for each scan chain in groups, thereby improving the efficiency of activation rate setting.

[0042] In conjunction with the first aspect, in some implementations of the first aspect, the correlation between the scan chain in the i-th scan chain group and the fault in the circuit under test is greater than the correlation between the scan chain in the j-th scan chain group and the fault in the circuit under test, the i-th activation rate is greater than the j-th activation rate, 1≤j≤n, and i≠j.

[0043] The higher the correlation between the scan chain in the scan chain group and the fault in the circuit under test, the greater the activation rate of the scan chain group.

[0044] For example, the circuit under test has 10 scan chains C1 to C10. These 10 scan chains are ordered from highest to lowest correlation with the fault in the circuit under test as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 groups, corresponding to preset activation rates P1 of 1, P2 of 0.5, and P3 of 0.25. The first scan chain group includes scan chain C1 with an activation rate of 1; the second scan chain group includes scan chains C2 to C8 with an activation rate of 0.5; and the third scan chain group includes scan chains C9 to C10 with an activation rate of 0.25.

[0045] This application provides a test circuit that can set each scan chain as a low-power scan chain or a non-low-power scan chain according to the correlation between the scan chain and the faults in the circuit under test, thereby reducing the power consumption of circuit testing and improving the coverage of circuit faults.

[0046] In conjunction with the first aspect, in some implementations of the first aspect, D1+D2+…+D n =1 and D1×P1+D2×P2+…+D n ×P n = P×2, where, D iEquals the number of scan chains in the i-th scan chain group divided by K, P i P is the activation rate corresponding to the i-th scan chain group, and P is the preset flip rate.

[0047] The K scan chains are allocated according to the following ratios: D1, D2, ..., D... n The circuit is assigned to n groups. Specifically, scan chains with a D1 ratio in the circuit under test are assigned to group 1, with an activation rate of P1; scan chains with a D2 ratio in the circuit under test are assigned to group 2, with an activation rate of P2; and scan chains with a D1 ratio in the circuit under test are assigned to group 3. n The proportional scan chain is assigned to the nth group, with a corresponding activation rate of P. n .

[0048] For example, the circuit under test has 10 scan chains C1 to C10. These 10 scan chains are ordered from highest to lowest correlation with the fault in the circuit under test as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 groups, with preset activation rates P1 = 1, P2 = 0.5, and P3 = 0.25. The preset expected toggle rate P is 0.25. The formula D1 + D2 + ... + D... n =1 and the formula D1×P1+D2×P2+…+D n ×P n The calculation of P×2 yields allocation ratios D1 of 0.1, D2 of 0.7, and D3 of 0.2. This means that one scan chain has an activation rate of 1, seven scan chains have an activation rate of 0.5, and two scan chains have an activation rate of 0.25. Scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2-C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9-C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0049] This application provides a test circuit that can set the activation rate for each scan chain in groups, thereby improving the efficiency of activation rate setting.

[0050] Secondly, a circuit testing method is provided, applied to a circuit under test, the circuit under test including K scan chains, K>1, the method including: acquiring circuit fault information in the circuit under test; determining the correlation degree between each scan chain in the K scan chains and the fault in the circuit under test based on the circuit fault information; determining the probability that a first scan chain is a low-power scan chain or a non-low-power scan chain based on a first fault correlation degree, the first fault correlation degree being the correlation degree between the first scan chain and the fault in the circuit under test, the first scan chain being any one of the K scan chains, the first fault correlation degree being proportional to the probability that the first scan chain is a non-low-power scan chain, the probability of the low-power scan chain or the non-low-power scan chain being used to input a first test vector or a second test vector for the first scan chain, the proportion of the number of consecutive 0s or consecutive 1s in the first test vector being greater than a preset threshold, and the second test vector being a random binary sequence.

[0051] This application provides a circuit testing method that can set each scan chain as a low-power scan chain or a non-low-power scan chain according to the correlation between the scan chain and the faults in the circuit under test, thereby reducing the power consumption of circuit testing and improving the coverage of circuit faults.

[0052] In some possible implementations, the first test vector can be all 0s, all 1s, or have a higher proportion of consecutive 0s or consecutive 1s. For example, the first test vector can be "0000000000", "1111111111", "0000000001111111111111111", "111111111111011", etc., and the preset threshold can be 50%.

[0053] In some possible implementations, the second test vector can be generated by PRPG or by a phase shifter.

[0054] In conjunction with the second aspect, in some implementations of the second aspect, obtaining circuit fault information in the circuit under test includes: using LBIST test vectors or ATPG test vectors to test or analyze the circuit under test to obtain the circuit fault information.

[0055] This application provides a circuit testing method that obtains circuit fault information in a test environment such as LBIST or ATPG, thereby ensuring the accuracy of scan chain and fault correlation.

[0056] In conjunction with the second aspect, in some implementations of the second aspect, the first fault correlation includes the number of times the first scan chain is determined to be associated with a fault in the circuit under test.

[0057] The more times the first scan chain is identified as being related to a fault in the circuit under test, the higher the correlation of the first fault, and the higher the probability that the first scan chain will be set as a non-low-power scan chain.

[0058] In some potential application scenarios, weights can be assigned to each scan chain. The correlation between the first scan chain and the fault in the circuit under test includes the weight of the first scan chain. The more times the first scan chain is determined to be related to the fault in the circuit under test, the higher the weight of the first scan chain, the higher the correlation with the first fault, and the higher the probability that the first scan chain will be set as a non-low-power scan chain.

[0059] This application provides a circuit testing method that can set each scan chain as a low-power scan chain or a non-low-power scan chain according to the correlation between the scan chain and the faults in the circuit under test, thereby reducing the power consumption of circuit testing and improving the coverage of circuit faults.

[0060] In conjunction with the second aspect, in some implementations of the second aspect, the K scan chains correspond to n scan chain groups, the n scan chain groups correspond one-to-one with n preset activation rates, and the i-th activation rate among the n preset activation rates is used to represent the probability that all scan chains in the i-th scan chain group are set as non-low-power scan chains, 1≤i≤n, 1<n≤K.

[0061] For example, the circuit under test has 10 scan chains C1 to C10. Scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2 to C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9 to C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0062] This application provides a circuit testing method that can set the activation rate for each scan chain in groups, thereby improving the efficiency of activation rate setting.

[0063] In conjunction with the second aspect, in some implementations of the second aspect, the correlation between the scan chain in the i-th scan chain group and the fault in the circuit under test is greater than the correlation between the scan chain in the j-th scan chain group and the fault in the circuit under test, the i-th activation rate is greater than the j-th activation rate, 1≤j≤n, and i≠j.

[0064] The higher the correlation between the scan chain in the scan chain group and the fault in the circuit under test, the greater the activation rate of the scan chain group.

[0065] For example, the circuit under test has 10 scan chains C1 to C10. These 10 scan chains are ordered from highest to lowest correlation with the fault in the circuit under test as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 groups, corresponding to preset activation rates P1 of 1, P2 of 0.5, and P3 of 0.25. The first scan chain group includes scan chain C1 with an activation rate of 1; the second scan chain group includes scan chains C2 to C8 with an activation rate of 0.5; and the third scan chain group includes scan chains C9 to C10 with an activation rate of 0.25.

[0066] This application provides a circuit testing method that can set each scan chain as a low-power scan chain or a non-low-power scan chain according to the correlation between the scan chain and the faults in the circuit under test, thereby reducing the power consumption of circuit testing and improving the coverage of circuit faults.

[0067] In conjunction with the second aspect, in some implementations of the second aspect, D1+D2+…+D n =1 and D1×P1+D2×P2+…+D n ×P n = P×2, where, D i Equals the number of scan chains in the i-th scan chain group divided by K, P i P is the activation rate corresponding to the i-th scan chain group, and P is the preset flip rate.

[0068] The K scan chains are allocated according to the following ratios: D1, D2, ..., D... n The circuit is assigned to n groups. Specifically, scan chains with a D1 ratio in the circuit under test are assigned to group 1, with an activation rate of P1; scan chains with a D2 ratio in the circuit under test are assigned to group 2, with an activation rate of P2; and scan chains with a D1 ratio in the circuit under test are assigned to group 3. n The proportional scan chain is assigned to the nth group, with a corresponding activation rate of P. n .

[0069] For example, the circuit under test has 10 scan chains C1 to C10. These 10 scan chains are ordered from highest to lowest correlation with the fault in the circuit under test as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 groups, with preset activation rates P1 = 1, P2 = 0.5, and P3 = 0.25. The preset expected toggle rate P is 0.25. The formula D1 + D2 + ... + D... n =1 and the formula D1×P1+D2×P2+…+D n ×P nThe calculation of P×2 yields allocation ratios D1 of 0.1, D2 of 0.7, and D3 of 0.2. This means that one scan chain has an activation rate of 1, seven scan chains have an activation rate of 0.5, and two scan chains have an activation rate of 0.25. Scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2-C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9-C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0070] This application provides a circuit testing method that can set the activation rate for each scan chain in groups, thereby improving the efficiency of activation rate setting.

[0071] Thirdly, a computer device is provided for use in a circuit under test, the circuit under test including K scan chains, K>1, the device including: an acquisition module for acquiring circuit fault information in the circuit under test; a processing module for determining the correlation degree between each scan chain in the K scan chains and the fault in the circuit under test based on the circuit fault information; the processing module is further configured to determine the probability that a first scan chain is a low-power scan chain or a non-low-power scan chain based on a first fault correlation degree, the first fault correlation degree being the correlation degree between the first scan chain and the fault in the circuit under test, the first scan chain being any one of the K scan chains, the first fault correlation degree being proportional to the probability that the first scan chain is a non-low-power scan chain, the probability of the low-power scan chain or the non-low-power scan chain being used to input a first test vector or a second test vector for the first scan chain, the proportion of the number of consecutive 0s or consecutive 1s in the first test vector being greater than a preset threshold, and the second test vector being a random binary sequence.

[0072] In conjunction with the third aspect, in some implementations of the third aspect, the acquisition module is specifically used to: use the test vectors of LBIST or ATPG to test or analyze the circuit under test to obtain the circuit fault information.

[0073] In conjunction with the third aspect, in some implementations of the third aspect, the first fault correlation includes the number of times the first scan chain is determined to be related to a fault in the circuit under test.

[0074] In conjunction with the third aspect, in some implementations of the third aspect, the K scan chains correspond to n scan chain groups, the n scan chain groups correspond one-to-one with n preset activation rates, and the i-th activation rate among the n preset activation rates is used to represent the probability that all scan chains in the i-th scan chain group are set as non-low-power scan chains, 1≤i≤n, 1<n≤K.

[0075] In conjunction with the third aspect, in some implementations of the third aspect, the correlation between the scan chain in the i-th scan chain group and the fault in the circuit under test is greater than the correlation between the scan chain in the j-th scan chain group and the fault in the circuit under test, the i-th activation rate is greater than the j-th activation rate, 1≤j≤n, and i≠j.

[0076] In conjunction with the third aspect, in some implementations of the third aspect, D1+D2+…+D n =1 and D1×P1+D2×P2+…+D n ×P n = P×2, where, D i Equals the number of scan chains in the i-th scan chain group divided by K, P i P is the activation rate corresponding to the i-th scan chain group, and P is the preset flip rate.

[0077] The beneficial effects of the third aspect and any possible implementation of the third aspect correspond to the beneficial effects of the second aspect and any possible implementation of the second aspect, which will not be elaborated further.

[0078] Fourthly, embodiments of this application provide a circuit including a PRPG, K scan chains, and a test circuit as described in any possible implementation of the first aspect, where K > 1.

[0079] Fifthly, embodiments of this application provide a computer device including a processor configured to be coupled to a memory, read and execute instructions and / or program code in the memory to perform the second aspect or any possible implementation thereof.

[0080] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing program code that, when the computer storage medium is run on a computer, causes the computer to perform the second aspect or any possible implementation thereof.

[0081] In a seventh aspect, embodiments of this application provide a computer program product comprising: computer program code, which, when run on a computer, causes the computer to perform as in the second aspect or any possible implementation thereof. Attached Figure Description

[0082] Figure 1 This is a schematic diagram of a scan chain testing technique provided in an embodiment of this application.

[0083] Figure 2 This is a schematic diagram of a scan chain shifting mode provided in an embodiment of this application.

[0084] Figure 3 This is a schematic diagram of an LBIST circuit provided in an embodiment of this application.

[0085] Figure 4 This is a schematic diagram of a test circuit provided in an embodiment of this application.

[0086] Figure 5 This is a schematic diagram of another test circuit provided in an embodiment of this application.

[0087] Figure 6 This is a schematic diagram of another test circuit provided in an embodiment of this application.

[0088] Figure 7 This is a schematic diagram of another test circuit provided in an embodiment of this application.

[0089] Figure 8 This is an exemplary flowchart of a circuit testing method provided in an embodiment of this application.

[0090] Figure 9 This is an exemplary flowchart of assigning activation rates to a scan chain, provided in an embodiment of this application.

[0091] Figure 10 This is a schematic diagram of a circuit fault analysis provided in an embodiment of this application.

[0092] Figure 11 This is a schematic diagram illustrating the correlation between a scan chain and a circuit fault, provided in an embodiment of this application.

[0093] Figure 12 This is another exemplary flowchart for allocating activation rates to a scan chain, provided in an embodiment of this application.

[0094] Figure 13 This is a schematic diagram illustrating another method for determining the correlation between the scan chain and circuit faults, provided in an embodiment of this application.

[0095] Figure 14 This is a schematic diagram of a low-power controller provided in an embodiment of this application.

[0096] Figure 15 This is a schematic diagram of another low-power controller provided in an embodiment of this application.

[0097] Figure 16 This is a schematic diagram of another low-power controller provided in an embodiment of this application.

[0098] Figure 17 This is a schematic diagram of a random constant generator provided in an embodiment of this application.

[0099] Figure 18 This is a structural example diagram of a computer device provided in an embodiment of this application.

[0100] Figure 19 This is a structural example diagram of another computer device provided in the embodiments of this application.

[0101] Figure 20 This is an example diagram of a computer program product provided in an embodiment of this application. Detailed Implementation

[0102] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0103] In the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0104] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0105] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0106] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0107] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0108] To facilitate understanding of the embodiments of this application, some definitions involved in this application will be briefly explained first.

[0109] 1. Electronic Design Automation (EDA): refers to the design method that uses computer-aided design software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, design rule checking, etc.) of very large-scale integrated circuit chips.

[0110] 2. Automatic Test Pattern Generation (ATPG): ATPG is an important component of the EDA process. Its main function is to generate test vectors for the input sequence in the testing phase of digital circuits, distinguishing between correct circuits and faulty circuits caused by defects. The generated vectors can be used to assist in the production and testing of semiconductor devices, or to help locate the cause of faults.

[0111] 3. Automated Test Equipment (ATE): A specialized piece of equipment used for automated testing and fault diagnosis of electronic devices. It is widely used in electronics manufacturing, semiconductor production, circuit board testing and repair, and other fields. ATEs typically consist of hardware and software and are used to perform various test tasks, such as signal measurement, electrical parameter testing, functional verification, fault diagnosis, and reliability testing. ATEs can perform comprehensive testing and evaluation of electronic devices, integrated circuits, circuit boards, or other electronic components.

[0112] 4. Test pattern: A test pattern is a set of input signals used in the testing of a chip or electronic device to detect the device's functionality, performance, and faults. Test patterns typically consist of a series of logic values, such as 0 and 1. These logic values ​​are applied to the input pins or input interfaces of the device under test according to a specific timing and sequence. The generation of test patterns is based on the test objective and can cover different test requirements, including functional testing, timing testing, boundary testing, and fault mode testing.

[0113] 5. Scan chain: A technique used for testing and fault diagnosis. It is a data path consisting of a series of consecutive registers, forming a circular or linear chain structure within the chip. In scan chain testing, test vectors are loaded into the registers of the scan chain and then passed through the scan chain. This scan chain transmission method can transfer test data between registers throughout the chip and output test response data from the scan chain to the chip's output pins.

[0114] 6. Scan Cell: The basic building block for implementing the scan chain. It is a specially designed register unit used to support chip testing and fault diagnosis. In normal operation mode, the scan cell's inputs and outputs are connected to the various logic function units of the chip to support normal chip functionality. However, in test mode, by capturing the clock control signal, the scan cell can switch input and output connections when transmitting test mode and test response data, guiding the data into the scan chain.

[0115] 7. Capture Clock: A clock signal used to synchronize data capture operations. During data capture, the signal value is captured only at the rising or falling edge of a specific moment and stored in a register. This specific moment is controlled by the "capture clock." When the "capture clock" is triggered, the value of the input signal is read and transferred to the relevant register.

[0116] 8. Logic Built-in Self-Test (LBIST): This is a self-test for logic circuits. When running LBIST, the circuit generates its own test vectors, then tests itself and detects potential faults. The test vectors are generated by an on-chip pseudo random pattern generator (PRPG). The output response is compressed using a multiple input signature register (MISR), and the resulting feature values ​​are compared. The hardware and / or software are built into the integrated circuit, allowing them to test their own operation rather than relying on external automated test equipment.

[0117] 9. Flip Rate: This usually refers to the number of times a signal changes state per unit time, and can also be understood as the signal frequency. In digital circuits or communication systems, the flip rate of a signal refers to the number of times a signal transitions from one state (e.g., high level) to another state (e.g., low level) or vice versa.

[0118] 10. Scan chain activation rate: refers to the probability that the scan chain is set to a non-low-power chain.

[0119] Complementary metal-oxide-semiconductor (CMOS) circuits are a widely used digital logic circuit technology, composed of N-type and P-type metal-oxide-semiconductor field-effect transistors (MOSFETs). Ideally, CMOS circuits have very low static power consumption; however, power consumption increases with changes in logic values, and this increase is further amplified by the frequency of logic value changes. During circuit testing, the logic values ​​in the scanning cells need to be continuously varied to locate the fault, which also increases the circuit's power consumption.

[0120] Figure 1 This is a schematic diagram of a scan chain testing technique provided in an embodiment of this application.

[0121] The circuit includes at least one scan chain, each scan chain comprising multiple consecutive registers. Test vectors are loaded into the registers of the scan chain and then passed through the scan chain. In some possible implementations, these registers may be scan cells.

[0122] Figure 1The rectangular cells in the diagram represent scan cells, which have input ports such as a data (D) port, a scan in (SI) port, and a scan enable (SE) port, and one output port Q. Except for the first and last scan cells, all other scan cells are connected end-to-end via the SI port and the output port Q. Multiple scan cells connected in this way are called a scan chain. The scan chain has two operating modes: shift mode and capture mode, controlled by the SE signal.

[0123] Figure 2 This is a schematic diagram of a scan chain shifting mode provided in an embodiment of this application.

[0124] When the SE signal is 1, the shift mode is enabled. Whenever the clock (CLK) signal changes, the test vector is input from the SI port, and shifted along the scan chain through the connected scan units. The output port Q of the scan unit drives the combinational logic of the corresponding circuit. If the logic value shifted into the scan chain keeps changing, it will cause all scan units on the subsequent scan chain to keep changing during the shift process, ultimately leading to increased circuit power consumption during testing.

[0125] Figure 3 This is a schematic diagram of an LBIST circuit provided in an embodiment of this application.

[0126] The LBIST circuit includes a PRPG, a phase shifter, a scan chain, a low-power controller, a mask controller, and a MISR.

[0127] The PRPG can continuously generate pseudo-random vectors for the LBIST circuit, and the phase shifter allows the PRPG to drive more scan chains. In the diagram, each small square in the scan chain represents a shift register, and multiple small squares are strung together to form a scan chain.

[0128] A low-power controller is used to control a fixed proportion of the scan chain to clamp the values ​​shifted into the scan chain during the entire shift cycle of a test vector, or during a segment of shift cycles. For example, controlling 30% of the scan chain to remain at logic 0 during the entire shift of the test vector into the scan chain allows the combinational logic circuits driven by the scanned units and the scanned units to remain unchanged during partial shifts, thereby reducing the circuit's toggle rate during the shift cycle and achieving the goal of reducing circuit power consumption.

[0129] Mask controllers are typically used to manage masking operations during the LBIST testing process. In LBIST, masks can be used to block out the output values ​​of a portion of the scan chain to exclude them from the self-test process, or to limit the scope of test modes.

[0130] The MISR (Multi-Installation Detector) receives the data stream from the logic under test (DUT), processes, compresses, and transforms this data to generate a fixed-length data signature. This signature can be seen as a "fingerprint" of the DUT's output under a specific test mode, representing the output state under that test mode. By comparing signatures generated under different test modes, the MISR can detect potential faults or inconsistencies. If the signatures of the same logic circuit output under different test modes are inconsistent, it indicates a possible fault.

[0131] Figure 4 This is a schematic diagram of a test circuit provided in an embodiment of this application.

[0132] The circuit under test includes a PRPG and K scan chains. The test circuit 400 is connected to the PRPG and the K scan chains, where K > 1.

[0133] PRPG is used to continuously generate pseudo-random vectors for the circuit. PRPG outputs logic 0 with a 50% probability and logic 1 with a 50% probability.

[0134] The test circuit 400 includes a random constant generator 410, a low-power controller 420, and a first multiplexer 430.

[0135] A random constant generator 410 is used to generate a first test vector, wherein the proportion of consecutive 0s or consecutive 1s in the first test vector is greater than a preset threshold. In some possible implementations, the first test vector can be all 0s, or all 1s, or the proportion of consecutive 0s or consecutive 1s in the first test vector is relatively high. For example, the first test vector can be "0000000000", "1111111111", "0000000001111111111111111", "111111111111011", etc., and the preset threshold can be 50%.

[0136] The low-power controller 420 is connected to the PRPG and is used to generate a low-power control signal. This low-power control signal is used to set each scan chain as a low-power scan chain or a non-low-power scan chain based on the correlation between each scan chain in the K scan chains and the fault in the circuit under test.

[0137] The scan chain can include low-power scan chains and non-low-power scan chains. Low-power scan chains operate in a low-power state during testing, meaning they have a low toggle rate; non-low-power scan chains operate in a non-low-power state during testing, meaning they have a high toggle rate. The higher the proportion of low-power scan chains, the lower the power consumption during circuit testing. The method for generating low-power control signals can be found in the following embodiments.

[0138] In some possible implementations, the higher the correlation between the scan chain and the fault in the circuit under test, the higher the probability that the scan chain will be set as a non-low-power scan chain; or, the lower the correlation between the scan chain and the fault in the circuit under test, the higher the probability that the scan chain will be set as a low-power scan chain; or, the higher the correlation between the scan chain and the fault in the circuit under test, the lower the probability that the scan chain will be set as a low-power scan chain; or, the lower the correlation between the scan chain and the fault in the circuit under test, the lower the probability that the scan chain will be set as a non-low-power scan chain.

[0139] The first multiplexer 430 is connected to the random constant generator 410, the low-power controller 420, and the K scan chains. It is used to input a first test vector for the k-th scan chain when the k-th scan chain is a low-power scan chain, or to input a second test vector for the k-th scan chain when the k-th scan chain is a non-low-power scan chain. The second test vector is a random binary sequence, 1≤k≤K.

[0140] In some possible implementations, such as Figure 5 As shown, the first multiplexer 430 can be connected to the PRPG, and the second test vector can be provided to the first multiplexer 430 by the PRPG.

[0141] In some possible implementations, such as Figure 6 As shown, the first multiplexer 430 can be connected to the phase shifter 440, and the second test vector can be provided by the phase shifter 440 to the first multiplexer 430.

[0142] In some possible implementations, such as Figure 7 As shown, the low-power controller 420 can also be connected to a fixed logic value output 450, which is used to output a logic value that is fixed to 0 or a logic value that is fixed to 1.

[0143] Figure 8 This is an exemplary flowchart of a circuit testing method provided in an embodiment of this application.

[0144] 810, Obtain circuit fault information in the circuit under test.

[0145] This circuit testing method is applied to the circuit under test, which includes K scan chains, where K > 1.

[0146] Circuit fault information includes the results obtained from testing or analyzing the circuit under test using test vectors from logic built-in self test (LBIST) or automatic-test-pattern-generation (ATPG).

[0147] 820, determine the correlation between each scan chain and the fault in the circuit under test.

[0148] The correlation between each of the K scan chains and the fault in the circuit under test is determined based on the circuit fault information. The correlation between the scan chain and the fault in the circuit under test includes the number of times the scan chain is determined to be related to the fault in the circuit under test.

[0149] 830, determine the probability that the first scan chain is a low-power scan chain or a non-low-power scan chain.

[0150] Based on the first fault correlation degree, the probability of the first scan chain being a low-power scan chain or a non-low-power scan chain is determined. The first fault correlation degree is the correlation between the first scan chain and a fault in the circuit under test, and the first scan chain is any one of K scan chains.

[0151] The first fault correlation degree is proportional to the probability that the first scan chain is a non-low-power scan chain. The probability of the low-power scan chain or the non-low-power scan chain is used to input the first test vector or the second test vector for the first scan chain. The proportion of the number of consecutive 0s or consecutive 1s in the first test vector is greater than a preset threshold. The second test vector is a random binary sequence.

[0152] In some possible implementations, the first test vector can be all 0s, all 1s, or have a higher proportion of consecutive 0s or consecutive 1s. For example, the first test vector can be "0000000000", "1111111111", "0000000001111111111111111", "111111111111011", etc., and the preset threshold can be 50%.

[0153] In some possible implementations, the second test vector can be generated by PRPG or by a phase shifter.

[0154] Figure 9 This is an exemplary flowchart of assigning activation rates to a scan chain, provided in an embodiment of this application.

[0155] 910. Use LBIST test vectors to obtain circuit fault information.

[0156] Using LBIST test vectors, the circuit under test is tested without low-power control to obtain captured fault information.

[0157] 920, Analyze circuit fault information.

[0158] Static analysis is performed on the circuit under test based on the circuit fault information. The circuit fault information includes at least one fault point, such as... Figure 10 As shown, firstly, a forward trace is performed on each fault point to find all fault observation cells. Then, a backward trace is performed on each fault observation cell to find the corresponding driving scan unit for each fault observation cell at each fault point. Finally, the driving scan chain is determined based on the identity document (ID) of the driving scan unit. A fault observation cell is a scan unit that can observe the fault caused by the fault point, and a driving scan unit is a scan unit that drives the fault observation cell.

[0159] For example, by tracing fault point 1 forward, fault observation unit 1 and fault observation unit 2 are found. By tracing fault observation unit 1 backward, drive scanning unit 1 is obtained. By tracing fault observation unit 2 backward, drive scanning unit 2 and drive scanning unit 3 are obtained. Since one scanning unit corresponds to only one scanning chain, the ID of drive scanning chain 1 to which drive scanning unit 1 belongs can be obtained from the circuit information. The ID of drive scanning unit 2 to which drive scanning chain 2 belongs can be obtained from the ID of drive scanning unit 1. The ID of drive scanning unit 3 to which drive scanning chain 3 belongs can be obtained from the ID of drive scanning unit 3.

[0160] It should be understood that the above method of first tracing forward and then tracing backward is only an example. It is also possible to directly trace backward to the fault point. The above example should not be construed as a limitation of this application.

[0161] 930, sort the frequency of use of the scan chain.

[0162] Based on the static analysis results of step 920, the scan chains can be sorted from highest to lowest usage frequency. The usage frequency of a scan chain is the number of times it is identified as a driving scan chain, or in other words, the number of times it is determined to be associated with a fault in the circuit under test. It should be understood that the more times a scan chain is identified as a driving scan chain for a fault point, the higher the probability that the scan chain is the cause of the fault.

[0163] For example, such as Figure 11 As shown, F1 to F3 are three different fault points, OC1 to OC5 are the fault observation units corresponding to F1 to F3, and C1 to C6 are the drive scan chains to which the drive scan units corresponding to OC1 to OC5 belong. The correspondence between F1 to F3, OC1 to OC5, and C1 to C6 can be referred to the lines connecting them. Figure 11 It can be seen that scan chain C1 is used once, scan chain C2 is used five times, scan chain C3 is used twice, scan chain C4 is used twice, scan chain C5 is used once, and scan chain C6 is used once. Figure 11 The scan chains shown are sorted by frequency of use from highest to lowest as follows: C2:5, C3:2, C4:2, C1:1, C5:1, C6:1.

[0164] 940, set the n activation rates corresponding to the n scan chains.

[0165] The scan chain in the circuit under test is set to be divided into n scan chain groups, each scan chain group corresponding to a preset activation rate, and the activation rate corresponding to the i-th scan chain group is P. i Let P represent the probability that all scan chains in the i-th group are set as non-low-power scan chains. i The activation rates, ranked from highest to lowest, are P1, P2, ..., P... n .

[0166] For the scan chains in step 930, which are sorted in descending order of frequency of use, according to the allocation ratios D1, D2, ..., D... n The circuit is assigned to n scan chain groups. Specifically, scan chains with a ratio of D1 are assigned to the first scan chain group, with an activation rate of P1; scan chains with a ratio of D2 are assigned to the second scan chain group, with an activation rate of P2; and so on. n A certain proportion of the scan chains are assigned to the nth scan chain group, with a corresponding activation rate of P. n When the circuit under test includes K scan chains, D i It is equal to the number of scan chains in the i-th scan chain group divided by K, 1≤i≤n, 1<n≤K.

[0167] Among them, the allocation ratios are D1, D2, ..., D n And activation rates P1, P2, ..., P n Satisfying constraints (1) and (2), P is the preset expected flip rate.

[0168] D1+D2+…+D n =1 constraint(1)

[0169] D1×P1+D2×P2+…+Dn ×P n =P×2 constraint(2)

[0170] Based on the preset activation rates P1, P2, ..., P n Given the preset P, constraints (1) and constraints (2), the allocation ratios D1, D2, ..., D can be obtained. n .

[0171] For example, the circuit under test has 10 scan chains C1 to C10. The 10 scan chains are ordered from highest to lowest frequency as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 scan chain groups, with preset activation rates P1 of 1, P2 of 0.5, and P3 of 0.25. The preset expected flip rate P is 0.25. After calculation based on constraints (1) and (2), the allocation ratios D1, D2, and D3 are 0.1, 0.7, and 0.2, respectively. That is, one scan chain has an activation rate of 1, seven scan chains have an activation rate of 0.5, and two scan chains have an activation rate of 0.25. The allocation ratios D1, D2, and D3 satisfy 0.1×1 + 0.7×0.5 + 0.2×0.25 = 0.25×2. This means that scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2 to C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9 to C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0172] Figure 12 This is another exemplary flowchart for allocating activation rates to a scan chain, provided in an embodiment of this application.

[0173] 1210. Use ATPG test vectors to obtain circuit fault information.

[0174] Using ATPG test vectors, the circuit under test is analyzed to obtain circuit fault information. This fault information can include test cube information corresponding to each fault point. The test cube information includes the ID of the activated scan unit, which refers to the scan unit that needs to be activated when activating the fault point.

[0175] 1220, Analyze circuit fault information.

[0176] The weight of each scan chain is calculated based on the circuit fault information. Each fault point has a weight of 1, which is equally distributed among each activated scan unit in the corresponding test cube information. The weight of a scan chain is the sum of the weights of all activated scan units on it. For example... Figure 13As shown, fault point F1 distributes its weight equally among active scanning units SC1, SC2, and SC3, while fault point F2 distributes its weight equally among active scanning units SC2 and SC4. The weight of active scanning unit SC1 is 1 / 3, SC2 is 5 / 6, SC3 is 1 / 3, and SC4 is 1 / 2. The weight of scan chain C1 is 1 / 3, scan chain C2 is 7 / 6, and scan chain C3 is 1 / 2.

[0177] 1230, Sort the weights of the scan chain.

[0178] Based on the data analysis results of step 1220, the weights of the scan chains can be sorted from largest to smallest.

[0179] 1240, set the n activation rates corresponding to the n scan chains.

[0180] For the scan chain sorted in descending order of weight in steps 1230, according to the allocation ratios D1, D2, ..., D... n The circuit is assigned to n scan chain groups. Specifically, scan chains with a ratio of D1 are assigned to the first scan chain group, with an activation rate of P1; scan chains with a ratio of D2 are assigned to the second scan chain group, with an activation rate of P2; and so on. n A certain proportion of the scan chains are assigned to the nth scan chain group, with a corresponding activation rate of P. n When the circuit under test includes K scan chains, D i It is equal to the number of scan chains in the i-th scan chain group divided by K, 1≤i≤n, 1<n≤K.

[0181] Among them, the allocation ratios are D1, D2, ..., D n And activation rates P1, P2, ..., P n It satisfies constraints (1) and (2).

[0182] Based on the preset activation rates P1, P2, ..., P n Given the preset P, constraints (1) and constraints (2), the allocation ratios D1, D2, ..., D can be obtained. n .

[0183] For example, the circuit under test has 10 scan chains C1 to C10. The 10 scan chains are sorted in descending order of weight as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 scan chain groups, with preset activation rates P1 of 1, P2 of 0.5, and P3 of 0.25. The preset expected flip rate P is 0.25. After calculation based on constraints (1) and (2), the allocation ratios D1, D2, and D3 are 0.1, 0.7, and 0.2, respectively. That is, one scan chain has an activation rate of 1, seven scan chains have an activation rate of 0.5, and two scan chains have an activation rate of 0.25. The allocation ratios D1, D2, and D3 satisfy 0.1×1 + 0.7×0.5 + 0.2×0.25 = 0.25×2. This means that scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2 to C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9 to C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0184] Figure 14 This is a schematic diagram of a low-power controller provided in an embodiment of this application.

[0185] The low-power controller 420 may include K activation circuits 421, a first register 422, and K output ports Q1 to Q2. K K output ports Q1~Q K It is connected to the first multiplexer 430. K activation circuits 421 correspond one-to-one with K scan chains, and the kth activation circuit 421 is used to output an activation rate of P. k The logic value is stored in the first register 422, which is used to store the logic values ​​output by the K activation circuits 421 and keeps them unchanged within a preset period. The K output ports are used to output the logic values ​​stored in the first register 422, and the K output ports correspond one-to-one with the K scan chains, where K > 1.

[0186] The activation circuit 421 can be an output line connected to the PRPG, a combinational logic circuit LC, or a fixed logic value output device 450. The output line connected to the PRPG has a 50% probability of outputting 0 and a 50% probability of outputting 1. The fixed logic value output device 450 is used to fix either an output of 0 or a fixed output of 1, meaning the probability of outputting 0 or 1 is 100%. The combinational logic circuit LC can be a multi-input AND gate, with each input provided by the PRPG. For example, when the AND gate has two inputs, the probability of the combinational logic circuit LC outputting 1 can be 0.5 × 0.5 = 0.25; when the AND gate has three inputs, the probability of the combinational logic circuit LC outputting 1 can be 0.5 × 0.5 × 0.5 = 0.125.

[0187] Optionally, the number of activation circuits 421 in the low-power controller 420 may be greater than K, the number of output ports may be greater than K, and the first register may be one register or multiple registers. The above examples should not be construed as limiting this application.

[0188] Optionally, the number of activation circuits 421 in the low-power controller 420 can also be less than K. In this case, one activation circuit 421 can correspond to multiple output ports, that is, one activation circuit 421 can correspond to multiple scan chains.

[0189] The logic values ​​output by the K output ports can constitute a low-power control signal. For example, when the logic value output by the k-th output port is 1, the k-th scan chain is a non-low-power scan chain; when the logic value output by the k-th output port is 0, the k-th scan chain is a low-power scan chain, where 1 ≤ k ≤ K. The above example of logic value 1 corresponding to a non-low-power scan chain and logic value 0 corresponding to a low-power scan chain is merely illustrative. It is also possible for logic value 0 to correspond to a non-low-power scan chain and logic value 1 to correspond to a low-power scan chain. Those skilled in the art can configure this according to actual needs, and the above example should not be construed as a limitation of this application.

[0190] For example, the test vector has a length of 5, the circuit under test has 4 scan chains, and the low-power control signal is "00000 00000 1111111111". A logic value of 1 output by the low-power controller 420 corresponds to a non-low-power scan chain, and a logic value of 0 corresponds to a low-power scan chain. Every 5 consecutive logic values ​​in the low-power control signal correspond to one scan chain, meaning that the logic value output by the low-power controller 420 remains unchanged within the input cycle of the test vector. The first scan chain corresponds to "00000", and is a low-power scan chain; the second scan chain corresponds to "00000", and is a low-power scan chain; the third scan chain corresponds to "11111", and is a non-low-power scan chain; the fourth scan chain corresponds to "11111", and is a non-low-power scan chain.

[0191] Figure 15 This is a schematic diagram of another low-power controller provided in an embodiment of this application.

[0192] The low-power controller 420 may include A+B activation circuits 461, a second register 462, a third register 463, a fourth register 465, a fifth register 467, and multiple output ports 464, where A≥1, B≥1, and A×B≥K. The multiple output ports 464 are connected to a first multiplexer 430.

[0193] The activation circuit 461 can be an output line connected to the PRPG, a combinational logic circuit LC, or a fixed logic value output device 450. The output line connected to the PRPG has a 50% probability of outputting 0 and a 50% probability of outputting 1. The fixed logic value output device 450 is used to fix either an output of 0 or a fixed output of 1, meaning the probability of outputting 0 or 1 is 100%. The combinational logic circuit LC can be a multi-input AND gate, with each input provided by the PRPG. For example, when the AND gate has two inputs, the probability of the combinational logic circuit LC outputting 1 can be 0.5 × 0.5 = 0.25; when the AND gate has three inputs, the probability of the combinational logic circuit LC outputting 1 can be 0.5 × 0.5 × 0.5 = 0.125.

[0194] The following describes in detail the method of outputting low-power control signals by the low-power controller 420 provided in this application embodiment, taking logic value 1 corresponding to a non-low-power scan chain and logic value 0 corresponding to a low-power scan chain as an example. The method of outputting low-power control signals by logic value 420 corresponding to logic value 0 corresponding to a non-low-power scan chain and logic value 1 corresponding to a low-power scan chain is similar and will not be repeated in this application.

[0195] A activation circuits 461 are connected to a fourth register 465, a second register 462, and multiple output ports 464. The a-th activation circuit in the A activation circuits 461 corresponds to an activation rate P. a That is, P a The probability output logic value is 1, 1≤a≤A. The fourth register 465 can store the logic values ​​output by A activation circuits 461, and the data stored in the fourth register 465 changes as the logic values ​​output by the A activation circuits 461 change. The fourth register 465 can transfer the logic values ​​output by the A activation circuits 461 to the second register 462, and the logic values ​​stored in the second register 462 remain unchanged within a preset period.

[0196] B activation circuits 461 are connected to the fifth register 467, the third register 463, and multiple output ports 464. The b-th activation circuit in the B activation circuits 461 corresponds to the activation rate P. b That is, P b The probability output logic value is 1, 1≤b≤B. The fifth register 467 can store the logic values ​​output by B activation circuits 461, and the data stored in the fifth register 467 changes as the logic values ​​output by the B activation circuits 461 change. The fifth register 467 can transfer the logic values ​​output by the B activation circuits 461 to the third register 463, and the logic values ​​stored in the third register 463 remain unchanged within a preset period.

[0197] Figure 15Each AND gate (&) corresponds to an output port 464. Multiple AND gates are arranged in a two-dimensional form. Each AND gate corresponds to a third value output by a second register 462 and a fourth value output by a third register 463. The logical value output by the first output port is the result of ANDing the corresponding third value output by the second register 462 and the corresponding fourth value output by the third register 463. The probability of the first output port outputting 1 is equal to the probability of the corresponding third value being 1 multiplied by the probability of the corresponding fourth value being 1. The first output port can be any one of the output ports 464.

[0198] For example, the circuit under test has 10 scan chains C1 to C10. The 10 scan chains are ordered from highest to lowest frequency as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 scan chain groups, with preset activation rates P1 of 1, P2 of 0.5, and P3 of 0.25. The preset expected flip rate P is 0.25. After calculation based on constraints (1) and (2), the allocation ratios D1, D2, and D3 are 0.1, 0.7, and 0.2, respectively. That is, one scan chain has an activation rate of 1, seven scan chains have an activation rate of 0.5, and two scan chains have an activation rate of 0.25. The allocation ratios D1, D2, and D3 satisfy 0.1×1 + 0.7×0.5 + 0.2×0.25 = 0.25×2. This means that scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2 to C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9 to C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0199] Since the circuit under test has 10 scan chains, a 4×4 AND gate arrangement can be used (4×4 = 16 > 10). It should be understood that 5×5 or 6×4 AND gate arrangements can also be used, as long as the number of AND gates is not less than the number of output ports.

[0200] Based on the values ​​of D1, D2, D3 and P1, P2, P3, the probability of the fourth register 465 and the fifth register 467 outputting 1 can be determined. That is, the logic value output by the corresponding activation circuit 461 is selected and stored in the fourth register 465 and the fifth register 467. For example, the fourth register 465 has the probabilities of outputting 1 as a row AND gate with probabilities of 1, 1, 1, 1, respectively, and the fifth register 467 has the probabilities of outputting 1 as a column AND gate with probabilities of 1, 0.5, 0.5, 0.25, respectively. The fourth register 465 passes the output logic value to the second register 462, and the fifth register 467 passes the output logic value to the third register 463. The 16 output ports 464 can output 4 logic values ​​of 1 (greater than 1) with a probability of 1, 8 logic values ​​of 1 (greater than 7) with a probability of 0.5, and 4 logic values ​​of 1 (greater than 2) with a probability of 0.25. The low-power controller 420 can select output ports with matching probabilities for 10 scan chains.

[0201] Figure 16 This is a schematic diagram of another low-power controller provided in an embodiment of this application.

[0202] The low-power controller 420 may include n activation circuits 471, an activation circuit selector 475, a second register 472, a third register 473, a sixth register 474, a second multiplexer 476, and multiple output ports 479. The activation circuit selector 475 includes m seventh registers and a shift controller 478, where the seventh registers may be shift registers, m ≥ 1. The multiple output ports 479 are connected to the first multiplexer 430.

[0203] The activation circuit 471 can be an output line connected to the PRPG, a combinational logic circuit LC, or a fixed logic value output device 450. The output line connected to the PRPG has a 50% probability of outputting 0 and a 50% probability of outputting 1. The fixed logic value output device 450 is used to fix either an output of 0 or a fixed output of 1, meaning the probability of outputting 0 or 1 is 100%. The combinational logic circuit LC can be a multi-input AND gate, with each input provided by the PRPG. For example, when the AND gate has two inputs, the probability of the combinational logic circuit LC outputting 1 can be 0.5 × 0.5 = 0.25; when the AND gate has three inputs, the probability of the combinational logic circuit LC outputting 1 can be 0.5 × 0.5 × 0.5 = 0.125.

[0204] The following describes in detail the method of outputting low-power control signals by the low-power controller 420 provided in this application embodiment, taking logic value 1 corresponding to a non-low-power scan chain and logic value 0 corresponding to a low-power scan chain as an example. The method of outputting low-power control signals by logic value 420 corresponding to logic value 0 corresponding to a non-low-power scan chain and logic value 1 corresponding to a low-power scan chain is similar and will not be repeated in this application.

[0205] The second multiplexer 476 is connected to the activation circuit selector 475 and n activation circuits 471. The n selection values ​​output by the activation circuit selector 475 correspond one-to-one with the n activation circuits. The second multiplexer 476 is used to output the logic value output by the i-th activation circuit based on the i-th selection value output by the activation circuit selector 475, where 1 ≤ i ≤ n. For example, n = 4, m = 2, the shift controller 478 controls the seventh register 1 to output 0, and controls the seventh register 2 to output 0. Then, the selection value output by the activation circuit selector 475 is 00. The selection value 00 corresponds to the first activation circuit. The second multiplexer 476 outputs the logic value output by the first activation circuit. The probability that the first activation circuit outputs 1 is P1, 2. m ≥n.

[0206] The sixth register 474 can store the logic value output by the activation circuit 471, and the data stored in the sixth register 474 will change as the logic value output by the activation circuit 471 changes. The sixth register 474 can pass the logic value output by the activation circuit 471 to the second register 472 and the third register 473, and the logic values ​​stored in the second register 472 and the third register 473 remain unchanged within a preset period.

[0207] Figure 16 Each AND gate (&) corresponds to an output port 479. Multiple AND gates are arranged in a two-dimensional configuration. Each AND gate corresponds to a third value output by a second register 472 and a fourth value output by a third register 473. The logical value output by the first output port is the result of the AND operation of the corresponding third value output by the second register 472 and the corresponding fourth value output by the third register 473. The probability of the first output port outputting 1 is equal to the probability of the corresponding third value being 1 multiplied by the probability of the corresponding fourth value being 1. The first output port can be any one of the output ports 479.

[0208] For example, the circuit under test has 10 scan chains C1 to C10. The 10 scan chains are ordered from highest to lowest frequency as follows: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10. These 10 scan chains are divided into 3 scan chain groups, with preset activation rates P1 of 1, P2 of 0.5, and P3 of 0.25. The preset expected flip rate P is 0.25. After calculation based on constraints (1) and (2), the allocation ratios D1, D2, and D3 are 0.1, 0.7, and 0.2, respectively. That is, one scan chain has an activation rate of 1, seven scan chains have an activation rate of 0.5, and two scan chains have an activation rate of 0.25. The allocation ratios D1, D2, and D3 satisfy 0.1×1 + 0.7×0.5 + 0.2×0.25 = 0.25×2. This means that scan chain C1 is assigned to the first scan chain group with an activation rate of 1; scan chains C2 to C8 are assigned to the second scan chain group with an activation rate of 0.5; and scan chains C9 to C10 are assigned to the third scan chain group with an activation rate of 0.25.

[0209] Since the circuit under test has 10 scan chains, a 4×4 AND gate arrangement can be used (4×4 = 16 > 10). It should be understood that 5×5 or 6×4 AND gate arrangements can also be used, as long as the number of AND gates is not less than the number of output ports.

[0210] Based on the values ​​of D1, D2, D3 and P1, P2, P3, the probability of the second register 472 and the third register 473 outputting 1 can be determined. That is, the logic value output by the corresponding activation circuit 471 is selected and stored in the sixth register 474. The sixth register 474 then passes the output logic value to the second register 472 and the third register 473. For example, the second register 472, being a 4-row AND gate, outputs 1 with probabilities of 1, 1, 1, and 1 respectively; the third register 473, being a 4-column AND gate, outputs 1 with probabilities of 1, 0.5, 0.5, and 0.25 respectively. The 16 output ports 479 can output 4 logic values ​​(greater than 1) with a probability of 1, 8 logic values ​​(greater than 7) with a probability of 0.5, and 4 logic values ​​(greater than 2) with a probability of 0.25. The low-power controller 420 can select output ports with matching probabilities for 10 scan chains.

[0211] The selection value output by the activation circuit selector 475 can control the probability that the scan chain is set to a non-low-power scan chain, so that the test circuit 400 can be reused in multiple different circuits under test, and has strong generalization ability.

[0212] Figure 17This is a schematic diagram of a random constant generator provided in an embodiment of this application. The 2DXOR decoder can use two register algorithms, such as Hold reg(x), to generate random 01 fixed values ​​with a 50% probability. That is, there is a 50% probability of generating a test vector that is all 0 and a 50% probability of generating a test vector that is all 1.

[0213] The test circuit and circuit testing method according to embodiments of this application have been described above. The following will be combined with... Figure 18 and Figure 19 This application describes apparatus and devices according to embodiments thereof.

[0214] This application also provides a computer storage medium storing program instructions, which, when executed, may include, for example... Figure 8 , Figure 9 and Figure 12 Some or all of the steps of the method in the corresponding embodiment.

[0215] Figure 18 This diagram illustrates the structure of a computer device 1800 according to an embodiment of this application. The computer device 1800 includes an acquisition module 1810 and a processing module 1820. The acquisition module 1810 and the processing module 1820 can be implemented in software, hardware, or a combination of both. Therefore, the computer device 1800 can be a computer simulation tool for implementing a method for allocating activation rates to a scan chain, such as an EDA software tool or related modules or devices with said tool installed.

[0216] The acquisition module 1810 is used to acquire circuit fault information in order to perform... Figure 8 810 in the method, Figure 9 910 and / or in the method Figure 12 Method 1210.

[0217] Processing module 1820 is used to allocate corresponding activation rates to the scan chain based on circuit fault information and execute... Figure 8 , Figure 9 and Figure 12 Some or all of the steps in the method.

[0218] Figure 19 This is a structural example diagram of another computer device 1900 provided in an embodiment of this application. The computer device 1900 includes a processor 1902, a communication interface 1903, and a memory 1904. One example of the computer device 1900 is a computing device, such as a server for performing EDA simulations.

[0219] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1902. The processor 1902 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. In implementation, each step of the above method can be completed by the integrated logic circuits in the hardware of the processor 1902 or by instructions in software form. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.

[0220] The memory 1904 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory used in the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0221] The processor 1902, memory 1904, and communication interface 1903 can communicate via a bus. Memory 1904 stores executable code, and the processor 1902 reads the executable code from memory 1904 to execute the corresponding method. Memory 1904 may also include other software modules required for running processes, such as an operating system. The operating system can be Linux. TM UNIX TM WINDOWS TM wait.

[0222] For example, the executable code in memory 1904 is used to implement Figure 8 , Figure 9 and Figure 12 The method shown involves processor 1902 reading the executable code from memory 1904 to execute it. Figure 8 , Figure 9 and Figure 12 The method shown.

[0223] In some embodiments of this application, the disclosed methods can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art. Figure 20 A conceptual partial view schematically illustrates an example computer program product arranged according to at least some embodiments shown herein, the example computer program product including a computer program for executing computer processes on a computing device. In one embodiment, the example computer program product 2000 is provided using a signal carrying medium 2001. The signal carrying medium 2001 may include one or more program instructions 2002, which, when executed by one or more processors, can provide the above-described instructions for... Figure 8 , Figure 9 and Figure 12 The functions or parts thereof described in the methods shown. Therefore, for example, refer to... Figure 8 , Figure 9 and Figure 12 In the embodiments shown, one or more features may be provided by one or more instructions associated with the signal carrying medium 2001.

[0224] In some examples, the signal-bearing medium 2001 may comprise a computer-readable medium 2003, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video optical disc (DVD), digital magnetic tape, a memory, read-only memory (ROM), or random access memory (RAM), etc. In some embodiments, the signal-bearing medium 2001 may comprise a computer-recordable medium 2004, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some embodiments, the signal-bearing medium 2001 may comprise a communication medium 2005, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). Therefore, for example, the signal-bearing medium 2001 may be conveyed by a wireless communication medium 2005 (e.g., a wireless communication medium conforming to the IEEE 802.11 standard or other transmission protocols). One or more program instructions 2002 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the aforementioned computing device can be configured to provide various operations, functions, or actions in response to program instructions 2002 transmitted to the computing device via one or more of computer-readable media 2003, computer-recordable media 2004, and / or communication media 2005. It should be understood that the arrangements described herein are merely illustrative. Therefore, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements can be omitted depending on the desired result. Furthermore, many of the described elements are functional entities that can be implemented as discrete or distributed components, or in any suitable combination and location in conjunction with other components.

[0225] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0226] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0227] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0228] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0229] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0230] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0231] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A test circuit, characterized in that, The test circuit is applied to a circuit under test, which includes a pseudo-random vector generator and K scan chains. The test circuit is connected to the pseudo-random vector generator and the K scan chains, where K > 1. The test circuit includes: A random constant generator is used to generate a first test vector, wherein the proportion of consecutive 0s or consecutive 1s in the first test vector is greater than a preset threshold. A low-power controller, connected to the pseudo-random vector generator, is used to generate a low-power control signal. The low-power control signal is used to set each scan chain as a low-power scan chain or a non-low-power scan chain according to the correlation between each scan chain in the K scan chains and the fault in the circuit under test. A first multiplexer, connected to the random constant generator, the low-power controller, and the K scan chains, is used to input the first test vector to the first scan chain when the first scan chain is a low-power scan chain, or to input the second test vector to the first scan chain when the first scan chain is a non-low-power scan chain. The first scan chain is any one of the K scan chains, and the second test vector is a random binary sequence.

2. The test circuit according to claim 1, characterized in that, It also includes a phase shifter, which is connected to the first multiplexer and is used to generate the second test vector.

3. The test circuit according to claim 1 or 2, characterized in that, The low-power controller includes at least K output ports, which are connected to the first multiplexer. K of the K output ports correspond one-to-one with the K scan chains. The logic values ​​output by the K output ports belong to the low-power control signal. The first output port corresponds to the first scan chain and is one of the K output ports. When the logic value output by the first output port is a first value, the first scan chain is a non-low-power scan chain; or, when the logic value output by the first output port is a second value, the first scan chain is a low-power scan chain, where the first value is 0 and the second value is 1, or the first value is 1 and the second value is 0.

4. The test circuit according to claim 3, characterized in that, The low-power controller further includes a first register and multiple activation circuits. At least some of the multiple activation circuits are connected to the pseudo-random vector generator. The multiple activation circuits are connected to the K output ports through the first register. The first register is used to store the logic values ​​output by the multiple activation circuits and keeps them unchanged within a preset period. Each of the K output ports corresponds to at least one activation circuit. The first activation circuit is used to control the probability of the first output port outputting the first value through the first register. The first activation circuit is the activation circuit corresponding to the first output port.

5. The test circuit according to claim 4, characterized in that, The low-power controller further includes an activation circuit selector and a second multiplexer. The second multiplexer is connected to the activation circuit selector and the plurality of activation circuits. The plurality of selection values ​​output by the activation circuit selector correspond one-to-one with the plurality of activation circuits. The second multiplexer is used to output the logic value output by the first activation circuit according to the first selection value output by the activation circuit selector. The first selection value is one of the plurality of selection values ​​and corresponds to the first activation circuit.

6. The test circuit according to claim 4 or 5, characterized in that, The first register includes a second register and a third register. The first value output by the first output port is the result of ANDing the third value output by the second register and the fourth value output by the third register. The probability of the first output port outputting the first value is equal to the probability of the second register outputting the third value multiplied by the probability of the third register outputting the fourth value.

7. A circuit testing method, characterized in that, Applied to a circuit under test, the circuit under test comprising K scan chains, K > 1, the method includes: Obtain circuit fault information in the circuit under test; The correlation between each of the K scan chains and the fault in the circuit under test is determined based on the circuit fault information. Based on the first fault correlation, the probability of the first scan chain being a low-power scan chain or a non-low-power scan chain is determined. The first fault correlation is the correlation between the first scan chain and the fault in the circuit under test. The first scan chain is any one of the K scan chains. The first fault correlation is proportional to the probability that the first scan chain is a non-low-power scan chain. The probability of being a low-power scan chain or a non-low-power scan chain is used to input a first test vector or a second test vector for the first scan chain. The proportion of consecutive 0s or consecutive 1s in the first test vector is greater than a preset threshold. The second test vector is a random binary sequence.

8. The method according to claim 7, characterized in that, The acquisition of circuit fault information in the circuit under test includes: The circuit under test is tested or analyzed using test vectors from the Logic Self-Test (LBIST) or the Automatic Test Vector Generation (ATPG) to obtain circuit fault information.

9. The method according to claim 7 or 8, characterized in that, The first fault correlation includes the number of times the first scan chain is determined to be related to a fault in the circuit under test.

10. The method according to any one of claims 7 to 9, characterized in that, The K scan chains correspond to n scan chain groups, and the n scan chain groups correspond one-to-one with n preset activation rates. Among the n preset activation rates, the i-th activation rate is used to represent the probability that all scan chains in the i-th scan chain group are set as non-low-power scan chains, 1≤i≤n, 1<n≤K.

11. The method according to claim 10, characterized in that, The correlation between the scan chain in the i-th scan chain group and the fault in the circuit under test is greater than that between the scan chain in the j-th scan chain group and the fault in the circuit under test. The i-th activation rate is greater than the j-th activation rate, 1≤j≤n, i≠j.

12. The method according to claim 10 or 11, characterized in that, D1+D2+…+D n =1 and D1×P1+D2×P2+…+D n ×P n = P×2, where, D i Equals the number of scan chains in the i-th scan chain group divided by K, P i P is the activation rate corresponding to the i-th scan chain group, and P is the preset flip rate.

13. A computer device, characterized in that, Applied to a circuit under test, the circuit under test includes K scan chains, K > 1, the device includes: The acquisition module is used to acquire circuit fault information in the circuit under test; The processing module is used to determine the correlation between each of the K scan chains and the fault in the circuit under test based on the circuit fault information. The processing module is further configured to determine the probability that the first scan chain is a low-power scan chain or a non-low-power scan chain based on a first fault correlation degree. The first fault correlation degree is the correlation between the first scan chain and a fault in the circuit under test. The first scan chain is any one of the K scan chains. The first fault correlation degree is proportional to the probability that the first scan chain is a non-low-power scan chain. The probability of a low-power scan chain or a non-low-power scan chain is used to input a first test vector or a second test vector for the first scan chain. The proportion of consecutive 0s or consecutive 1s in the first test vector is greater than a preset threshold. The second test vector is a random binary sequence.

14. The apparatus according to claim 13, characterized in that, The acquisition module is specifically used for: The circuit under test is tested or analyzed using test vectors from the Logic Self-Test (LBIST) or the Automatic Test Vector Generation (ATPG) to obtain circuit fault information.

15. The apparatus according to claim 13 or 14, characterized in that, The first fault correlation includes the number of times the first scan chain is determined to be related to a fault in the circuit under test.

16. The apparatus according to any one of claims 13 to 15, characterized in that, The K scan chains correspond to n scan chain groups, and the n scan chain groups correspond one-to-one with n preset activation rates. Among the n preset activation rates, the i-th activation rate is used to represent the probability that all scan chains in the i-th scan chain group are set as non-low-power scan chains, 1≤i≤n, 1<n≤K.

17. The apparatus according to claim 16, characterized in that, The correlation between the scan chain in the i-th scan chain group and the fault in the circuit under test is greater than that between the scan chain in the j-th scan chain group and the fault in the circuit under test. The i-th activation rate is greater than the j-th activation rate, 1≤j≤n, i≠j.

18. The apparatus according to claim 16 or 17, characterized in that, D1+D2+…+D n =1 and D1×P1+D2×P2+…+D n ×P n = P×2, where, D i Equals the number of scan chains in the i-th scan chain group divided by K, P i P is the activation rate corresponding to the i-th scan chain group, and P is the preset flip rate.

19. A circuit, characterized in that, It includes a pseudo-random vector generator, K scan chains, and a test circuit as described in any one of claims 1 to 6, where K > 1.

20. A computer device, characterized in that, include: A processor configured to be coupled to a memory, read and execute instructions and / or program code in the memory to perform the method as described in any one of claims 7 to 12.

21. A computer-readable medium, characterized in that, The computer-readable medium stores computer program code that, when executed on a computer, causes the computer to perform the method as described in any one of claims 7 to 12.

22. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to perform the method as described in any one of claims 7 to 12.

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