IGBT equivalent circuit model and IGBT common emitter parasitic inductance calculation method

Abstract

The invention discloses an IGBT equivalent circuit model and an IGBT common emitter parasitic inductance calculation method. The combination of the capacitor and the voltage source of the direct current side branch can simulate energy supporting and filtering effects, the load inductance and the load parasitic inductance of the load side branch can reflect the influence of an inductive load and line stray parameters, and the grid electrode parasitic inductance circuit, the collector electrode parasitic inductance circuit and the emitter electrode parasitic inductance circuit of the IGBT branch correspond to stray inductances of different electrode outgoing lines respectively. Parasitic effects of grid driving signal transmission and a collector current path are accurately reflected, and an FWD chip and a freewheeling parasitic inductance circuit of a freewheeling branch truly simulate a freewheeling path and related stray parameters when an IGBT is turned off. In conclusion, the circuit is divided into the direct current side branch circuit, the load side branch circuit, the IGBT branch circuit and the follow current branch circuit, core elements and parasitic parameters of all the branch circuits are subjected to clear modeling, the multi-loop coupling characteristic of the IGBT in actual work can be completely reproduced, and the consistency of simulation analysis and engineering application is improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to an equivalent circuit model of IGBT and a method for calculating the parasitic inductance of IGBT common emitter. Background Technology

[0002] The core structure of an Insulated Gate Bipolar Transistor (IGBT) consists of a gate, collector, and emitter. During operation, the formation and shutdown of the internal conductive channel are controlled by the gate voltage, involving two key circuits: the gate circuit and the collector-emitter circuit. The gate circuit transmits the drive signal; current flows in from the gate and out through the emitter. The collector-emitter circuit is responsible for main power transmission; current flows in from the collector and out through the emitter. Specifically, when a forward voltage is applied to the gate, the channel opens, allowing the flow of charge carriers (electrons and holes) between the collector and emitter, thus achieving efficient high-current transmission. When the gate voltage is removed or a reverse voltage is applied, the channel closes, the flow of charge carriers is interrupted, and current transmission stops.

[0003] In the actual structure and packaging of IGBTs, the emitter is usually connected to external circuits via wire bonding or conductive connections. These connections and the conductive areas inside the chip inevitably contain parasitic inductance. Furthermore, as the emitter serves as a common node for both the gate and collector-emitter circuits, emitter-related parasitic inductance exists in both circuits simultaneously, thus forming a common-emitter parasitic inductance.

[0004] During IGBT switching, the collector current changes rapidly, and the common-emitter parasitic inductance generates an induced electromotive force (EMF) according to the law of electromagnetic induction. This EMF is directly superimposed on the device's terminal voltage, causing voltage spikes or oscillations during switching, affecting switching losses and the voltage stress the device withstands. Simultaneously, as the common-emitter parasitic inductance serves as a common path between the gate and collector-emitter circuits, the induced EMF generated by the collector current change couples to the gate circuit through this inductance, interfering with the stable transmission of the gate voltage and causing distortion of the gate drive signal (such as gate voltage overshoot or oscillation), thus affecting the IGBT's turn-on and turn-off speeds. Furthermore, the parasitic inductance and the device's junction capacitance (such as gate-emitter capacitance and collector-emitter capacitance) form an LC resonant circuit, inducing high-frequency oscillations during switching and increasing electromagnetic interference. These factors combined significantly impact the dynamic characteristics of the IGBT due to the common-emitter parasitic inductance. To deeply analyze the specific mechanisms of this impact, it is necessary to transform the device's physical structure into quantifiable circuit parameters; therefore, establishing an accurate IGBT equivalent circuit model is essential.

[0005] In existing technologies, the construction of IGBT equivalent circuit models often employs simplified methods, typically treating only the parasitic inductances of the collector and emitter as concentrated parasitic inductances. This means ignoring the distribution of parasitic inductances at different locations within the actual device, merging the parasitic inductances from different locations such as the internal conductive regions and wire bonds of the IGBT into a single inductance parameter, and using a single node in the equivalent circuit model to represent the overall effect of these parasitic inductances. This fails to distinguish the differentiated distribution of emitter-related parasitic inductances in the gate circuit and the collector-emitter circuit. Therefore, this simplification cannot accurately reflect the coupling effect of common-emitter parasitic inductance between the gate and collector-emitter circuits, resulting in simulation results from the IGBT equivalent circuit model that cannot accurately reproduce actual dynamic characteristics (such as nonlinear changes in gate voltage and current oscillation amplitude), leading to deviations from the actual operating conditions of the IGBT. Summary of the Invention

[0006] In view of the above problems, this application provides an equivalent circuit model of IGBT and a method for calculating the parasitic inductance of IGBT common emitter.

[0007] To solve the above-mentioned technical problems, this application proposes the following solution: Firstly, this application provides an equivalent circuit model of an IGBT, comprising: a DC-side branch, including a DC voltage source and a capacitor, wherein the positive terminal of the DC voltage source is connected to the positive terminal of the capacitor, and the negative terminal of the DC voltage source is connected to the negative terminal of the capacitor; a load-side branch, including a load inductor and a load parasitic inductor, wherein one end of the load parasitic inductor is connected to the load inductor, and the other end is connected to the positive terminal of the DC-side branch; and an IGBT branch, including an IGBT and an IGBT parasitic inductance network, wherein the IGBT parasitic inductance network includes a gate parasitic inductance circuit, a collector parasitic inductance, an emitter parasitic inductance circuit, and a gate parasitic inductance circuit. The parasitic inductance circuit is connected between the emitter parasitic inductance circuit and the IGBT gate; the collector parasitic inductance is connected between the IGBT collector and the load inductor; and the emitter parasitic inductance circuit is connected between the IGBT emitter and the negative terminal of the DC-side branch. The freewheeling branch includes a freewheeling diode (FWD) chip and a freewheeling parasitic inductance circuit. The cathode of the FWD chip is connected to one end of the freewheeling parasitic inductance circuit, and the anode of the FWD chip is connected to the connection path between the load inductor and the load parasitic inductor. The other end of the freewheeling parasitic inductance circuit is connected to the connection path between the load-side branch and the IGBT branch.

[0008] Secondly, this application provides a method for calculating the common-emitter parasitic inductance of an IGBT. The method is applied to the IGBT equivalent circuit model as described in the first aspect. In the IGBT equivalent circuit model, the gate parasitic inductance circuit, the IGBT gate and emitter parasitic inductance circuit constitute the gate loop, and the collector parasitic inductance, the IGBT collector and emitter, the emitter parasitic inductance circuit, the load-side branch, and the DC-side branch constitute the collector-emitter loop. The method includes: obtaining the gate voltage waveform and collector current waveform during the IGBT turn-on process in the IGBT equivalent circuit model, wherein the gate voltage is the common-emitter parasitic inductance at the gate... The voltage presented between the gate pin and the emitter pin of the IGBT device is determined by the combined action of the emitter parasitic inductance circuit, the emitter parasitic inductance circuit, and the IGBT gate-emitter capacitor. The collector current is the current flowing through the IGBT collector and the collector parasitic inductance. The gate voltage change is determined based on the gate voltage waveform, and the collector current change rate is determined based on the collector current waveform. The inductance value of the first emitter parasitic inductance in the emitter parasitic inductance circuit is calculated based on the gate voltage change and the collector current change rate. The first emitter parasitic inductance is a common emitter parasitic inductance that exists simultaneously in both the gate circuit and the collector-emitter circuit.

[0009] By employing the above-described technical solution, the technical solution provided in this application has at least the following advantages: This application distinguishes the differentiated distribution of common-emitter parasitic inductance in the gate and collector-emitter circuits by setting an independent emitter parasitic inductance circuit in the IGBT branch and clearly defining its connection relationship with the gate parasitic inductance circuit, the IGBT emitter, and the negative terminal of the DC-side branch. Specifically, the emitter parasitic inductance circuit specifically addresses the parasitic inductance of the connection between the emitter and external circuitry, as well as the conductive area inside the chip. One end of the circuit is connected to the IGBT emitter, and the other end is connected to the negative terminal of the DC-side branch. The gate parasitic inductance circuit is connected between the emitter parasitic inductance circuit and the IGBT gate. This means that the emitter-related parasitic inductance in the gate circuit must pass through a series path between the gate parasitic inductance circuit and the emitter parasitic inductance circuit, while the emitter-related parasitic inductance in the collector-emitter circuit forms a direct path through the emitter parasitic inductance circuit. Through this structural design, the equivalent circuit model clearly distinguishes the different paths and distribution characteristics of the common-emitter parasitic inductance in the two circuits. This approach not only reflects the commonality of the emitter as a common node, but also distinguishes the differentiated role of parasitic inductance in gate drive signal transmission and main power current transmission, thus avoiding the limitation of simplifying it into a single lumped parameter.

[0010] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This paper shows a schematic diagram of the equivalent circuit model of an IGBT provided in an embodiment of this application; Figure 2 This paper shows a schematic diagram of another IGBT equivalent circuit model provided in an embodiment of this application; Figure 3 This paper shows a schematic diagram of another IGBT equivalent circuit model provided in an embodiment of this application; Figure 4 This paper shows a schematic diagram of another IGBT equivalent circuit model provided in an embodiment of this application; Figure 5 A flowchart illustrating a method for calculating the common-emitter parasitic inductance of an IGBT according to an embodiment of this application is shown. Figure 6 This diagram illustrates the variation of gate voltage and collector current according to an embodiment of this application. Detailed Implementation

[0012] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0013] In the embodiments of this application, the terms "first," "second," etc., do not have a logical or temporal dependency, nor do they limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another.

[0014] In this application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0015] It should also be understood that the term “if” can be interpreted as “when” or “upon”, or “in response to determination” or “in response to detection”. Similarly, depending on the context, the phrase “if determination…” or “if detection [the stated condition or event]” can be interpreted as “when determination…” or “in response to determination…” or “when detection [the stated condition or event]” or “in response to detection [the stated condition or event]”.

[0016] During IGBT switching, the collector current changes rapidly, and the common-emitter parasitic inductance generates an induced electromotive force (EMF) according to the law of electromagnetic induction. This EMF is directly superimposed on the device's terminal voltage, causing voltage spikes or oscillations during switching, affecting switching losses and the voltage stress the device can withstand. Simultaneously, since the common-emitter parasitic inductance is the common path for both the gate and collector-emitter circuits, the induced EMF generated by the collector current change couples to the gate circuit through it, interfering with the stable transmission of the gate voltage and causing distortion of the gate drive signal (such as gate voltage overshoot or oscillation), thus affecting the IGBT's switching speed. Furthermore, the parasitic inductance and the device's junction capacitance (such as gate-emitter capacitance and collector-emitter capacitance) form an LC resonant circuit, inducing high-frequency oscillations during switching and increasing electromagnetic interference. These factors combined make the common-emitter parasitic inductance significantly impact the dynamic characteristics of the IGBT. To understand the specific mechanisms of this impact, it is necessary to transform the device's physical structure into quantifiable circuit parameters; therefore, establishing an accurate IGBT equivalent circuit model becomes essential.

[0017] In existing technologies, the construction of equivalent circuit models for IGBTs often employs simplification, typically treating the parasitic inductances of the collector and emitter as concentrated parasitic inductances. That is, it ignores the distribution of parasitic inductances at different locations within the actual device, merging the parasitic inductances from different areas such as the internal conductive regions and wire bonds of the IGBT into a single inductance parameter. In the equivalent circuit model, a single node is used to centrally represent the overall effect of these parasitic inductances. This makes it impossible to distinguish the different distributions of emitter-related parasitic inductances in the gate circuit and the collector-emitter circuit. Therefore, this model cannot accurately reflect the coupling effect of common-emitter parasitic inductance between the two circuits, resulting in simulation results that cannot accurately represent actual dynamic characteristics (such as nonlinear changes in gate voltage and current oscillation amplitude), leading to a discrepancy with the actual operation of the IGBT.

[0018] Based on this, the equivalent circuit model of the IGBT in this application will be described in detail with reference to the accompanying drawings. Figure 1 A schematic diagram of the equivalent circuit model of an IGBT provided in this application.

[0019] like Figure 1As shown, the equivalent circuit model of an IGBT includes a DC-side branch, a load-side branch, an IGBT branch, and a freewheeling branch. Each branch forms a closed-loop circuit through specific electrical connections to accurately simulate the switching characteristics and parasitic parameter effects of the IGBT under actual operating conditions.

[0020] The DC-side branch serves as the energy source and voltage support for the entire circuit, including the DC voltage source U. DC The DC voltage source and capacitor C are connected in parallel, meaning the positive terminal of the DC voltage source is directly connected to the positive terminal of the capacitor, and the negative terminal of the DC voltage source is directly connected to the negative terminal of the capacitor. In this structure, the DC voltage source provides a stable DC input voltage, while the capacitor acts as a filter and energy storage, effectively suppressing voltage fluctuations caused by sudden current changes during circuit operation and ensuring the stability of the DC side voltage.

[0021] The load-side branch is used to simulate the load characteristics and line parasitic parameters in actual circuits, and consists of the load inductance. and load parasitic inductance The components are connected in series. One end of the load parasitic inductance is connected to the load inductance, and the other end is connected to the positive terminal of the DC-side branch, forming a current path from the positive terminal of the DC side to the load inductance. The load inductance mainly simulates the energy storage characteristics of an inductive load, while the load parasitic inductance is equivalent to the stray inductance present in the load line and connection path. Although this type of inductance has a small value, it will affect the rate of change of current during switching, thereby generating voltage spikes and having a significant impact on circuit performance.

[0022] The IGBT branch, as the core switching part of the circuit, includes the IGBT and the IGBT parasitic inductance network. The IGBT parasitic inductance network is further subdivided into the gate parasitic inductance circuit and the collector parasitic inductance. The IGBT includes both emitter parasitic inductance circuits, with each parasitic inductor corresponding to stray inductances in different IGBT electrode leads and connection structures. Specifically, the gate parasitic inductance circuit is connected between the emitter parasitic inductance circuit and the IGBT gate, simulating the parasitic inductance in the gate drive signal transmission path and affecting the rise and fall speed of the gate voltage. The collector parasitic inductance is connected between the IGBT collector and the load inductor; one end is connected to the IGBT collector, and the other end is connected to the connection path between the load inductor and the load parasitic inductor, simulating the parasitic inductance of the collector lead. The emitter parasitic inductance circuit is connected between the IGBT emitter and the negative terminal of the DC-side branch; one end is connected to the IGBT emitter, and the other end is connected to the negative terminal of the DC-side capacitor, simulating the parasitic inductance of the emitter lead. These parasitic inductances will form LC oscillations with the capacitors in the circuit during IGBT switching, affecting switching losses and electromagnetic compatibility.

[0023] The freewheeling branch, serving as the current freewheeling path when the IGBT is turned off, includes a freewheeling diode (FWD) chip and a freewheeling parasitic inductor circuit. The cathode of the FWD chip is connected to one end of the freewheeling parasitic inductor circuit, while the other end of the circuit is connected to the path between the collector parasitic inductor and the load-side branch. Simultaneously, the anode of the FWD chip is connected to the path between the load inductor and the load parasitic inductor, forming a complete freewheeling loop. In this structure, the FWD chip conducts when the IGBT is turned off, providing a release path for the energy stored in the load inductor and preventing excessively high reverse voltage from damaging the IGBT due to sudden current changes. The freewheeling parasitic inductor circuit is equivalent to the stray inductance in the freewheeling diode lead and connecting lines; its value affects the rate of change of the freewheeling current, directly influencing the voltage waveform and electromagnetic interference characteristics during the freewheeling process.

[0024] As can be seen from the above, this application incorporates key elements affecting the dynamic characteristics of IGBTs in the actual circuit into the simulation range through the refined construction of the DC-side branch, load-side branch, IGBT branch, and freewheeling branch. The capacitor and voltage source on the DC side not only provide stable energy support, but their interaction with the parasitic inductance of each branch can also reflect the real situation of voltage fluctuations during switching. The inductance and parasitic inductance on the load side accurately reproduce the energy storage characteristics of inductive loads during current changes and the constraint of stray parameters on the rate of current change, which directly affect the voltage spikes and energy losses during IGBT switching. In the IGBT branch, the parasitic inductance networks of the gate, collector, and emitter correspond to the stray parameters in the gate drive signal transmission and main current path, respectively. Among them, the gate parasitic inductance affects the rise / fall rate of the gate voltage, thereby changing the turn-on and turn-off time of the IGBT. The collector and emitter parasitic inductance generate induced electromotive force when the current changes, forming oscillations with the junction capacitance of the IGBT, which is completely consistent with the surge voltage and switching loss characteristics that occur during actual switching. The FWD chip and freewheeling parasitic inductor circuit of the freewheeling branch realistically simulate the freewheeling path of the load current after the IGBT is turned off. The influence of the freewheeling parasitic inductance on the rate of change of the freewheeling current, as well as the resulting electromagnetic interference characteristics, are consistent with actual operating conditions. It is this comprehensive coverage of the core parameters and interactions of each branch that enables the model to accurately reproduce the dynamic processes of the IGBT, such as the current rise when it is turned on, the steady-state voltage drop when it is turned on, the voltage spike when it is turned off, and the current decay during freewheeling, especially the influence of various parasitic inductances on switching speed, loss distribution, and electromagnetic compatibility performance.

[0025] The present application further optimizes the gate drive circuit in the equivalent circuit model of IGBT by integrating a gate drive circuit that includes turn-on and turn-off circuits, and by combining accurate modeling of parasitic inductance network, improving the simulation accuracy of IGBT switching dynamic characteristics.

[0026] like Figure 2 As shown, the gate drive circuit in the IGBT branch adopts a parallel dual-channel design, consisting of a turn-on circuit and a turn-off circuit connected in parallel. The turn-on circuit is composed of a turn-on power supply U. G,on and turn-on resistor R G,on The circuit is connected in series, and the shutdown circuit consists of the shutdown power supply U. G,off and the turn-off resistor R G,off The IGBT is configured in series. This structure allows for independent and controllable drive paths during the IGBT's turn-on and turn-off phases, enabling fine-grained control of the switching process. The turn-on power supply provides a positive voltage, injecting current into the IGBT gate through the turn-on resistor to control the gate voltage rise rate; the turn-off power supply provides a negative voltage, rapidly extracting gate charge through the turn-off resistor to accelerate the gate voltage drop. By adjusting the values ​​of the turn-on and turn-off resistors, the IGBT's turn-on and turn-off speeds can be optimized separately, balancing switching losses and electromagnetic interference.

[0027] The output of the gate drive circuit is connected to the gate parasitic inductance circuit, and the input is connected to the emitter parasitic inductance circuit, forming a complete signal transmission path. This connection method fully considers the parasitic effects in actual circuits. Specifically, the gate parasitic inductance circuit simulates the stray inductance in the gate drive circuit; the LC oscillation formed by the gate and emitter capacitance affects the gate voltage waveform, leading to switching delays or oscillations. The emitter parasitic inductance circuit reflects the parasitic inductance in the emitter loop; the induced electromotive force generated by it is fed back to the gate drive loop, changing the actual voltage applied to the gate. By incorporating these two key parasitic parameters into the gate drive circuit, the distortion of the gate drive signal during transmission and the resulting changes in IGBT switching characteristics can be accurately simulated.

[0028] In actual operation, when the IGBT needs to be turned on, the turn-on circuit conducts, and the turn-on power supply charges the gate through the turn-on resistor. At this time, the gate parasitic inductance suppresses current surges, resulting in a slower gate voltage rise time and prolonging the turn-on time. Meanwhile, the induced electromotive force generated by the emitter parasitic inductance is opposite in direction to the gate voltage, further weakening the effective drive voltage and exacerbating the turn-on delay. When the IGBT needs to be turned off, the turn-off circuit conducts, and the gate charge is quickly released through the turn-off resistor and the turn-off power supply. However, the gate parasitic inductance impedes current changes, generating a reverse electromotive force in the gate circuit, which may lead to a negative overshoot of the gate voltage. The presence of the emitter parasitic inductance reduces the actual voltage drop between the gate and emitter, delaying the turn-off process.

[0029] This application comprehensively reveals the nonlinear interaction effects present in actual circuits by co-modeling the gate drive circuit and the parasitic inductance network. For example, under high-frequency switching conditions, the oscillation phenomenon caused by parasitic inductance can significantly increase switching losses and generate electromagnetic interference; however, by adjusting the resistance value of the turn-on / turn-off resistor, the gate voltage waveform can be optimized, reducing these adverse effects. This accurate simulation capability enables engineers to accurately predict the dynamic performance of IGBTs during the design phase, and to specifically optimize drive parameters (such as resistance value and power supply voltage) and layout structure (such as reducing parasitic inductance), thereby achieving comprehensive optimization of switching losses, reliability, and electromagnetic compatibility.

[0030] The present application further refines the parasitic inductance network in the equivalent circuit model of IGBT. By performing hierarchical modeling of the gate parasitic inductance circuit and the emitter parasitic inductance circuit, a more accurate simulation of the IGBT switching dynamic process is achieved.

[0031] like Figure 3 As shown, the gate parasitic inductor circuit adopts a two-stage inductor structure, including the gate line parasitic inductance L. s,GL and gate chip parasitic inductance L s,G This structural design takes into account the distribution characteristics of parasitic inductance in actual circuits: the gate line parasitic inductance mainly originates from external connection structures such as PCB traces and bonding wires, with one end connected to the output of the gate drive circuit and the other end connected to the gate chip parasitic inductance; the gate chip parasitic inductance reflects the parasitic effect of the IGBT's internal gate structure, with its other end directly connected to the IGBT's gate. During switching, the presence of these two inductors causes delays and oscillations in the gate drive signal: when the gate drive circuit outputs a step voltage, the gate line parasitic inductance first suppresses current changes, limiting the rate of gate voltage rise; subsequently, the gate chip parasitic inductance interacts with the gate-emitter capacitance inside the chip, potentially triggering high-frequency oscillations and affecting the IGBT's turn-on and turn-off times.

[0032] The emitter parasitic inductor circuit adopts a three-stage inductor topology, including the first emitter parasitic inductor L. s,E1 Second emitter parasitic inductance L s,E2 and the third emitter parasitic inductance L s,E3 For soldered IGBT devices, when the IGBT gate circuit is connected via an auxiliary emitter terminal, the auxiliary emitter terminal is directly led out from the chip emitter bonding wire, which can significantly eliminate the shared parasitic inductance between the gate circuit and the main circuit. In this case, the first emitter parasitic inductance is only a part of the parasitic inductance on the emitter side of the IGBT. For press-fit IGBT devices, since there is no auxiliary emitter structure, the emitter parasitic inductance of the gate circuit and the main circuit is completely shared. Therefore, the first emitter parasitic inductance is approximately equal to the total parasitic inductance on the emitter side of the IGBT.

[0033] This design comprehensively considers the parasitic parameter distribution in the emitter circuit: one end of the first emitter parasitic inductor is connected to the emitter of the IGBT, and the other end is connected to the connection path of the second and third emitter parasitic inductors; the other end of the second emitter parasitic inductor is connected to the input terminal of the gate drive circuit, forming the return path of the drive signal; the other end of the third emitter parasitic inductor is connected to the negative terminal of the DC side branch, forming part of the main current circuit. This structure allows the emitter parasitic inductor to simultaneously affect both the drive circuit and the main current circuit. When the main current changes, the induced electromotive force generated by the first and third emitter parasitic inductors affects the saturation voltage drop and switching losses of the IGBT; while during gate signal transmission, the presence of the second emitter parasitic inductor changes the actual voltage between the gate and emitter, causing drive signal distortion.

[0034] During the IGBT turn-on phase, the gate drive circuit outputs a positive voltage, and current charges the gate through the parasitic inductance of the gate line and the gate chip. At this time, the series connection of the two inductors slows down the rise rate of the gate voltage, prolonging the turn-on delay time. Simultaneously, the current in the emitter circuit begins to rise, and the induced electromotive force generated by the first and third emitter parasitic inductors is opposite to the direction of the main current, increasing the IGBT turn-on losses. During the IGBT turn-off phase, the gate charge is released through the gate parasitic inductor circuit. The inductor's impedance may cause a negative overshoot of the gate voltage, increasing the risk of false turn-on. At the same time, the rapid decrease in emitter current generates a positive induced electromotive force in the first emitter parasitic inductor, which is fed back to the gate drive circuit through the second emitter parasitic inductor, further affecting the stability of the turn-off process.

[0035] This refined modeling of parasitic inductance circuits accurately reflects the complex electromagnetic coupling effects present in actual circuits. For example, under high-frequency switching conditions, the synergistic effect of the gate and emitter parasitic inductance circuits can cause ringing in the switching waveform, which not only increases switching losses but also generates electromagnetic interference. By adjusting the model parameters, the impact of different layout schemes (such as reducing the gate trace length and optimizing the emitter loop structure) on parasitic inductance can be quantitatively analyzed.

[0036] The present application further improves the freewheeling branch structure in the IGBT equivalent circuit model by introducing a two-stage freewheeling parasitic inductor circuit, thereby achieving accurate simulation of the freewheeling stage during the IGBT turn-off process.

[0037] like Figure 4As shown, the freewheeling parasitic inductor circuit adopts a two-stage inductor topology, including a first parasitic inductor and a second parasitic inductor. This structural design takes into account the distribution characteristics of the freewheeling path in the actual circuit: one end of the first parasitic inductor is connected to the cathode of the FWD chip, and the other end is connected to one end of the second parasitic inductor; the other end of the second parasitic inductor is connected to the connection path between the load-side branch and the IGBT branch, specifically the connection node between the collector parasitic inductance and the load parasitic inductance. This two-stage inductor structure can more accurately reflect the parasitic inductance effect at different locations in the freewheeling path: the first parasitic inductor mainly corresponds to the parasitic inductance inside the FWD chip and the leads, while the second parasitic inductor reflects the parasitic inductance of the external connection lines and PCB traces.

[0038] During the IGBT turn-off phase, the current in the load inductor cannot change abruptly and must continue flowing through the freewheeling branch. At this time, the freewheeling current flows out of the load inductor, through the FWD chip, the first parasitic inductor, and the second parasitic inductor, finally returning to the load-side branch. The presence of these two parasitic inductors significantly affects the dynamic characteristics of the freewheeling process: when the freewheeling current begins to change, the induced electromotive force generated by the first and second parasitic inductors is opposite to the current direction, suppressing the rate of change of current and prolonging the reverse recovery process of the FWD chip. Simultaneously, the parasitic inductors and the junction capacitance of the FWD chip form an LC oscillation circuit, which may generate voltage spikes on the freewheeling path, increasing EMI risk.

[0039] At the moment the FWD chip turns on, the freewheeling current rises rapidly. The induced electromotive force on the first and second parasitic inductors increases the cathode voltage of the FWD chip, leading to a greater actual forward voltage drop. This phenomenon is particularly pronounced in high-frequency switching applications. Conversely, when the FWD chip turns off, the rapid drop in freewheeling current generates a reverse electromotive force on the parasitic inductors. This reverse electromotive force, combined with the power supply voltage, acts on the IGBT collector, potentially causing excessive voltage stress on the IGBT and even triggering a breakdown risk.

[0040] By incorporating the freewheeling parasitic inductance circuit into the equivalent circuit model, the impact of the aforementioned dynamic processes on IGBT performance can be accurately predicted. For example, under high-frequency switching conditions, voltage spikes caused by parasitic inductance may exceed the IGBT's rated voltage. By adjusting model parameters, the impact of different layout schemes (such as shortening the freewheeling path length or reducing PCB trace width) on the parasitic inductance can be quantitatively analyzed. This refined freewheeling branch modeling method not only accurately reflects the dynamic characteristics of the IGBT during the freewheeling phase but also effectively reduces switching losses and electromagnetic interference, improving the performance and stability of power electronic systems.

[0041] In addition, it should be noted that IGBT and FWD chips are usually integrated into the same power module using common substrate packaging technology. This physical structure causes the collector parasitic inductance and the second parasitic inductance to share a common path on the common path connected to the load side branch, so that the parasitic parameters of the common path affect both inductor elements at the same time.

[0042] In practical power modules, the collector of the IGBT and the anode of the FWD are typically connected to the load terminal via a copper substrate or bonding wire. This common connection path inevitably introduces parasitic inductance. According to the modeling method of this application, the parasitic parameters of this common path are simultaneously assigned to the collector parasitic inductance and the second parasitic inductance. Specifically, when current flows through the common path, the generated magnetic field energy couples with both the IGBT collector circuit and the FWD freewheeling circuit, creating a cross-effect. This coupling effect is particularly significant during switching: when the IGBT is turned on, the main current flows from the DC positive terminal through the load inductor, the common path, and the IGBT collector to the emitter. At this time, the parasitic inductance of the common path, as part of the collector parasitic inductance, affects the IGBT's turn-on characteristics. When the IGBT is turned off, the freewheeling current returns from the load inductor through the FWD chip and the common path to the load side branch. The parasitic inductance of the common path, as part of the second parasitic inductance, participates in the FWD's reverse recovery process.

[0043] This parametric coupling phenomenon has complex effects on circuit performance. At the moment the IGBT turns on, the rapid rise in collector current induces an electromotive force (EMF) in the common parasitic inductance. This EMF, on the one hand, hinders the increase of main current, prolonging the turn-on time; on the other hand, it affects the cathode voltage of the FWD chip through electromagnetic coupling, potentially causing a brief reverse bias in the FWD during IGBT turn-on. When the IGBT turns off, the change in freewheeling current induces an EMF in the common parasitic inductance, which, combined with the supply voltage, acts on the IGBT collector, increasing the amplitude of the turn-off voltage spike. Furthermore, the common parasitic inductance can also trigger dynamic interactions between the IGBT and FWD, potentially increasing switching losses in both devices under hard-switching conditions.

[0044] This application achieves accurate modeling of this coupling effect by simultaneously assigning the parasitic parameters of the common path to the collector parasitic inductance and the second parasitic inductance. In simulation analysis, this model can accurately predict the current distribution and voltage distribution within the power module, especially the dynamic characteristics under high-frequency switching conditions. For example, by adjusting the parameters of the common parasitic inductance, the impact of different package structures (such as terminal layout and number of bond wires) on switching performance can be quantitatively analyzed, guiding the optimized design of the power module. Furthermore, this model can also be used to evaluate the effectiveness of snubber circuits; for example, adding an RC snubber network to the common path can simultaneously suppress voltage spikes during IGBT turn-on and FWD reverse recovery.

[0045] As shown above, the core structure of an IGBT includes a gate, collector, and emitter. During operation, the formation and turn-off of the internal conductive channel are controlled by the gate voltage, involving two key circuits: the gate circuit and the collector-emitter circuit. The gate circuit is responsible for transmitting the drive signal; current flows in from the gate and out through the emitter. The collector-emitter circuit is responsible for main power transmission; current flows in from the collector and out through the emitter as well. Specifically, when a positive voltage is applied to the gate, the channel opens, allowing the carriers (electrons and holes) between the collector and emitter to flow smoothly, thus achieving efficient transmission of large currents. When the gate voltage is removed or a reverse voltage is applied, the channel closes, the carrier flow is interrupted, and current transmission stops.

[0046] In the actual structure and packaging of IGBTs, the emitter is usually connected to external circuits via wire bonding or conductive connections. These connections and the conductive areas inside the chip inevitably contain parasitic inductance. Furthermore, as the emitter serves as a common node for both the gate and collector-emitter circuits, emitter-related parasitic inductance exists in both circuits simultaneously, thus forming a common-emitter parasitic inductance.

[0047] Since the common-emitter parasitic inductance exists in both the gate circuit and the collector-emitter circuit, it can cause energy coupling and signal interference between the two circuits. For example, the induced electromotive force generated by the change in the collector-emitter circuit current can affect the drive signal of the gate circuit through the parasitic inductance, and the change in the gate circuit signal may in turn interfere with the dynamic characteristics of the collector-emitter circuit. Therefore, analyzing the common-emitter parasitic inductance can clarify the mechanism and strength of this coupling effect, and thus provide key references for IGBT devices in terms of package structure design (such as optimizing parasitic inductance distribution), drive circuit parameter matching (such as suppressing coupling interference), and stability control in application scenarios. Therefore, it is necessary to calculate its inductance value.

[0048] The following explains the method for calculating the parasitic inductance of the common emitter of an IGBT provided in this application. Figure 5 This is a flowchart illustrating a method for calculating the common-emitter parasitic inductance of an IGBT provided in this application. Specifically, it includes the following steps: Step 510: Obtain the gate voltage waveform and collector current waveform during the IGBT turn-on process in the IGBT equivalent circuit model.

[0049] During the IGBT turn-on process, the dynamic change of the gate voltage is affected by the parasitic inductance L of the gate chip. s,G First emitter parasitic inductance L s,E1 Second emitter parasitic inductance L s,E2 and IGBT gate emitter capacitor C GEThe combined effect is specifically manifested in the measured voltage u between the gate pin and the emitter pin of the IGBT device. GE Measured gate voltage u GE The formation of this voltage has a dual nature: on the one hand, it is the result of the gate drive signal being transmitted through the gate parasitic inductance circuit. That is, after the drive signal is output through the turn-on or turn-off circuit, it is transmitted to the gate through the gate line parasitic inductance and the gate chip parasitic inductance. During this process, the gate parasitic inductance affects the rise / fall rate of the signal, so that the measured voltage naturally reflects the transmission characteristics of the drive signal; on the other hand, due to the parasitic inductance L of the first emitter... s,E1 It is the common parasitic inductance of the gate circuit and the collector-emitter circuit. When the collector current i c When a change occurs, an induced electromotive force is generated in the inductor. This electromotive force will be superimposed on the gate circuit, changing the actual effect on the gate-emitter capacitance C. GE The voltage, which in turn causes the measured gate voltage to deviate from the ideal waveform determined solely by the drive signal. Therefore, the measured gate voltage value u GE It not only reflects the transmission characteristics of the gate drive signal, but is also affected by the coupling effect of changes in the collector current. The collector current i c Specifically refers to the total current flowing through the collector of the IGBT and its parasitic inductance, and its dynamic characteristics are directly related to the energy transfer process of the collector.

[0050] like Figure 6 As shown, the gate voltage u during IGBT turn-on... GE and collector current i c The variation law of the collector current i is closely related to the above-mentioned coupling mechanism and can be divided into three stages. During the turn-on delay process (t0~t1), the collector current i c The gate voltage u has not yet risen. GE Under the influence of the gate drive circuit, and affected by the RC charging and discharging characteristics of the gate parasitic inductance and gate emitter capacitance, the voltage rises exponentially from the initial value to the threshold voltage. (Enter i) c During the Δt1 stage, which rises from 0 to the peak, as i c Rapid rise, first emitter parasitic inductance L s,E1 The induced electromotive force on the grid is superimposed with the gate drive voltage, causing u GE The rate of increase accelerates, and at time t1 in the figure, u GE The inflection point of the rate of increase occurs before the rate decreases due to the influence of the FWD reverse recovery current, and then increases due to the dominance of the IGBT forward current. If i... c The changing coupling effect, u GE It should rise to the steady-state value u along the dashed line trajectory ① in the figure. GE . in i c During the Δt2 stage from the peak value to the steady-state value, as ic Decrease, L s,E1 The induced electromotive force on it reverses, causing u GE It shows a downward trend, i in the figure c There is a delay (Δtd) between the peak value and the time when it drops to the steady state value, because i c The inherent phase delay measured using Rogowski coils is a time offset introduced by the measurement system.

[0051] Of the three stages mentioned above, the stage in which the collector current rises from 0 to its peak value (corresponding to...) Figure 6 The Δt1 stage in the middle is the extraction of the common-emitter parasitic inductance L. s,E1 The key period for characteristic information. This stage is the commutation transition period between the IGBT and the FWD chip. During the commutation transition period, the forward conduction current of the IGBT and the reverse recovery current of the FWD chip dynamically superimpose over time, realizing the transfer of load current from the FWD chip to the IGBT. As the IGBT gradually turns on, its forward conduction current i c The voltage rises rapidly, and the FWD chip, due to the reverse voltage, begins to turn off, its reverse recovery current i F The current gradually increases to its peak value and then gradually decreases until the forward current of the IGBT is sufficient to carry the entire load current. At this point, the reverse recovery current of the FWD chip drops to zero, and the commutation process is complete. This current superposition phenomenon originates from the energy freewheeling characteristic of inductive loads. The current in the load inductor cannot change abruptly. During the initial IGBT turn-on phase, the FWD remains in the on state to maintain current continuity until the forward current of the IGBT is sufficient to carry the entire load current, at which point the FWD is completely turned off. Therefore, the current waveform within the Δt1 stage is actually i c with i F The dynamic synthesis results, accompanied by strong collector-gate circuit coupling, provide a basis for extracting L s,E1 Feature information provides key scenarios.

[0052] During the commutation transition period, gate voltage and collector current waveforms are synchronously acquired using high-precision measurement equipment. The acquisition must meet the following conditions: a time resolution of at least 10 ns to capture waveform details on a microsecond timescale; a voltage measurement range covering -15V to +20V (adapting to the typical range of the gate drive signal); and current measurement compatible with peak currents of several thousand amperes and a rate of change of several thousand amperes per microsecond (achieved using a Rogowski coil or a high-frequency current sensor). The acquired gate voltage waveform will exhibit a characteristic inflection point (corresponding to...). Figure 6 (at time t1 in the equation), the inflection point is i c The rapid changes triggered L s,E1 The induced electromotive force on the gate begins to significantly affect the indicator of the gate voltage; while i c The rising slope di of the waveform c / dt directly reflects the intensity of dynamic changes in the collector circuit and is used to calculate L. s,E1 The core parameter is obtained by performing piecewise fitting and differentiation on the waveform data during this stage. The inductance value of the common-emitter parasitic inductance can then be derived.

[0053] In another implementation, during the IGBT turn-on process, a high-frequency voltage probe is connected between the gate pin and the auxiliary emitter pin of the IGBT module to acquire the gate voltage waveform; a high-frequency current sensor is connected in series in the collector circuit to acquire the collector current waveform. The acquisition period is selected from the entire process of the IGBT gate voltage rising from the threshold voltage to the steady-state voltage, covering the stage of the collector current rising from 0 to the peak value and then falling to the steady state.

[0054] Unlike acquisition methods based on the commutation transition period, this method uses an isolated synchronous triggering device to synchronously record waveforms using the rising edge of the IGBT gate drive signal as the trigger reference for voltage probes and current sensors. Specifically, voltage measurement employs a differential probe to eliminate common-mode interference, while current measurement uses a Schottky diode bridge sensor with a bandwidth ≥1GHz to capture the transient coupling details of the gate and collector currents. This eliminates the need to distinguish between the superposition period of the FWD chip's reverse recovery current and the IGBT's forward current, directly acquiring the complete voltage and current dynamic response during the turn-on process.

[0055] Step 520: Determine the gate voltage change based on the gate voltage waveform, and determine the collector current change rate based on the collector current waveform.

[0056] After obtaining the gate voltage waveform and collector current waveform during the IGBT turn-on process, the waveforms are processed as follows to calculate relevant parameters: Calculating the common-emitter parasitic inductance L inside the IGBT device based on transient waveform. s,E1 During the process, the processing of the gate voltage waveform focuses on the key period corresponding to the reverse recovery process of the FWD chip. During this period, the reverse recovery current of the FWD chip and the forward conduction current of the IGBT are dynamically superimposed, and the collector current changes drastically. This is the core region for extracting the common-emitter parasitic inductive coupling characteristics.

[0057] Specifically, in the gate voltage waveform, the dynamic characteristic nodes of the reverse recovery current of the FWD chip are first determined: the moment when the reverse recovery current begins to decrease is taken as the start time, and the gate voltage value at that moment is recorded synchronously; the moment when the reverse recovery current decays to 0 is taken as the end time, and the gate voltage value at that moment is recorded. The difference between the gate voltages at these two moments is the gate voltage change Δu corresponding to the FWD reverse recovery process. GE .

[0058] The physical nature of the gate voltage change originates from the common-emitter parasitic inductance L s,E1 Induced electromotive force effect: During the reverse recovery phase of FWD, the collector current i c rapid changes di c / dt via L s,E1 Generate induced voltage The induced voltage is superimposed on the gate drive signal, causing a characteristic shift in the gate voltage waveform, and Δu GE This direct manifestation of coupling effect provides a basis for subsequent calculations of L. s,E1 Key measured parameters are provided.

[0059] Calculating the common-emitter parasitic inductance L of an IGBT device based on transient waveforms s,E1 When processing the collector current waveform, the focus should be on the entire phase from 0 to its peak value. During this phase, the reverse recovery current of the FWD chip and the forward conduction current of the IGBT are dynamically superimposed, and the slope change of the current-time curve directly reflects the switching of the dominant relationship between the two currents.

[0060] First, extract the collector current i. c The complete time curve from 0 to the peak has a slope di c The variation characteristics of / dt are the core basis for interval division: the absolute value of the curve slope in the reverse recovery current dominated interval shows a decreasing trend. Because the carrier extraction speed is fast during reverse recovery of the FWD chip, the current rise slope changes rapidly (such as a steep increase followed by a rapid slowdown). In this stage, the contribution of the freewheeling diode reverse recovery current to the collector current is greater than that of the IGBT forward conduction current. The curve slope in the IGBT forward current dominated interval shows an increasing trend. Because the current rise is mainly determined by the conduction characteristics controlled by the IGBT gate voltage, the slope change is relatively gentle (approaching a stable linear increase). In this stage, the contribution of the IGBT forward conduction current to the collector current is greater than that of the freewheeling diode reverse recovery current.

[0061] After dividing the intervals based on the aforementioned slope characteristics, the current-time curves of the two intervals are differentiated: the curve of the interval dominated by reverse recovery current is differentiated to obtain the rate of change of current di within that interval. c1 / dt; Differentiating the curve of the IGBT forward current-dominated region yields the corresponding current change rate di. c2 / dt. These two rate-of-change parameters reflect the collector dynamic characteristics in different current-dominated stages. Specifically, the current rate of change in the reverse recovery current-dominated range (e.g., 4.2kA / μs) mainly reflects the current mutation characteristics caused by the rapid extraction of charge carriers during the reverse recovery process of the FWD chip. In this stage, because the FWD reverse recovery current dominates, the collector current changes drastically due to the influence of the internal charge carrier recombination rate, corresponding to the rapid fluctuation of the induced electromotive force on the parasitic inductance, and the resulting voltage spikes and electromagnetic interference risks. On the other hand, the current rate of change in the IGBT forward current-dominated range (e.g., 1.8kA / μs) reflects the characteristics of the IGBT channel gradually forming and the forward conduction current steadily increasing under the control of the gate voltage. In this stage, the current change is mainly modulated by the charging rate of the gate drive signal and the IGBT on-resistance. The collector exhibits a relatively smooth dynamic response, and the influence of parasitic parameters tends to be more stable. These two rates of change together outline the complete dynamic transition process of the collector from FWD-dominated to IGBT-dominated during the commutation transition period.

[0062] When calculating the collector current change rate, a weighted calculation method is used to account for the different effects of reverse recovery current and IGBT forward current. Specifically, based on the pre-defined reverse recovery current-dominated and IGBT forward current-dominated intervals, the ratio of the duration of each interval to the total stage duration is first calculated: the ratio of the duration of the reverse recovery current-dominated interval to the total stage duration is the first ratio, and the ratio of the duration of the IGBT forward current-dominated interval to the total stage duration is the second ratio, with the sum of the first and second ratios being 1. Subsequently, the current change rate of the reverse recovery current-dominated interval (obtained by differentiating the interval curve) is multiplied by the first ratio to obtain the first weighted component; the current change rate of the IGBT forward current-dominated interval (obtained by differentiating the interval curve) is multiplied by the second ratio to obtain the second weighted component. Finally, the collector current change rate of the total stage is determined by adding the first and second weighted components.

[0063] This weighted calculation method fully considers the contribution weight of the two intervals in the overall stage, which is consistent with the dynamic superposition characteristics of the reverse recovery current and the IGBT forward current in the actual commutation process. It provides a more accurate current change rate parameter for subsequent calculation of common emitter parasitic inductance, and improves the consistency between the calculation results and the actual parasitic characteristics of the device.

[0064] In another implementation, for the gate voltage change, the period from the threshold voltage to 90% of the steady-state voltage of the IGBT is selected. The gate voltage values ​​at the beginning and end of this period are recorded, and the difference between the two is the gate voltage change, independent of the FWD reverse recovery current characteristic moment. For the collector current change rate, the curve segment from the 10% peak value to the 90% peak value of the collector current is extracted, and the entire curve segment is linearly fitted. The slope of the fitted line is used as the collector current change rate, without distinguishing between the reverse recovery current and IGBT forward current dominant regions, directly using the average change rate of the entire region.

[0065] Step 530: Calculate the inductance value of the first emitter parasitic inductor in the emitter parasitic inductor circuit based on the gate voltage change and the collector current change rate.

[0066] During the IGBT turn-on process, by combining the aforementioned processing of the gate voltage waveform and collector current waveform, the gate voltage change Δu corresponding to the reverse recovery process of the FWD chip is obtained. GE And the rate of change of current di during the total phase of the collector current rising from 0 to its peak value. c / dt (obtained by weighted calculation of the reverse recovery current-dominated region and the IGBT forward current-dominated region). Based on the coupling relationship between the gate circuit and the collector circuit, neglecting the gate current change rate di... G Under the approximate condition of / dt influence, the parasitic inductance L of the first emitter s,E1 The inductance value can be calculated using the following formula: This calculation method directly utilizes the ratio of the measured voltage change to the current change rate during the transient process, reflecting the inductive effect of the common-emitter parasitic inductance on the gate voltage when the collector current changes. It provides a simple and effective calculation path for quantifying the common parasitic inductance of the gate circuit and collector inside the IGBT device.

[0067] In another implementation, the period during the IGBT turn-on process during which the gate voltage rises from the initial threshold voltage to a stable value is selected, and the total change in gate voltage during this period is recorded. The complete curve of the collector current rising from 0 to the steady-state value is extracted, and the average current change rate is obtained by performing an overall differential operation on the curve. Ignoring the segmented effect of the FWD reverse recovery process, the ratio of the total change in gate voltage to the average current change rate is directly used as the inductance value of the first emitter parasitic inductance.

[0068] For example, during the turn-on process of an IGBT, the commutation transition period from 0 to peak collector current is selected for analysis. During this stage, the reverse recovery current (FWD) and the IGBT forward current overlap. By acquiring the gate voltage waveform using a high-frequency voltage probe, the gate voltage is determined to be 5.2V at the moment the FWD reverse recovery current begins to decrease (starting moment) and 8.7V at the moment the reverse recovery current drops to 0 (ending moment), resulting in a gate voltage change of 3.5V. Simultaneously, the collector current waveform is acquired, and the current-time curve from 0 to peak value is extracted. Based on the slope change characteristics, intervals are divided: the reverse recovery current-dominated interval lasts 120ns, and the rate of change after curve differentiation is 4.2kA / μs; the IGBT forward current-dominated interval lasts 280ns, and the rate of change after curve differentiation is 1.8kA / μs. Calculations show that the first proportion is 120ns / (120ns+280ns)=0.3, and the second proportion is 0.7. Therefore, the first weighted component is 4.2kA / μs×0.3=1.26kA / μs, and the second weighted component is 1.8kA / μs×0.7=1.26kA / μs. The collector current change rate is the sum of the two, 2.52kA / μs. Finally, according to the formula... The inductance of the parasitic inductance of the first emitter was calculated to be 3.5V / (2.52kA / μs) = 1.39nH.

[0069] In summary, this application provides a method for accurately calculating the common-emitter parasitic inductance by combining the equivalent circuit model of the IGBT with measured waveform analysis. Its core advantages lie in: focusing on the dynamic characteristics of the IGBT and FWD commutation transition period, separating and independently quantifying the first emitter parasitic inductance (as a common path for the gate and collector circuits) in the emitter parasitic inductance network from the overall parasitic parameters, thus overcoming the limitation of traditional methods that treat parasitic inductance as a lumped parameter; and dividing the waveform into a reverse recovery current-dominated region and an IGBT forward current-dominated region based on the slope characteristics of the current change rate. This method achieves a refined processing of the complex electromagnetic coupling effect when two currents are superimposed. Compared with traditional averaging methods, it can more accurately reflect the influence of parasitic inductance in different physical processes. It directly extracts key parameters based on measured waveforms, avoiding errors caused by relying on preset values ​​of device internal structural parameters. For example, by accurately identifying the start and end points of the FWD reverse recovery current, the gate voltage change is determined, ensuring a strict correspondence with the collector current change. By weighting the current change rate in different intervals, it takes into account the combined influence of the FWD reverse recovery stage and the IGBT forward conduction stage on the parasitic inductance, making the calculation results closer to actual operating conditions.

[0070] It is understood that, in order to achieve the functions in the above embodiments, the computer device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0071] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0072] In a typical configuration, the device includes one or more processors (CPUs), memory, and a bus. The device may also include input / output interfaces, network interfaces, etc.

[0073] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM, and memory includes at least one memory chip. Memory is an example of computer-readable media.

[0074] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0075] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0076] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0077] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An equivalent circuit model for an IGBT, characterized in that, include: The DC-side branch includes a DC voltage source and a capacitor, wherein the positive terminal of the DC voltage source is connected to the positive terminal of the capacitor, and the negative terminal of the DC voltage source is connected to the negative terminal of the capacitor. The load-side branch includes a load inductor and a load parasitic inductor, with one end of the load parasitic inductor connected to the load inductor and the other end connected to the positive terminal of the DC-side branch; The IGBT branch includes an IGBT and an IGBT parasitic inductance network. The IGBT parasitic inductance network includes a gate parasitic inductance circuit, a collector parasitic inductance, and an emitter parasitic inductance circuit. The gate parasitic inductance circuit is connected between the emitter parasitic inductance circuit and the IGBT gate. The collector parasitic inductance is connected between the IGBT collector and the load inductance. The emitter parasitic inductance circuit is connected between the IGBT emitter and the negative terminal of the DC-side branch. The freewheeling branch includes a freewheeling diode (FWD) chip and a freewheeling parasitic inductor circuit. The cathode of the FWD chip is connected to one end of the freewheeling parasitic inductor circuit, and the anode of the FWD chip is connected to the connection path between the load inductor and the load parasitic inductor. The other end of the freewheeling parasitic inductor circuit is connected to the connection path between the load-side branch and the IGBT branch.

2. The IGBT equivalent circuit model according to claim 1, characterized in that, The IGBT branch further includes a gate driving circuit, which includes an on-circuit and a off-circuit. The on-circuit and the off-circuit are connected in parallel. The on-circuit consists of an on-power supply and an on-resistor connected in series. The off-circuit consists of an off-power supply and a off-resistor connected in series. The output terminal of the gate driving circuit is connected to the gate parasitic inductance circuit, and the input terminal of the gate driving circuit is connected to the emitter parasitic inductance circuit.

3. The IGBT equivalent circuit model according to claim 2, characterized in that, The gate parasitic inductance circuit includes a gate line parasitic inductance and a gate chip parasitic inductance. One end of the gate line parasitic inductance is connected to the output terminal of the gate drive circuit, and the other end is connected to the gate chip parasitic inductance. The other end of the gate chip parasitic inductance is connected to the gate of the IGBT.

4. The IGBT equivalent circuit model according to claim 2, characterized in that, The emitter parasitic inductor circuit includes a first emitter parasitic inductor, a second emitter parasitic inductor, and a third emitter parasitic inductor. One end of the first emitter parasitic inductor is connected to the emitter of the IGBT, and the other end is connected to the connection path between the second emitter parasitic inductor and the third emitter parasitic inductor. The other end of the second emitter parasitic inductor is connected to the input terminal of the gate drive circuit, and the other end of the third emitter parasitic inductor is connected to the negative terminal of the DC side branch.

5. The IGBT equivalent circuit model according to claim 1, characterized in that, The freewheeling parasitic inductor circuit includes a first parasitic inductor and a second parasitic inductor. One end of the first parasitic inductor is connected to the cathode of the FWD chip, and the other end is connected to one end of the second parasitic inductor. The other end of the second parasitic inductor is connected to the connection path between the load-side branch and the IGBT branch.

6. A method for calculating the common-emitter parasitic inductance of an IGBT, characterized in that, The method is applied to the IGBT equivalent circuit model as described in any one of claims 1-5. In the IGBT equivalent circuit model, the gate parasitic inductance circuit, the IGBT gate and emitter parasitic inductance circuit constitute the gate loop, and the collector parasitic inductance, the IGBT collector and emitter, the emitter parasitic inductance circuit, the load side branch and the DC side branch constitute the collector-emitter loop. The method includes: Obtain the gate voltage waveform and collector current waveform during the IGBT turn-on process in the equivalent circuit model of the IGBT. The gate voltage is the voltage between the gate pin and the emitter pin of the IGBT device under the combined action of the gate parasitic inductance circuit, the emitter parasitic inductance circuit and the IGBT gate-emitter capacitance. The collector current is the current flowing through the IGBT collector and the collector parasitic inductance. The gate voltage change is determined based on the gate voltage waveform, and the collector current change rate is determined based on the collector current waveform. The inductance value of the first emitter parasitic inductor in the emitter parasitic inductor circuit is calculated based on the gate voltage change and the collector current change rate, wherein the first emitter parasitic inductor is a common emitter parasitic inductor that exists simultaneously in the gate circuit and the collector-emitter circuit.

7. The method according to claim 6, characterized in that, Obtain the gate voltage waveform and collector current waveform during the IGBT turn-on process in the equivalent circuit model of the IGBT, including: During the IGBT turn-on process, the stage from which the collector current rises from 0 to its peak value is selected. This stage is the commutation transition period between the IGBT and the FWD chip, and during this stage, the reverse recovery current of the FWD chip and the forward conduction current of the IGBT are superimposed. The gate voltage waveform and collector current waveform are acquired during the aforementioned stage.

8. The method according to claim 7, characterized in that, Determining the gate voltage change based on the gate voltage waveform includes: In the gate voltage waveform, the gate voltage value at the start time and the gate voltage value at the end time are selected. The start time is the moment when the reverse recovery current of the FWD chip begins to decrease, and the end time is the moment when the reverse recovery current of the FWD chip drops to 0. The gate voltage change is determined based on the gate voltage value at the start time and the gate voltage value at the end time.

9. The method according to claim 7, characterized in that, Determining the collector current change rate based on the collector current waveform includes: From the collector current waveform, extract the current-time curve during the rise of the collector current from 0 to its peak value; Based on the slope variation characteristics of the current-time curve, the current-time curve is divided into a reverse recovery current-dominated region and an IGBT forward current-dominated region. Differentiate the curve for each interval to obtain the rate of change of current for each interval; The collector current change rate is determined based on the duration percentage and current change rate of each interval.

10. The method according to claim 9, characterized in that, The collector current change rate is determined based on the duration percentage and current change rate of each interval, including: In the reverse recovery current dominant region, the duration of the reverse recovery current dominant region is calculated as a first proportion of the total duration of the collector current rising from 0 to the peak value. A first weighted component is determined based on the current change rate of the reverse recovery current dominant region and the first proportion. In the IGBT forward current dominance region, calculate the second proportion of the duration of the IGBT forward current dominance region to the total duration of the collector current rising from 0 to the peak value, and determine the second weighted component based on the current change rate of the IGBT forward current dominance region and the second proportion. The collector current change rate is determined based on the first weighted component and the second weighted component.

11. The method according to claim 7, characterized in that, The inductance value of the first emitter parasitic inductance is calculated based on the gate voltage change and the collector current change rate, including: according to Calculate the parasitic inductance of the first emitter. The inductance value, where, The change in gate voltage. The rate of change of the collector current is given.

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