Domain controller PCIe signal layout wiring method, PCB and vehicle

Abstract

The invention discloses a domain controller PCIe (Peripheral Component Interconnect Express) signal layout and wiring method, a PCB (Printed Circuit Board) and a vehicle. The method comprises the following steps: setting a standard impedance value of a PCIe 3.0 wire to be 80 omega, and setting the length of the PCIe 3.0 wire to be within 3000 mils; wiring of PCIe3.0 routing is set to be inner-layer routing, the routing width is 5.6 mil, and the distance between differential lines is 5.4 mil. According to the method disclosed by the invention, the layout and the wiring of the PCIe3.0 routing are limited in various aspects, so that the layout and the wiring of the PCIe3.0 routing can well cope with a complicated vehicle-mounted environment, and effective transmission and processing of the PCIe3.0 signal are ensured. And the reliability of the corresponding PCB is improved. And furthermore, the reliability and the safety of the whole vehicle are improved. The invention is mainly used in the technical field of vehicles.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicles, in particular to a domain controller PCIe signal layout wiring method, a PCB board and a vehicle. BACKGROUND

[0002] The PCB layout and signal transmission of a high-level automatic driving (High-Autonomy Driving Domain, HAD) controller require high requirements. The HAD controller is composed of a high-performance system-on-chip (SoC) and its supporting circuit, and realizes faster communication between the processor and each expansion card through PCIe3.0 signals. PCIe3.0 (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices allocate exclusive channel bandwidth and do not share bus bandwidth.

[0003] With the development of automatic driving car technology, the importance of PCIe3.0 protocol in automotive electronic architecture is increasingly prominent. This is because the automatic driving system needs to process a large amount of data, including information from sensors, as well as high-precision maps and positioning data. In order to realize such complex data processing, high-performance computing platforms such as GPUs, FPGAs or ASICs need to be equipped inside the vehicle. These computing resources are usually connected through PCIe3.0 buses to provide the necessary bandwidth and low latency.

[0004] However, although PCIe3.0 technology theoretically supports 8GT / s data transmission rate, in actual application, the uniform layout and wiring of PCIe3.0 signals on the printed circuit board (PCB) will greatly affect the actual data transmission rate. Especially in a complex vehicle environment. Therefore, how to ensure the effective transmission and processing of PCIe3.0 signals in a complex vehicle environment and guarantee the stability, reliability and safety of the high-level automatic driving system is a technical problem that needs to be studied in the industry. SUMMARY

[0005] The present application provides a domain controller PCIe signal layout wiring method, a PCB board and a vehicle, which solves the problem of how to ensure the effective transmission and processing of PCIe3.0 signals in a complex vehicle environment, and at least provides a beneficial choice or creates conditions.

[0006] The application provides a domain controller PCIe signal layout wiring method, comprising the following steps: setting the standard impedance value of a PCIe 3.0 wiring to 80Ω, and setting the length of the PCIe 3.0 wiring to within 3000 mils; setting the wiring of the PCIe 3.0 wiring to inner layer wiring, and setting the wiring width to 5.6 mil and the differential line spacing to 5.4 mil.

[0007] Further, the domain controller PCIe signal layout wiring method further comprises the following step: placing an AC coupling capacitor related to the PCIe 3.0 wiring close to a receiving end.

[0008] Further, the domain controller PCIe signal layout wiring method further comprises the following step: placing an impedance resistor related to the PCIe 3.0 wiring close to a sending end, so as to reduce signal reflection.

[0009] Further, the domain controller PCIe signal layout wiring method further comprises the following step: placing a ground via hole symmetric to a signal via hole related to the PCIe 3.0 wiring close to the signal via hole, and the inner diameter of the ground via hole is less than or equal to 14 mil.

[0010] Further, when the inner diameter of the ground via hole is 8 mil, the spacing between the ground via hole and the signal ground via hole is 25 mil, and the spacing between adjacent shielding via holes is less than or equal to 360 mil.

[0011] Further, when the inner diameter of the shielding via hole is 8 mil, the spacing between adjacent shielding via holes is 30 mil.

[0012] Further, the length error between differential pairs related to the PCIe 3.0 wiring is controlled to be within 5 mil.

[0013] Further, the size of an AC coupling capacitor back pad is greater than the size of a capacitor pad, and the size of a signal via hole back pad is greater than the size of a via hole pad.

[0014] In another aspect, a PCB board is provided, and the PCB board has a circuit formed by the domain controller PCIe signal layout wiring method in any of the above technical solutions.

[0015] In another aspect, a vehicle is provided, and the vehicle is integrated with the PCB board in the above technical solutions.

[0016] The application has at least the following beneficial effects: the method of the application can well cope with the complex vehicle-mounted environment by limiting the layout and wiring of the PCIe3.0 wiring in all aspects, so as to ensure the effective transmission and processing of the PCIe3.0 signal. The reliability of the corresponding PCB board is improved. Further, the reliability and safety of the whole vehicle are improved. The application is mainly used in the field of vehicle technology. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the technical solutions of the application, and constitute a part of the specification, and are used together with the embodiments of the application to explain the technical solutions of the application, and do not constitute a limitation on the technical solutions of the application.

[0018] Figure 1 is a schematic diagram of eight step dimensions of the domain controller PCIe signal layout and wiring method; Figure 2 is a schematic diagram of differential return loss; Figure 3 is a schematic diagram of common mode return loss. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the application more clear, the application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and do not limit the application.

[0020] It should be noted that although the functional modules are divided in the system schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the system or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0021] The application relates to the technical field of vehicle control, in particular to a PCB layout and signal transmission optimization design method for a high-autonomy driving (HAD) controller.

[0022] However, although the PCIe3.0 technology theoretically supports a data transmission rate of 8GT / s, in actual application, there is no unified layout and wiring scheme of the PCIe3.0 signal on a printed circuit board (PCB). Existing engineering practices show that in a complex real vehicle running environment, especially under harsh conditions, due to the lack of standard specification PCB design guidance, signal integrity problems are prominent, the first-time board success rate is limited, and signal attenuation may occur, causing problems such as code interference, jitter, loss and the like, so that the equipment cannot work normally. Therefore, the application proposes an innovative PCB layout and signal transmission strategy, aiming to solve the above problems, ensure the effective transmission and processing of the PCIe3.0 signal in a complex vehicle environment, improve the first-time design success rate, and guarantee the stability and reliability of the high-autonomy driving system.

[0023] Before the embodiments of the application are described in detail, first, some terms and nouns involved in the embodiments of the application are explained, and the terms and nouns involved in the embodiments of the application are applicable to the following explanations.

[0024] PCIe3.0, PCIe3.0 (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth without sharing bus bandwidth.

[0025] In vehicle-related technologies, ensuring the effective transmission and processing of PCIe 3.0 signals in complex in-vehicle environments is a technical problem that urgently needs to be solved in the industry.

[0026] Please refer to Figure 1 , Figure 1 This is a schematic diagram illustrating the eight-step dimensions of the domain controller PCIe signal placement and routing method.

[0027] The layout and routing of PCIe signals for domain controllers needs to be considered from eight dimensions.

[0028] The first step involves defining the impedance requirements for PCIe 3.0 traces. This impedance requirement is strongly correlated with the trace width and differential line spacing. In this aspect, this application explicitly requires PCIe 3.0 traces to be designed with a standard impedance of 85Ω and strictly control the trace length to within 3000 mils. This invention uses the Polar SI9000 professional simulation tool to calculate the trace width that meets the 85-ohm impedance requirement based on the specific layer stack-up in actual application cases. In the described embodiment, regarding the actual routing of the PCIe 3.0 traces, this invention selects inner layer routing, and the calculated and optimized trace width is determined to be 5.6 mils, with a differential line spacing of 5.4 mils.

[0029] The second step involves determining the placement of the AC coupling capacitors. In this step, the placement of the AC coupling capacitors is determined for signal integrity optimization design of the high-speed serial link in the PCIe 3.0 routing. To maximize signal transmission quality and reduce noise interference, the AC coupling capacitors should be placed close to the receiving end. This placement strategy effectively achieves AC coupling, filters out DC components, and reduces mutual interference between signals, thereby improving the transmission performance and stability of PCIe 3.0 signals in the entire high-level autonomous driving system.

[0030] The third step involves defining the placement of the impedance matching resistor. In this step, specifically for signal integrity optimization design of PCIe 3.0 high-speed serial links, the placement of the impedance matching resistor is clearly defined. To minimize signal reflection, the impedance matching resistor should be placed at the transmitting end. This placement strategy can suppress noise and interference caused by reflections, thereby improving signal purity and transmission quality.

[0031] The fourth step involves specifying the location, size, and spacing of the accompanying ground vias. In this step, specifically for signal integrity optimization design of the PCIe 3.0 high-speed serial link, the placement, size, and spacing of the accompanying ground vias (GND vias) are clearly defined. To provide a low-impedance return path for the signal current, the GND vias must be symmetrically placed close to the signal vias, and their inner diameter should be less than 14 mil. For specific design details in the embodiments, this invention further specifies the inner diameter of the GND vias as 8 mil and the spacing between the GND vias and the signal vias as 25 mil. This design helps reduce signal loss and jitter during transmission, ensuring signal integrity.

[0032] The fifth step involves specifying the location, size, and spacing of the shielding vias. In this step, specifically for signal integrity optimization design of the PCIe 3.0 high-speed serial link, the size and spacing of the shielding vias (GND vias) are clearly defined. To isolate PCIe 3.0 signals from other signals, the gap between adjacent shielding vias (GND vias) should be 360 ​​mil. For specific design details in the embodiments, this invention further determines the inner diameter of the shielding vias (GND vias) to be 8 mil, and sets the gap between adjacent shielding vias (GND vias) to 30 mil. This design helps reduce the impact of electromagnetic interference, thereby improving the stability and reliability of the PCIe 3.0 signal.

[0033] The sixth step is to define the inter-pair length control error requirements. In this step, specifically for signal integrity optimization design of the PCIe 3.0 high-speed serial link, the inter-pair length control error is clearly defined. To reduce the relative delay of signals during transmission, the inter-pair length error must be controlled within 5 mils. For the design details of specific embodiments, this invention controls the inter-pair length error to 5 mils. This design helps improve the transmission quality and stability of PCIe 3.0 signals.

[0034] The seventh step is to define the anti-pad dimensions of the AC coupling capacitor and signal vias. In this step, specifically for signal integrity optimization design of the PCIe 3.0 high-speed serial link, the anti-pad dimensions of the AC coupling capacitor and signal vias are defined. To reduce impedance discontinuities in the PCIe 3.0 signal link, the size of the AC coupling capacitor anti-pad should be slightly larger than the capacitor pad size, and the size of the signal via anti-pad should be slightly larger than the via pad size. For the specific design details in the embodiment, this invention sets the size of the AC coupling capacitor anti-pad to be slightly larger than the capacitor pad size, and the size of the signal via anti-pad to be 13 mil larger than the via pad size. This design helps improve the transmission quality and stability of the PCIe 3.0 signal.

[0035] The eighth step involves conducting simulations and performing signal integrity analysis. This step requires rigorous signal integrity simulation analysis. The simulation process aims to comprehensively evaluate the quality performance of the PCIe 3.0 signal throughout the entire transmission path, including but not limited to simulations of return loss. By analyzing the simulation results, this invention can accurately determine whether the current PCIe 3.0 signal design meets the preset signal quality standards. If the simulation results show that the signal integrity does not meet the expected goals, the PCB design of the PCIe 3.0 signal is optimized and adjusted in a targeted manner based on the specific problems reported by the simulation results until the signal integrity simulation indicators meet the stringent requirements of PCIe signal transmission. This simulation-driven iterative optimization method for PCIe 3.0 signal PCB design not only ensures the consistency and reliability of signal transmission performance but also provides an efficient and feasible technical means for the design of data communication links based on PCIe 3.0 technology in automotive electronic devices.

[0036] Simulations can reveal the effect of the routing method used to lay up the domain controller's PCIe signals. (Referencing...) Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of differential return loss. Figure 3 This is a schematic diagram of common-mode return loss. From... Figure 2 and Figure 3 As can be seen, the differential return loss and common-mode return loss of the entire line are both controlled at a low level, and the entire line has good performance.

[0037] This invention imposes various restrictions on the layout and routing of PCIe 3.0 traces, enabling them to effectively cope with the complex automotive environment and ensuring efficient transmission and processing of PCIe 3.0 signals. This improves the reliability of the corresponding PCB board, and consequently, enhances the overall reliability and safety of the vehicle.

[0038] On the other hand, the present invention also provides a PCB board, wherein the PCB board integrates the circuitry formed by the domain controller PCIe signal layout and routing method described in any of the above specific embodiments.

[0039] On the other hand, the present invention also provides a vehicle that integrates the PCB board described in any of the above specific embodiments.

[0040] When the entire domain controller PCIe signal placement and routing method is executed automatically, another aspect of this application provides a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to implement the domain controller PCIe signal placement and routing method as described in any of the above specific embodiments.

[0041] This application also discloses a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. The processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the domain controller PCIe signal layout and routing method as described in any of the preceding embodiments.

[0042] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0043] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0044] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or units, and may be electrical, mechanical, or other forms.

[0045] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0046] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0047] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0048] Although the description of this application has been quite detailed and particularly focused on several of the described embodiments, it is not intended to limit itself to any of these details or embodiments or any particular embodiment. Rather, it should be considered as effectively covering the intended scope of this application by referring to the appended claims and taking into account the prior art, which provides for a broad possible interpretation of these claims. Furthermore, the foregoing description of this application with respect to embodiments foreseeable by the inventors is intended to provide a useful description, and non-substantial modifications to this application that have not yet been foreseen may still represent equivalent modifications.

[0049] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent is obtained first. Furthermore, the collection, use, and processing of this data comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user is obtained through pop-ups or redirection to confirmation pages. Only after obtaining the user's separate permission or consent is the necessary user-related data required for the proper functioning of these embodiments acquired.

Claims

1. A method for laying out and routing PCIe signals for a domain controller, characterized in that, include: Set the standard impedance of the PCIe 3.0 trace to 80Ω, and set the length of the PCIe 3.0 trace to within 3000 mils; set the PCIe 3.0 trace routing as inner layer trace, with a trace width of 5.6 mil and a differential line spacing of 5.4 mil.

2. The domain controller PCIe signal layout and routing method according to claim 1, characterized in that, Also includes: The AC coupling capacitors involved in the PCIe 3.0 traces should be placed near the receiving end.

3. The domain controller PCIe signal layout and routing method according to claim 1, characterized in that, Also includes: The impedance resistors involved in the PCIe 3.0 traces are placed close to the transmitting end to reduce signal reflection.

4. The domain controller PCIe signal layout and routing method according to claim 1, characterized in that, Also includes: The accompanying ground vias for the PCIe 3.0 traces are symmetrically placed near the signal vias, and the inner diameter of the accompanying ground vias is less than or equal to 14 mil.

5. The domain controller PCIe signal layout and routing method according to claim 4, characterized in that, When the inner diameter of the accompanying ground via is 8 mil, the spacing between the accompanying ground via and the signal ground via is 25 mil; the gap between adjacent shielding vias is less than or equal to 360 mil.

6. The domain controller PCIe signal layout and routing method according to claim 5, characterized in that, When the inner diameter of the shielding via is 8 mil, the gap between adjacent shielding vias is 30 mil.

7. The domain controller PCIe signal layout and routing method according to claim 1, characterized in that, The length error between differential pairs involving the PCIe 3.0 traces will be controlled within 5 mil.

8. The domain controller PCIe signal layout and routing method according to claim 1, characterized in that, The size of the anti-pad for AC coupling capacitors is larger than the size of the capacitor pads, and the size of the anti-pad for signal vias is larger than the size of the via pads.

9. A PCB board, characterized in that, The PCB board has the circuitry formed by the domain controller PCIe signal layout and routing method according to any one of claims 1 to 8.

10. A vehicle, characterized in that, The PCB board as described in claim 9 is integrated.

Images