Pcie parameter optimization training method and device, equipment, medium and product

Abstract

The application discloses a PCI E parameter optimization training method and device, equipment, medium and product, relates to the technical field of computer hardware, and the method comprises the following steps: acquiring test equalization parameters corresponding to each PCIE differential line channel, and determining a device working state according to a link bandwidth of a PCIE controller in a device enumeration stage; performing multi-round stress test training on all the test equalization parameters according to the device working state being a parameter test state, and obtaining optimal equalization parameters. The application aims to automatically optimize PCIE signal parameters to improve the optimization efficiency of the PCIE signal parameters.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to a PCIe parameter optimization training method, apparatus, device, medium and product. Background Technology

[0002] In computer hardware systems, the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) link plays a crucial role in data transmission. However, due to various factors such as link length, material properties, design layout, and PCB traces, PCIe signals are highly susceptible to attenuation or distortion during transmission. This not only leads to reduced or lost PCIe training bandwidth but can also, in severe cases, cause device loss, significantly impacting the compatibility and stability of PCIe devices on the board.

[0003] Currently, the main method for optimizing PCIe signals is to test the PCIe eye diagram using a high-bandwidth oscilloscope. If the eye diagram is poor, the PCIe EQ (Equalization) parameters are manually modified through the BIOS (Basic Input / Output System), and the eye diagram is tested again. This process is repeated until suitable EQ parameters are found to meet the eye diagram test requirements. If parameters that effectively improve signal quality cannot be found, hardware modifications and re-optimization of the PCIe routing are necessary. This traditional method has many drawbacks: First, the hardware cost is high, with high-end oscilloscopes being expensive, making it unaffordable for many small and medium-sized companies. Second, the analysis and optimization process for PCIe signal quality is extremely complex, requiring close cooperation between hardware engineers, BIOS engineers, and SI engineers, consuming a significant amount of manpower. Third, the number of EQ parameter combinations corresponding to PCIe differential lanes is enormous. For example, for a PCIe Ex16 slot, TxPreset has 16 settings, and RxPreset has 8 settings, theoretically allowing for as many as (16×8)^16 adjustable parameters, making manual testing almost impossible. Each EQ parameter verification involves BIOS compilation, updates, and entering the operating system to check bandwidth and test eye diagrams, which is a huge workload.

[0004] Therefore, how to automatically optimize PCIe signal parameters to improve the optimization efficiency is a technical problem that urgently needs to be solved.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide a PCIe parameter optimization training method, apparatus, device, medium, and product, which aims to automatically optimize PCIe signal parameters to improve the optimization efficiency of PCIe signal parameters.

[0007] To achieve the above objectives, this application proposes a PCIe parameter optimization training method, which includes:

[0008] Obtain the test equalization parameters corresponding to each PCIe differential line channel, and determine the device working status based on the link bandwidth of the PCIe controller during the device enumeration phase;

[0009] Based on the device's operating state as a parameter testing state, multiple rounds of stress testing training are performed on all the test equilibrium parameters to obtain the optimal equilibrium parameters.

[0010] In one embodiment, the step of determining the device operating state based on the link bandwidth of the PCIe controller during the device enumeration phase includes:

[0011] During the device enumeration phase, it checks whether the link bandwidth of the PCIe controller is at the preset maximum bandwidth threshold.

[0012] If the link bandwidth is the highest bandwidth threshold, then the device is determined to be in parameter testing state.

[0013] If the link bandwidth is not the maximum bandwidth threshold, then the device is determined to be in parameter adjustment mode.

[0014] In one embodiment, after the step of determining the device operating state based on the link bandwidth of the PCIe controller during the device enumeration phase, the PCIe parameter optimization training method includes:

[0015] In response to the device's operating state being in parameter adjustment mode, the automatic training module updates the test equilibrium parameters for the ongoing stress test training based on preset parameters.

[0016] In one embodiment, the step of performing multiple rounds of stress testing on all the test balancing parameters based on the device's operating state as a parameter testing state to obtain the optimal balancing parameters includes:

[0017] In response to the device operating state being parameter testing state, a first round of stress test training is performed on each of the test equalization parameters according to a preset first number of tests, and the number of consecutive test passes for each of the test equalization parameters in the first round of stress test training is recorded, and the test equalization parameters with a number of consecutive test passes greater than the number of stable training tests are taken as the better equalization parameters.

[0018] Multiple rounds of stress testing were performed based on all the aforementioned optimal equilibrium parameters to obtain the optimal equilibrium parameters.

[0019] In one embodiment, the step of performing multiple rounds of stress test training based on all the better equilibrium parameters to obtain the optimal equilibrium parameters includes:

[0020] The second round of stress testing is performed on each of the test equilibrium parameters according to the preset second test number, and the third round of stress testing is performed on the better equilibrium parameters that are stable in the second test number according to the preset third test number, so as to obtain multiple final training equilibrium parameters.

[0021] The optimal equilibrium parameters are determined based on all the final training equilibrium parameters.

[0022] In one embodiment, the step of determining the optimal equilibrium parameters based on all the final training equilibrium parameters includes:

[0023] The final training equalization parameters are transmitted to a preset equalization parameter list in chronological order to form an equalization parameter training list, and the official BIOS firmware is generated based on the equalization parameter training list.

[0024] Furthermore, to achieve the above objectives, this application also proposes a PC IE parameter optimization training device, the device comprising:

[0025] The acquisition module is used to acquire the test equalization parameters corresponding to each PCIe differential line channel, and determine the device working status based on the link bandwidth of the PCIe controller during the device enumeration phase.

[0026] The test training module is used to perform multiple rounds of stress test training on all the test equilibrium parameters based on the working state of the device as the parameter test state, so as to obtain the optimal equilibrium parameters.

[0027] Furthermore, to achieve the above objectives, this application also proposes a PC IE parameter optimization training device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the PC IE parameter optimization training method described above.

[0028] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the PC IE parameter optimization training method described above.

[0029] In addition, to achieve the above objectives, this application also proposes a computer product comprising a computer program, the computer program including computer program code means stored on a computer-readable medium or carrier wave, the computer program code means being configured to cause a computer or processor to execute the steps of the PCIE parameter optimization training method described above.

[0030] To address the problems of high cost, complex processes, and large parameter combinations in traditional PCIe signal optimization methods that make manual testing difficult, this application provides a PCIe parameter optimization training method that significantly improves the optimization efficiency of PCIe signal parameters through automation. Specifically, by acquiring the test equalization parameters corresponding to each PCIe differential line channel, the device's operating state can be quickly determined based on the link bandwidth of the PCIe controller during the device enumeration phase. When the device is in parameter testing mode, multiple rounds of stress testing training are performed on all test equalization parameters. Unlike traditional methods that rely on expensive oscilloscopes and manual parameter adjustments, this method automatically performs multiple rounds of testing, continuously filtering and optimizing parameters during the testing process to ultimately obtain the optimal equalization parameters. This not only avoids the high cost of high-end oscilloscopes and reduces the complex process of collaboration among engineers from multiple fields, but also significantly improves the optimization efficiency of PCIe signal parameters through automated multi-round stress testing training. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the first embodiment of the PCIE parameter optimization training method of this application;

[0032] Figure 2 This is a flowchart illustrating the second embodiment of the PCIE parameter optimization training method of this application;

[0033] Figure 3 This is a schematic diagram of the PCIE parameter optimization training device of this application;

[0034] Figure 4 This is a schematic diagram of the hardware operating environment involved in the device in this application;

[0035] Figure 5 This is a schematic diagram of the storage medium structure involved in the PCIE parameter optimization training method of this application.

[0036] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0037] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0038] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0039] In PCIe technology applications, PCIe links often suffer from signal attenuation or distortion due to factors such as length, materials, design, and PCB traces. This can lead to problems such as reduced PCIe training bandwidth, bandwidth loss, and even device failure. To improve the compatibility and stability of PCIe devices on the board and reduce the bit error rate, adjusting PCIe EQ parameters has become a key approach.

[0040] However, existing PCIe signal optimization solutions have many drawbacks: on the one hand, they rely on high-bandwidth oscilloscopes to test PCIe eye diagrams, and high-end oscilloscopes are expensive, making it difficult for small and medium-sized companies to afford the hardware costs; on the other hand, the PCIe signal quality analysis and optimization process is complex, requiring collaboration among hardware engineers, BIOS engineers, and SI engineers, resulting in high labor costs. Furthermore, the number of EQ parameter combinations corresponding to PCIe differential lanes is enormous. Taking a PCIe x16 slot as an example, theoretically, there are as many as (16×8)^16 adjustable parameters, making manual testing almost impossible. Each EQ parameter verification involves a significant amount of work, including BIOS compilation and updates, and entering the operating system to check bandwidth and test eye diagrams. These difficulties make PCIe device compatibility and stability a thorny issue in board design, leading engineers to often prioritize speed reduction (such as switching to PCIe GEN2 or GEN1) rather than modifying EQ parameters when faced with such problems.

[0041] Therefore, how to automatically optimize PCIe signal parameters to improve the optimization efficiency is a technical problem that urgently needs to be solved.

[0042] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art.

[0043] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a device capable of performing the above functions, such as a PCIe parameter optimization training device (e.g., the domestic Phytium platform). The following description uses a PCIe parameter optimization training device as an example to illustrate this embodiment and the subsequent embodiments.

[0044] Based on this, embodiments of this application provide a PCIE parameter optimization training method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the PCIE parameter optimization training method of this application.

[0045] Reference Figure 1This application provides a PCIE parameter optimization training method. In the first embodiment of the PCIE parameter optimization training method, the PCIE parameter optimization training method includes steps S10 to S20.

[0046] Step S10: Obtain the test equalization parameters corresponding to each PCIe differential line channel, and determine the device working status based on the link bandwidth of the PCIe controller during the device enumeration phase.

[0047] In this embodiment, since the PCIe differential line channel is the critical path for data transmission, different PCIe differential line channels may differ due to factors such as hardware design and line layout. Therefore, it is necessary to obtain the test equalization parameters corresponding to each PCIe differential line channel to provide basic data for subsequent parameter optimization training. Next, the link bandwidth of the PCIe controller is detected during the device enumeration stage, so as to accurately obtain the device working status, thereby providing accurate and reliable judgment conditions for subsequent parameter optimization training.

[0048] It should be noted that PCIe differential line channels are the fundamental physical links for achieving high-speed data transmission. Each pair of PCIe differential line channels has its own corresponding initial EQ (Equalization) parameters, among which TxPreset (transmit preset) and RxPreset (receive preset) are important components of the initial EQ parameters.

[0049] TxPreset is responsible for adjusting the signal characteristics of the transmitting end, and it has 16 different setting options. These settings can change key parameters such as the amplitude, phase, and pre-emphasis of the transmitted signal to adapt to different transmission environments and requirements. For example, in long-distance transmission or situations where the signal is prone to attenuation, adjusting the settings of TxPreset can enhance the strength of the transmitted signal and its anti-interference capability.

[0050] RxPreset focuses on signal processing at the receiver and offers eight settings. Its function is to optimize the receiver's sampling, amplification, and equalization of the signal, ensuring accurate interpretation of the received signal. For example, when the signal is affected by noise during transmission, appropriate RxPreset settings can effectively suppress noise and improve the quality of the received signal.

[0051] In a specific embodiment, taking a PCIe x16 slot as an example, it contains 16 pairs of differential lanes. Since each pair of lanes can independently set TxPreset and RxPreset, theoretically, the number of adjustable PCIe parameters corresponding to a PCIe x16 slot is extremely large. The specific calculation method is as follows: for each pair of lanes, there are 16 possible TxPreset settings and 8 possible RxPreset settings, so there are 16 × 8 possible combinations for each pair of lanes. Since a PCIe x16 slot has 16 pairs of lanes, according to the principle of permutation and combination, the total number of adjustable parameter combinations is (16 × 8)^16, that is, (16 * 8)^16.

[0052] Furthermore, in another embodiment, step S10 above: obtaining the test equalization parameters corresponding to each PCIe differential line channel may also include steps 100 to 900.

[0053] Step 100: Obtain historical test data from previous PCIe differential line channel tests. This historical test data includes at least the TxPreset (i.e., the preset value of the transmitting end) and RxPreset (i.e., the preset value of the receiving end) of each pair of PCIe differential line lanes, as well as the corresponding test results (i.e., the number of times the test passed).

[0054] Step 200: Determine the EQ parameter set for each PCIe differential line channel. This EQ parameter set includes multiple initial EQ parameters. Specifically, taking a PCIe X16 slot as an example, each PCIe differential line channel has 16 TxPreset settings and 8 RxPreset settings, meaning each PCIe differential line channel has n = 16 × 8 initial EQ parameters.

[0055] Step 300: Initialize the channel number lane_index of the current differential line channel (i.e., the PCIe differential line channel to be processed) to 0, and pre-set the test pass threshold (i.e., the preset test pass threshold); Next, determine the search range of the current differential line channel, with its starting index start=0 and ending index end=n-1.

[0056] Step 400: Calculate the intermediate index mid = (start + end) / / 2, and find the target EQ parameter specified by the intermediate index from the EQ parameter set of the current differential line channel.

[0057] Step 500: Check if there are test results for the target EQ parameter in the historical test data.

[0058] Step 600: If a test result (i.e., the number of times the test passes) exists for the target EQ parameter, based on the determination that the number of times the test passes ≥ the preset test passing threshold, record the target EQ parameter as a possible test equalization parameter for the current differential line channel, and update start = mid + 1. Return to execute step 400 to check whether there are other better initial EQ parameters that meet the conditions in the second half interval (mid, end) of the current parameter set (i.e., the EQ parameter set of the current differential line channel), until all test EQ parameters that meet the condition of the number of times the test passes ≤ the preset test passing threshold are found in the current parameter set.

[0059] Step 700: If a test result for the target EQ parameter exists, based on the judgment result that the number of times the test passes is less than or equal to the preset test pass threshold, it can be determined that the target EQ parameter does not meet the requirements. Next, the search range is adjusted to [0, mid), and start = mid-1 is updated. Then, the process returns to step 400.

[0060] Step 800: If no test results exist for the target EQ parameter, perform actual PCIe differential line channel testing based on the target EQ parameter to obtain the number of times the target EQ parameter passes the test. After recording the target EQ parameter and its number of test passes into the historical test data, return to step 600.

[0061] Step 900: After completing the preprocessing of the EQ parameter set in the current differential line channel, update the channel number lane_index_c = lane_index + 1, and return to execute step 400 to perform data preprocessing on the EQ parameter set in the next PCIe differential line channel of the current differential line channel until lane_index_c > 16. Then, it is determined that the data preprocessing of all PCIe differential line channels is completed. Next, the test equalization parameters of all 16 pairs of lanes will be integrated to obtain the test equalization parameter set of the entire PCIe X16 slot. This test equalization parameter set includes several test equalization parameters that meet the preset test pass count requirements.

[0062] Step S20: Based on the device's working state as the parameter test state, perform multiple rounds of stress test training on all the test equalization parameters to obtain the optimal equalization parameters.

[0063] In this embodiment, after determining that the device is in parameter testing mode, multiple rounds of stress testing training are immediately performed on each test equalization parameter to obtain the optimal equalization parameters. Unlike traditional methods that rely on expensive oscilloscopes and manual parameter adjustments, this approach automatically performs multiple rounds of testing, continuously filtering and optimizing parameters during the testing process to ultimately obtain the optimal equalization parameters. This not only avoids the high costs associated with high-end oscilloscopes and reduces the complex process of collaboration among engineers from multiple fields, but also significantly improves the optimization efficiency of PCIe signal parameters through automated multi-round stress testing training.

[0064] In summary, addressing the problems of high cost, complex process, and large number of parameter combinations that make manual testing difficult in traditional PCIe signal optimization methods, this application provides a PCIe parameter optimization training method that significantly improves the optimization efficiency of PCIe signal parameters through automation. Specifically, by acquiring the test equalization parameters corresponding to each PCIe differential line channel, the device's operating state can be quickly determined based on the link bandwidth of the PCIe controller during the device enumeration phase. When the device is in the parameter testing state, multiple rounds of stress test training are performed on all test equalization parameters. Unlike traditional methods that rely on expensive oscilloscopes and manual parameter adjustments, this method automatically performs multiple rounds of testing, continuously filtering and optimizing parameters during the testing process to ultimately obtain the optimal equalization parameters. This not only avoids the high cost of high-end oscilloscopes and reduces the complex process of collaboration among engineers from multiple fields, but also significantly improves the optimization efficiency of PCIe signal parameters through automated multi-round stress test training.

[0065] Furthermore, based on the first embodiment of this application described above, a second embodiment of the PCIE parameter optimization training method of this application is proposed, referring to... Figure 2 The above step S10: Determining the device working status based on the link bandwidth of the PCIe controller during the device enumeration phase may also include the following implementation steps S101 to S103.

[0066] Step S101: During the device enumeration phase, check whether the link bandwidth of the PCIe controller is at the preset maximum bandwidth threshold.

[0067] In this embodiment, the link bandwidth of the PCIe controller is accurately detected during the device enumeration phase. Device enumeration is the process by which the computer platform identifies and locates each device connected to the PCIe bus. During this process, the computer platform communicates with the PCIe controller, reads the key indicator of the PCIe controller's link bandwidth, and compares this link bandwidth with a preset maximum bandwidth threshold. This preset maximum bandwidth threshold is set according to the standards and performance requirements of PCIe devices, representing the bandwidth range that the device should ideally achieve. By comparing the link bandwidth of the PCIe controller with the preset maximum bandwidth threshold, the current operating efficiency of the PCIe controller and the transmission capacity of the link can be preliminarily determined.

[0068] It should be noted that the preset maximum bandwidth threshold can be customized according to application requirements, and this application does not impose any restrictions here. For example, the preset maximum bandwidth threshold can be PCIE3.0 8GT / s or PCIE2.0 5GT / s.

[0069] Step S102: If the link bandwidth is the highest bandwidth threshold, then the device is determined to be in parameter testing state.

[0070] In this embodiment, if the link bandwidth of the PCIe controller is the preset maximum bandwidth threshold, the device is determined to be in parameter testing state. In this parameter testing state, multiple rounds of stress testing training are performed on the test equalization parameters corresponding to each pair of PCIe differential lines lanes so that the optimal equalization parameters can be obtained quickly and accurately, thereby improving the overall performance and stability of the PCIe device and ensuring efficient and accurate data transmission.

[0071] Step S103: If the link bandwidth is not the maximum bandwidth threshold, then the device is determined to be in parameter adjustment state.

[0072] In this embodiment, if the link bandwidth of the PCIe controller is detected to be outside the preset maximum bandwidth threshold, the device is determined to be in parameter adjustment mode. In this mode, a preset automatic parameter training module automatically adjusts the test equalization parameters corresponding to each PCIe differential line channel. Specifically, based on the degree to which the PCIe controller's link bandwidth deviates from the maximum bandwidth threshold, the settings of EQ parameters such as Tx Preset and Rx Preset are automatically adjusted, trying different parameter combinations to improve signal quality and increase link bandwidth. Through continuous adjustment and optimization, the link bandwidth gradually approaches or reaches the preset maximum bandwidth threshold, creating conditions for stable device operation and efficient data transmission.

[0073] Furthermore, in some other feasible embodiments, in step S10 above: determining the device operating state based on the link bandwidth of the PCIE controller during the device enumeration phase, the subsequent PCIE parameter optimization training method may also include the following implementation step A10.

[0074] Step A10: In response to the device's operating state being in parameter adjustment state, the test equilibrium parameters for the ongoing stress test training are updated according to the preset parameter automatic training module.

[0075] In this embodiment, based on the device's operating status and response to parameter adjustment, a preset automatic parameter training module is immediately invoked to update the test equalizer parameters currently undergoing stress testing training as the optimization target. Specifically, the automatic parameter training module updates the test equalizer parameters currently undergoing stress testing training according to its built-in automatic parameter training algorithm. The update process set in this application is not random, but fully considers the characteristics of the PCIe link, feedback data obtained from previous tests, and preset optimization goals. For example, based on issues such as signal attenuation and bit error rate found in previous tests, the module will specifically adjust parameter settings such as Tx Preset and Rx Preset. If severe signal attenuation is found during transmission in the test, the automatic parameter training module may appropriately increase the pre-emphasis value of the signal in Tx Preset to enhance the signal transmission strength; at the same time, based on the signal quality at the receiving end, the relevant parameters of Rx Preset are adjusted to optimize the receiving end's signal processing capability. In this way, the test equalizer parameters are continuously updated in the hope of finding an optimal set of parameters, thereby improving PCIe signal quality, increasing link bandwidth, and enabling the device to achieve a better operating state.

[0076] Furthermore, in some feasible embodiments, the above step S20: performing multiple rounds of stress test training on all the test equalization parameters based on the device working state as the parameter test state to obtain the optimal equalization parameters may also include the following implementation steps S201 to S202.

[0077] Step S201: In response to the device operating state being parameter testing state, perform a first round of stress test training on each of the test equalization parameters according to a preset first number of tests, and record the number of consecutive test passes for each of the test equalization parameters during the first round of stress test training, and take the test equalization parameters whose number of consecutive test passes is greater than the number of stable training passes as the better equalization parameters.

[0078] In this embodiment, based on the device's operating state and the response to the parameter test state, a first round of stress test training is conducted on each of the test equalization parameters according to a preset first test number. The preset first test number is set based on a comprehensive consideration of the characteristics of PCIe devices and actual application scenarios, with the aim of comprehensively and accurately evaluating the performance of the test equalization parameters through a sufficient number of tests. During each test, the computer platform strictly monitors the signal transmission of the PCIe link to determine whether it meets the requirements for stable transmission. If the PCIe link can stably transmit data in a test without any abnormalities such as speed reduction, bandwidth loss, or device loss, then the test is considered passed. The computer platform records the number of consecutive pass times for each test equalization parameter during the first round of stress test training in real time. When the number of consecutive pass times for a certain test equalization parameter is greater than the preset number of stable training times, it indicates that the parameter exhibits good stability and adaptability under the current test conditions, and the computer platform will select it as a better equalization parameter.

[0079] It should be noted that the preset number of first tests can be 50, or it can be customized according to application requirements; this application does not impose any restrictions. The number of stable training iterations can also be customized according to user needs, and it can be 50, or it can be customized according to user needs; this application does not impose any restrictions.

[0080] Step S202: Perform multiple rounds of stress test training based on all the aforementioned optimal equilibrium parameters to obtain the optimal equilibrium parameters.

[0081] In this embodiment, multiple rounds of stress testing are performed based on all the better equalization parameters to obtain the optimal equalization parameters. In other words, through multiple rounds of stable stress testing, various complex real-world working scenarios can be simulated, comprehensively and thoroughly examining the performance of the better equalization parameters under different conditions. As the testing rounds progress, equalization parameters that perform better in terms of signal stability, bandwidth maintenance, and anti-interference will gradually emerge. This avoids the limitations of determining parameters based on a single test or simple conditions, effectively eliminating the interference of accidental factors. The selected optimal equalization parameters can best meet the operational requirements of PCIe devices. The final optimal equalization parameters can significantly improve PCIe signal quality, reduce signal attenuation and bit error rate, enhance the stability of the PCIe link, reduce bandwidth reduction and device loss caused by signal problems, and greatly improve the compatibility and overall performance of PCIe devices, providing a solid guarantee for stable system operation and efficient data transmission.

[0082] Furthermore, in some other feasible embodiments, the above step S202: performing multiple rounds of stress test training based on all the better equilibrium parameters to obtain the optimal equilibrium parameters may also include the following implementation steps S2021 to S2022.

[0083] Step S2021: Perform a second round of stress test training on each of the test equilibrium parameters according to the preset second test number, and perform a third round of stress test on the better equilibrium parameters that are stable after the second test number according to the preset third test number, to obtain multiple final training equilibrium parameters.

[0084] In this embodiment, a second round of stress testing is performed on each test equalization parameter according to a preset second number of tests. This second number of tests can be 200 times, or it can be customized according to user needs. This application does not impose any restrictions here. Next, a third round of stress testing is performed on the better equalization parameter (i.e., the final candidate equalization parameter) that has passed 200 consecutive tests and is stable, according to a preset third number of tests (i.e., 1000 times, or it can be customized according to user needs. This application does not impose any restrictions here). Thus, each final candidate equalization parameter that has passed 1000 consecutive tests and is stable can be used as a final training equalization parameter. After all final candidate equalization parameters have been enumerated, all final training equalization parameters are output, which can significantly improve the accuracy and reliability of PCIE signal parameter optimization.

[0085] Step S2022: Determine the optimal equilibrium parameters based on all the final training equilibrium parameters.

[0086] In this embodiment, the optimal equalization parameters can be accurately obtained based on all the final training equalization parameters, which can greatly improve the PCIe signal quality, reduce the bit error rate, ensure the stable operation of the PCIe link, effectively improve the compatibility and stability of PCIe devices, avoid problems such as speed reduction, bandwidth loss, and device loss, and strongly guarantee the system to transmit data efficiently and stably.

[0087] In a specific embodiment, an automatic training module for PCIe EQ parameters is developed in the UEFI BIOS. This module automatically modifies the PCIe EQ parameters in the Phytium PBF and then performs stability stress tests on PCIe devices for each EQ parameter. For example, in the first round of parameter screening, each EQ parameter is tested 50 times; in the second round, each parameter is tested 200 times; and in the third round, each parameter is tested 1000 times. During the PCIe device enumeration process, the PCIe device link bandwidth is checked. During training, EQ parameters that cause speed reduction, bandwidth loss, or even device loss are eliminated, retaining parameters with stable PCIe link bandwidth, meaning parameters that can be trained stably within a preset number of tests. For example, the first screening identifies all PCIe EQ parameters that are stable for 50 consecutive tests, the second round identifies all PCIe EQ parameters that are stable for 200 consecutive tests, and so on. Simultaneously, the training process is recorded using a debug serial port, allowing monitoring of the PCIe device training status for each EQ parameter.

[0088] Furthermore, in some other feasible embodiments, the number of the optimal equalization parameters is at least one. In step S20 above: based on the device working state as the parameter test state, perform multiple rounds of stress test training on all the test equalization parameters to obtain the optimal equalization parameters. The subsequent PCIE parameter optimization training method may also include the following implementation step B10.

[0089] Step B10: Transmit the final training equalization parameters to the preset equalization parameter list in chronological order to form an equalization parameter training list, and generate the official BIOS firmware based on the equalization parameter training list.

[0090] In this embodiment, once all equalization parameters have been enumerated, the automatic training process of PCIe EQ parameters is considered complete. Next, the computer platform transmits each final trained equalization parameter to a preset equalization parameter list in chronological order, forming an equalization parameter training list. Then, based on preset evaluation criteria, the optimal equalization parameter is selected from the equalization parameter training list and sent to the BIOS as the final recommended configuration to generate the official BIOS firmware (i.e., the official BIOS version). This allows the computer platform to use this optimal EQ parameter configuration to initialize the PCIe link during subsequent device startup, ensuring that the link can operate with optimal performance.

[0091] It should be noted that the preset evaluation criterion is configured as the median value of the equalization parameters. This median value refers to the value in the middle of the range covered by the equalization parameter training list, serving as a benchmark for measuring and selecting the optimal equalization parameters. The determination of this median value depends on the range of equalization parameter values. If the range is continuous, it can be obtained by averaging the values ​​at both ends of the range; for example, if the range is from a to b, the median value is (a+b) / 2. If the values ​​are discrete, the value in the exact middle of all possible values ​​is selected. This is used as the preset evaluation criterion because it takes into account factors such as link stability, device compatibility, and parameter universality during the automatic training of PCIe EQ parameters. In the absence of a specific optimization direction or special requirements, it provides a reasonable and universal reference benchmark for selecting the optimal equalization parameters that adapt to most situations and enable the link to achieve best performance. This ensures that when the device is started up, the optimal equalization parameters selected based on this standard will enable the PCIe link to achieve optimal performance.

[0092] Furthermore, in another feasible embodiment, the PCIE parameter optimization training method may also include the following implementation steps 1 to 6.

[0093] Step 1. Power on the device and initialize it.

[0094] Step 2. During the UEFI BIOS PCIe device enumeration phase, check the link status (i.e., link bandwidth) of the PCIe controller. Is it the expected maximum bandwidth, such as PCIe x16 GEN3? If yes, update the test pass count and proceed to Step 3; otherwise, proceed to Step 4 and update the EQ parameters in pbf.

[0095] Step 3. Determine if a stable training run has been reached. If so, proceed to Step 4 and update the EQ parameters in pbf; otherwise, restart and continue with the PCIe device stability test.

[0096] Step 4. Have all EQ parameter combinations been enumerated? If yes, proceed to step 5; otherwise, update the EQ parameters in pbf and proceed to step 1.

[0097] Step 5. Complete the automatic training of PCIE EQ parameters, print the training results, such as outputting a list of all required EQ parameters and providing the optimal EQ parameters.

[0098] Step 6. Release the official BIOS using the trained optimal EQ parameters. If the company's hardware allows, test the PCIe eye diagram with an oscilloscope.

[0099] In summary, the PCIE parameter optimization training method proposed in this application effectively solves the problems of high hardware cost, complex implementation, and low efficiency in traditional PCIE signal optimization technology through a purely software-implemented UEFI firmware-level automatic EQ enumeration module. Its core technological advantages are: 1) Low cost: It eliminates the need for expensive hardware such as high-end oscilloscopes, relying entirely on software algorithms for parameter optimization, significantly reducing R&D costs; 2) Easy implementation: It requires no hardware modifications or collaboration among engineers from multiple fields, only a board environment needs to be set up to automatically complete training through software, ultimately outputting the optimal EQ parameters, greatly simplifying the operation process; 3) High efficiency: Based on UEFI firmware, it directly detects the PCIE link bandwidth during the device enumeration stage, combined with a binary parameter enumeration algorithm to dynamically eliminate invalid parameter combinations, significantly reducing the originally massive testing tasks. Taking the Phytium platform as an example, parameter verification can be completed in just 15 seconds each time it boots up. Combined with 50-1000 stability tests, it successfully improved the PCIE link stability of a customer's FPGA product from 50% to 100%, achieving stable operation of the entire link under the PCIE GEN3 standard. This method, through a deep integration of algorithm optimization and firmware-level detection, provides an efficient, economical, and easily scalable solution for PCIe device compatibility and signal quality optimization.

[0100] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the PCIE parameter optimization training method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0101] This application also provides a PCIE parameter optimization training device, which includes an acquisition module and a test training module. Please refer to [reference needed]. Figure 3 The PCIE parameter optimization training controller includes:

[0102] The acquisition module H01 is used to acquire the test equalization parameters corresponding to each PCIe differential line channel, and to determine the device working status based on the link bandwidth of the PCIe controller during the device enumeration phase.

[0103] The test training module H02 is used to perform multiple rounds of stress test training on all the test equilibrium parameters based on the device's working state as the parameter test state, so as to obtain the optimal equilibrium parameters.

[0104] Optionally, the acquisition module H01 may also include:

[0105] The detection unit is used to detect whether the link bandwidth of the PCIe controller is at the preset maximum bandwidth threshold during the device enumeration phase.

[0106] The parameter testing unit is used to determine that the device is in parameter testing state if the link bandwidth is the highest bandwidth threshold.

[0107] The parameter adjustment unit is used to determine that the device is in parameter adjustment state if the link bandwidth is not the maximum bandwidth threshold.

[0108] Optionally, the acquisition module H01 may also include:

[0109] The update unit is used to update the test equilibrium parameters that are undergoing stress test training according to the preset parameter automatic training module in response to the device's working state being in parameter adjustment state.

[0110] Optionally, the test training module H02 may also include:

[0111] The response unit is configured to respond to the device operating state being parameter test state, perform a first round of stress test training on each of the test equalization parameters according to a preset first number of tests, record the number of consecutive test passes for each of the test equalization parameters during the first round of stress test training, and take the test equalization parameters whose number of consecutive test passes is greater than the number of stable training passes as the better equalization parameters.

[0112] The testing unit is used to perform multiple rounds of stress test training based on all the aforementioned optimal equilibrium parameters to obtain the optimal equilibrium parameters.

[0113] Optionally, the test training module H02 may also include:

[0114] The multi-round testing unit is used to perform a second round of stress testing training on each of the test equilibrium parameters according to a preset second number of tests, and to perform a third round of stress testing on the better equilibrium parameters that are stable in the second round of tests according to a preset third number of tests, so as to obtain multiple final training equilibrium parameters.

[0115] The optimal equilibrium parameter determination unit is used to determine the optimal equilibrium parameters based on all the final training equilibrium parameters.

[0116] Optionally, the test training module H02 may also include:

[0117] The generation unit is used to transmit each of the final training equalization parameters to a preset equalization parameter list in chronological order to form an equalization parameter training list, and generate the official BIOS firmware based on the equalization parameter training list.

[0118] The PCIE parameter optimization training device provided in this application, employing the PCIE parameter optimization training method in the above embodiments, can solve the technical problem of poor PCIE parameter optimization training results. Compared with the prior art, the beneficial effects of the PCIE parameter optimization training device provided in this application are the same as those of the PCIE parameter optimization training method provided in the above embodiments, and other technical features in the PCIE parameter optimization training device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0119] This application provides a PCIE parameter optimization training device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the PCIE parameter optimization training method in the above embodiment 1.

[0120] The following is for reference. Figure 4 This document illustrates a structural schematic diagram of a PCIE parameter optimization training device suitable for implementing embodiments of this application. The PCIE parameter optimization training device in these embodiments may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 4 The PCIE parameter optimization training device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0121] like Figure 4As shown, the PCIe parameter optimization training device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the PCIe parameter optimization training device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following devices can be connected to I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the PCIe parameter optimization training device to communicate wirelessly or wiredly with other devices to exchange data. Although a PCIe parameter optimization training device with various devices is shown in the figure, it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0122] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0123] The PCIE parameter optimization training device provided in this application, employing the PCIE parameter optimization training method described in the above embodiments, can solve the technical problem of poor PCIE parameter optimization training results. Compared with the prior art, the beneficial effects of the PCIE parameter optimization training device provided in this application are the same as those of the PCIE parameter optimization training method provided in the above embodiments, and other technical features of this PCIE parameter optimization training device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0124] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0125] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0126] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the PCIE parameter optimization training method in the above embodiments.

[0127] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor devices, apparatuses, or components, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution apparatus, device, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0128] The aforementioned computer-readable storage medium may be included in the PCIe parameter optimization training device; or it may exist independently and not be assembled into the PCIe parameter optimization training device.

[0129] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the PCIe parameter optimization training device, cause the PCIe parameter optimization training device to:

[0130] Obtain the initial text data to be processed, wherein the initial text data includes the initial text format and processing format requirements;

[0131] The processing mode is determined based on the processing format requirements and the initial text format, wherein the processing mode includes a first processing mode that changes the text format and a second processing mode that does not change the text format;

[0132] When the processing mode is the first processing mode, the text is displayed according to the initial text format and the processing format requirements;

[0133] In the processing mode, which is the second processing mode, the text is displayed according to the initial text format.

[0134] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0135] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using dedicated hardware-based apparatus to perform the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0136] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0137] Reference Figure 5 , Figure 5 This is a schematic diagram of the storage medium structure involved in the PCIE parameter optimization training method of this application. The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program, which is an over-the-top tracing program) for executing the above-described PCIE parameter optimization training method, which can solve the technical problem of poor PCIE parameter optimization training effect. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the PCIE parameter optimization training method provided in the above embodiments, and will not be repeated here.

[0138] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the PCIE parameter optimization training method described above.

[0139] The computer program product provided in this application can solve the technical problem of poor performance in PCIE parameter optimization training. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the PCIE parameter optimization training method provided in the above embodiments, and will not be repeated here.

[0140] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A PCIE parameter optimization training method, characterized in that, The PCIE parameter optimization training method includes: Obtain the test equalization parameters corresponding to each PCIe differential line channel, and determine the device working state based on the link bandwidth of the PCIe controller during the device enumeration stage. Specifically, when the link bandwidth is a preset maximum bandwidth threshold, the device working state is determined to be a parameter test state, and when the link bandwidth is not the maximum bandwidth threshold, the device working state is determined to be a parameter adjustment state. Based on the device's operating state being a parameter testing state, multiple rounds of stress testing training are performed on all the test equilibrium parameters to obtain the optimal equilibrium parameters; The step of performing multiple rounds of stress testing on all the test equalization parameters based on the device's operating state as a parameter testing state to obtain the optimal equalization parameters includes: In response to the device's operating state being a parameter testing state, a first round of stress testing training is performed on each of the test equilibrium parameters according to a preset first number of tests, and the number of consecutive passes for each test equilibrium parameter in the first round of stress testing training is recorded. The test equilibrium parameter with a number of consecutive passes greater than the number of stable training tests is taken as the better equilibrium parameter. A second round of stress testing training is performed on each of the test equilibrium parameters according to a preset second number of tests, and a third round of stress testing is performed on the better equilibrium parameter that is stable in the second round of tests according to a preset third number of tests, to obtain multiple final training equilibrium parameters. The optimal equilibrium parameter is determined based on all the final training equilibrium parameters. The PCIE parameter optimization training method further includes: when the device is in parameter adjustment mode, the preset automatic parameter training module automatically adjusts the equalization parameter combination of Tx Preset and Rx Preset parameters corresponding to each PCIE differential line channel according to the degree to which the link bandwidth deviates from the maximum bandwidth threshold, and adjusts the link bandwidth through different equalization parameter combinations so that the link bandwidth reaches the maximum bandwidth threshold.

2. The PCIE parameter optimization training method as described in claim 1, characterized in that, The step of determining the device operating status based on the link bandwidth of the PCIe controller during the device enumeration phase includes: During the device enumeration phase, it checks whether the link bandwidth of the PCIe controller is at the preset maximum bandwidth threshold. If the link bandwidth is the highest bandwidth threshold, then the device is determined to be in parameter testing state. If the link bandwidth is not the maximum bandwidth threshold, then the device is determined to be in parameter adjustment mode.

3. The PCIE parameter optimization training method as described in claim 2, characterized in that, Following the step of determining the device operating status based on the link bandwidth of the PCIe controller during the device enumeration phase, the PCIe parameter optimization training method includes: In response to the device's operating state being in parameter adjustment mode, the automatic training module updates the test equilibrium parameters for the ongoing stress test training based on preset parameters.

4. The PCIE parameter optimization training method as described in claim 1, characterized in that, The step of determining the optimal equilibrium parameters based on all the final training equilibrium parameters includes: The final training equalization parameters are transmitted to a preset equalization parameter list in chronological order to form an equalization parameter training list, and the official BIOS firmware is generated based on the equalization parameter training list.

5. A PCIE parameter optimization training device, characterized in that, The PCIE parameter optimization training device includes: The acquisition module is used to acquire the test equalization parameters corresponding to each PCIe differential line channel, and determine the device working state based on the link bandwidth of the PCIe controller during the device enumeration stage. Specifically, when the link bandwidth is a preset maximum bandwidth threshold, the device working state is determined to be the parameter test state, and when the link bandwidth is not the maximum bandwidth threshold, the device working state is determined to be the parameter adjustment state. The test training module is used to perform multiple rounds of stress test training on all the test equilibrium parameters based on the device's working state as the parameter test state, so as to obtain the optimal equilibrium parameters. The test training module is further configured to, in response to the device's operating state being a parameter test state, perform a first round of stress test training on each of the test equilibrium parameters according to a preset first number of tests, and record the number of consecutive pass tests for each of the test equilibrium parameters during the first round of stress test training. Test equilibrium parameters with a number of consecutive pass tests greater than the number of stable training tests are selected as the optimal equilibrium parameters. A second round of stress test training is then performed on each of the test equilibrium parameters according to a preset second number of tests, and a third round of stress test training is performed on the optimal equilibrium parameters that have remained stable for the second round of tests according to a preset third number of tests, resulting in multiple final training equilibrium parameters. The optimal equilibrium parameter is then determined based on all the final training equilibrium parameters. The PCIE parameter optimization training device is further configured to, when the device is in parameter adjustment mode, automatically adjust the equalization parameter combination of Tx Preset and Rx Preset parameters corresponding to each PCIE differential line channel based on the degree to which the link bandwidth deviates from the maximum bandwidth threshold using a preset automatic parameter training module, and adjust the link bandwidth through different equalization parameter combinations so that the link bandwidth reaches the maximum bandwidth threshold.

6. A PCIE parameter optimization training device, characterized in that, The PCIE parameter optimization training device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the PCIE parameter optimization training method as described in any one of claims 1 to 4.

7. A medium, said medium being a computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the PCIE parameter optimization training method as described in any one of claims 1 to 4.

8. A computer program product, the computer program product comprising a computer program, characterized in that, The computer program includes computer program code means stored on a computer-readable medium or carrier, the computer program code means being configured to cause a computer or processor to execute the steps of the PCIE parameter optimization training method as described in any one of claims 1 to 4.

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