Memory device and forming method thereof

Abstract

A cell design for power distribution in a CFET SRAM device is presented, the back side of the device being connected to the front side thereof using an intermediate band cell. A device includes an array of cells disposed on a substrate. The cell array includes a first array portion and a second array portion separated in a first direction in a top view of the device. The device also includes an intermediate band cell array disposed between the first array portion and the second array portion in the first direction. The intermediate belt unit array includes a plurality of intermediate belt units arranged in a second direction perpendicular to the first direction in a top view. Each intermediate band cell includes a via structure configured to pass a reference voltage signal from a back side of the substrate to a front side of the substrate. The embodiment of the invention also provides a memory device and a forming method thereof.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to providing a memory device and a method of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a substrate, and patterning the various layers of material by using photolithographic techniques to form circuit components and elements. As semiconductor devices proceed into nanometer technology nodes in the pursuit of higher device densities, better performance, and lower costs, challenges from both manufacturing and design have led to the development of a variety of three-dimensional designs, including, for example, metal oxide semiconductor field effect transistors (MOS-FET), field effect transistors (FET), fin field effect transistors (FinFET), gate-all-around (GAA) devices (nanowire / nanosheet), GAA devices configured as complementary field effect transistor (CFET) devices, and multi-bridge-channel field effect transistors (MBCFET) devices (nanosheet).

[0003] As integrated circuit (IC) technology progresses to smaller technology nodes, memory or storage cells (e.g., static random access memory cells) often incorporate peripheral cells in their design to improve device performance, where each storage cell can store one bit of data. In such examples, a power tap cell is implemented to facilitate the transmission of power throughout the array of storage cells. While existing designs of power tap cells generally meet their intended purpose, they are not entirely satisfactory in all respects. SUMMARY

[0004] According to one aspect of embodiments of the present application, a memory device is provided, including: a substrate, the substrate including a front side and a back side opposite the front side; a cell array disposed above the substrate, the cell array including a first array portion and a second array portion separated along a first direction in a top-down perspective view of the memory device, the first array portion and the second array portion each including a plurality of cells; and an intervening band cell array disposed between the first array portion and the second array portion along the first direction, the intervening band cell array including a plurality of intervening band cells arranged along a second direction perpendicular to the first direction in the top-down perspective view, and each of the intervening band cells including a via structure configured to transfer a reference voltage signal from the back side of the substrate to the front side of the substrate.

[0005] According to another aspect of the embodiments of the present application, a memory device is provided, including: a first cell disposed over a front side of a substrate, the front side opposite a back side of the substrate; a second cell disposed over the front side of the substrate, spaced apart from the first cell along a first direction in a top view of the memory device; a first metal line disposed over the front side of the substrate, the first metal line electrically coupled to the first cell and the second cell; a second metal line disposed over the back side of the substrate; and a middle band cell interposed between and aligned with the first cell and the second cell along the first direction, the middle band cell including a via structure electrically coupling the first metal line to the second metal line.

[0006] According to yet another aspect of the embodiments of the present application, a method of forming a memory device is provided, including: forming a first array portion, a second array portion, and a middle band cell array in the memory device, the middle band cell array interposed between the first array portion and the second array portion along a first direction, the first array portion, the second array portion, and the middle band cell array including: first and second active regions each extending over a front side of a substrate along the first direction and spaced apart along a second direction perpendicular to the first direction in a top view of the memory device, wherein the first and second active regions provide first cells in the first array portion, second cells in the second array portion, and middle band cells in the middle band cell array; and a third active region extending along the first direction and vertically stacked under the first active region along a third direction perpendicular to the first and second directions; forming a via structure in the middle band cell between the first and second active regions along the second direction, the via structure extending between the front side of the substrate and a back side opposite the front side along the third direction; forming a first metal line over the first and second active regions along the third direction, the first metal line electrically coupled to the first and second active regions; and forming a second metal line over the back side of the substrate, the second metal line electrically coupled to the third active region and the via structure electrically coupled to the second metal line and the first metal line. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale, and are merely intended as illustrative. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] FIG. 1 A block diagram of a memory device having a vertically stacked structure is shown in accordance with some embodiments.

[0009] FIG. 2 A block diagram of a memory device having a vertically stacked structure is shown in accordance with some embodiments. FIG. 1 A portion of the illustrated memory device (e.g., a memory array).

[0010] FIG. 3A A perspective view of a portion of a memory device is shown in accordance with some embodiments. FIG. 2 A perspective view of a portion of a memory device is shown in accordance with some embodiments.

[0011] FIG. 3B A perspective view of a portion of a memory device is shown in accordance with some embodiments. FIG. 3A A perspective view of a portion of a memory device is shown in accordance with some embodiments.

[0012] FIG. 4 A block diagram of a memory device having a vertical stack structure is shown in accordance with some embodiments.

[0013] FIG. 5 A front view of a portion of an example layout design of a memory device having a vertical stack structure is shown in accordance with some embodiments, taken along the AA' plane. FIG. 3A A front view of a portion of an example layout design of a memory device having a vertical stack structure is shown in accordance with some embodiments, taken along the AA' plane.

[0014] FIG. 6 A back view of a portion of an example layout design of a memory device having a vertical stack structure is shown in accordance with some embodiments, taken along the BB' plane and corresponding to the front view shown in FIG. 3A A back view of a portion of an example layout design of a memory device having a vertical stack structure is shown in accordance with some embodiments, taken along the BB' plane and corresponding to the front view shown in FIG. 5 A back view of a portion of an example layout design of a memory device having a vertical stack structure is shown in accordance with some embodiments, taken along the BB' plane and corresponding to the front view shown in

[0015] FIG. 7 A front view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 11 A front view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 15 A front view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 19 A front view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 5 A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in

[0016] A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 8 A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 12 A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 16 A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 20 A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in FIG. 6 A back view of a portion of an example layout design is shown in accordance with some embodiments, as shown in

[0017] FIG. 9 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 13 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 17 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 21 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 7 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 8 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 11 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 12 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 15 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 16 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 19 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 20 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in

[0018] FIG. 10 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 14 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 18 A cross-sectional view of a portion of an example layout design is shown in accordance with some embodiments, taken along the CC' line, as shown in FIG. 22Examples of cuts along the DD' line according to some embodiments are shown respectively. FIG. 7 (or FIG. 8 ), FIG. 11 (or FIG. 12 ), FIG. 15 (or FIG. 16 )and FIG. 19 (or FIG. 20 The example layout design shown is a partial cross-sectional view.

[0019] FIG. 23 A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments is shown.

[0020] FIG. 24 A block diagram of an integrated circuit layout design generation system according to some embodiments is shown.

[0021] FIG. 25 A block diagram of an integrated circuit manufacturing system and its associated manufacturing process according to some embodiments is shown.

[0022] FIG. 26 A flowchart illustrating a method for manufacturing a memory device having a vertically stacked structure according to some embodiments is shown.

[0023] FIG. 27 The following are examples of implementations. FIG. 26 The flowchart shows a portion of the method.

[0024] FIG. 28 and FIG. 29 The following are examples illustrating the use of various embodiments. FIG. 27 A three-dimensional perspective view of a portion of the storage cells in a storage device with a vertically stacked structure, representing an intermediate stage of the method shown in the flowchart.

[0025] FIG. 30 , FIG. 31 , FIG. 32 and FIG. 33 The following are examples illustrating the use of various embodiments. FIG. 27 The flowchart shows the intermediate stages and along the process. FIG. 29 A cross-sectional view of a portion of the storage cell shown along the EE' line.

[0026] FIG. 34 , FIG. 35 and FIG. 36 The following are examples illustrating the use of various embodiments. FIG. 26 The flowchart shows a top view of the layout design of the intermediate stage of the method, specifically the middle band cell portion of a storage device with a vertical stacking structure.

[0027] FIG. 37 and FIG. 38 The following are examples illustrating the use of various embodiments.FIG. 26 The flowchart shows the intermediate stages and along the process. FIG. 29 A cross-sectional view of a portion of the storage cell shown along the EE' line. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0030] The structures and methods detailed below relate to improved structures, designs, and fabrication methods for CFET integrated circuit devices. In some embodiments, the semiconductor device stack includes top or upper semiconductor devices physically stacked vertically above bottom or lower semiconductor devices. CFET structures include stacked upper and lower semiconductor devices of different conductivity types. For simplicity, semiconductor device stacks are sometimes referred to as device stacks. Depending on the device design, the included device stacks may include stacked semiconductor devices of the same conductivity type, and / or stacked semiconductor devices of different conductivity types. For example, n-type metal-oxide-semiconductor (NMOS) transistors may be vertically stacked above p-type metal-oxide-semiconductor (PMOS) transistors. In some embodiments, by configuring the semiconductor devices as device stacks, the required chip area can be reduced by up to 50%.

[0031] In some embodiments, the semiconductor devices in the device stack are coupled in an electrically series manner, which is advantageous in high-voltage applications. In some embodiments, the semiconductor devices in the device stack are coupled in an electrically parallel manner, which is advantageous in high-current applications. In at least one embodiment, the device stack can be advantageously applied to the memory devices or memory regions of an IC device. In one or more embodiments, further advantages of the device stack include improvements in the power, performance, and / or area (PPA) of the final IC device, etc.

[0032] FIG. 1 An exemplary block diagram of a semiconductor memory device 100A (hereinafter referred to as memory device 100A) according to various embodiments is shown. In some embodiments, memory device 100A is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, transistors (e.g., p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, etc.), other suitable components, or combinations thereof.

[0033] The memory device (or macrocell) 100A includes one or more of input / output (I / O) circuitry 110, control logic circuitry 120, word line (WL) drivers 130, and memory blocks 101, which contain multiple memory arrays, such as a first memory array 102 and a second memory array 104. In this disclosure, the I / O circuitry 110, control logic circuitry 120, and word line drivers 130 may be collectively referred to as the peripheral circuitry of the memory device 100A. Although FIG. 1 Although not explicitly shown, the components of memory device 100A may be electrically coupled (or operatively coupled) to each other and coupled to control logic circuitry 120. For example, I / O (input / output) circuitry 110, control logic circuitry 120, and WL driver 130 may be electrically coupled to memory block 101. Furthermore, although the components are shown in [the diagram / illustrative context] for purposes of illustration... FIG. 1 The components are shown as independent blocks, but in some embodiments, some or all of the components may be integrated together.

[0034] In this embodiment, a memory block 101 (e.g., memory arrays 102 and 104 together) is formed above a substrate (e.g., a semiconductor substrate). The memory block 101 may be included in a microprocessor, memory cell, and / or other integrated circuit device. In some embodiments, each memory array 102, 104 is electrically coupled to a corresponding input / output circuit 110. In this configuration, each memory array 102, 104 may be arranged adjacent to the corresponding input / output circuit 110 along a first direction (e.g., the X direction). Furthermore, memory arrays 102 and 104 may be arranged along a second direction (e.g., the Y direction) such that the boundaries of the memory arrays are adjacent to the vertical boundaries of the input / output circuit 110. Control logic circuitry 120 and word line driver 130 may be electrically coupled to each memory array 102 and 104. It should be noted that the arrangement of the components of the memory device 100A is not limited to... FIG. 1 As shown, the components of its peripheral circuit can be arranged around the memory block 101 and electrically connected to it through a variety of suitable layout designs.

[0035] Storage arrays 102 and 104 are configured as hardware components for storing data. In one aspect, storage arrays 102 and 104 are embodied as semiconductor storage devices. (Refer to...) FIG. 2 The storage arrays 102 and 104 contain a plurality of storage cells (storage units or bit units) 10. The storage arrays 102 and 104 include a plurality of rows R1, R2, R3…R extending along a first direction. M And several columns C1, C2, C3…C extending along the second direction. N Each row / column may contain one or more conductive structures. In some embodiments, each memory cell 10 is disposed at the intersection of the corresponding row and the corresponding column, and is operable according to the voltage or current flowing through the respective conductive structures of the column and the row.

[0036] In this embodiment, memory cell 10 is configured as a static random access memory (SRAM) cell, although this disclosure is also applicable to other types of memory cells. Furthermore, for discussion purposes, each memory cell 10 includes transistors stacked along a third direction (e.g., the Z direction). In some embodiments, each memory cell 10 is configured with a CFET structure, wherein a metal gate structure is coupled to vertically stacked active regions to provide various vertically stacked transistors. In some examples, memory cell 10 may additionally or alternatively include other types of FET structures, such as nanosheet FETs, nanowire FETs, gate all-around (GAA) FETs, etc.

[0037] refer to FIG. 3AA three-dimensional perspective view of an embodiment of a memory cell 10 having a CFET structure is shown. According to some embodiments of this disclosure, the memory cell 10 includes six transistors (6T) and is therefore referred to as a 6T SRAM cell. In some examples, the memory cell 10 may be implemented as any of a variety of SRAM cells, such as a two-transistor two-resistor (2T-2R) SRAM cell, a four-transistor (4T) SRAM cell, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, etc.

[0038] like FIG. 3A As shown, the memory cell 10 includes a first pull-up transistor (PU1; not in...) FIG. 3A (shown in the perspective view), the first pull-down transistor (PD1; not in) FIG. 3A (shown in the perspective view), second pull-up transistor (PU2), second pull-down transistor (PD2), first transmission gate transistor (PG1), and second transmission gate transistor (PG2; not shown in the perspective view) FIG. 3A (As shown in the perspective view). In some embodiments, transistors PD1, PD2, PG1 and PG2 each include an NMOS transistor, and PU1 and PU2 each include a PMOS transistor.

[0039] Combination FIG. 3A and FIG. 3B Referring together, PU1 and PD1 are coupled to form a first inverter (or a first cross-coupled inverter), and PU2 and PD2 are coupled to form a second inverter (or a second cross-coupled inverter), wherein the first inverter and the second inverter are cross-coupled with each other. Specifically, the first inverter and the second inverter are each coupled between the power supply voltage (or the first power supply voltage) VDD and ground (or the second power supply voltage) VSS through corresponding front (FS) source / drain contacts (MD) and front via contacts (VD), or back (BS) source / drain contacts (BMD) and back via contacts (BVD). In addition to being coupled to the first inverter and the second inverter, transistors PG1 and PG2 are also each coupled to the word line (WL) through a gate contact (e.g., a back gate contact (BVG)). Transistors PG1 and PG2 are also coupled to the bit line (BL) and bit line complement (BBL) through corresponding MD and VD, respectively. In the illustrated embodiment, memory cell 10 includes two ground VSS lines extending along the edge of the memory cell in a first direction. In an alternative embodiment, memory cell 10 may include only one ground VSS line that runs through the center of memory cell 10 in a first direction and is located between BL and BLB in a second direction. The ground VSS line, BL, and BLB may each be configured as one of the front-side MO metal lines closest to the front side of the substrate, while WL and the power supply voltage VDD may each be configured as one of the back-side MO metal lines closest to the back side of the substrate.

[0040] In this embodiment, refer to FIG. 3A PU1 and PD1, coupled to form a first inverter, are stacked and aligned vertically along a third direction (e.g., channel alignment), while PU2 and PD2, coupled to form a second inverter, are stacked and aligned vertically along a third direction in a manner similar to the first inverter. In some embodiments, PU1 and PU2 are formed in a lower active region (or lower layer of a CFET structure) extending along a first direction and spaced apart along a second direction. This lower active region may be doped with n-type dopants, such as phosphorus (P), arsenic (As), antimony (Sb), and combinations thereof, to provide a PMOS transistor in the lower layer. Similarly, PD1, PD2, PG1, and PG2 are formed in an upper active region (or upper layer of a CFET structure) above the lower active region, wherein the upper active region extends along a first direction and is spaced apart along a second direction. This upper active region may be doped with p-type dopants, such as boron (B), aluminum (Al), indium (In), and gallium (Ga), and combinations thereof, to provide an NMOS transistor in the upper layer. In some embodiments, an NMOS transistor is formed in the lower layer of the memory device 100A, and a PMOS transistor is formed in the upper layer of the memory device 100A.

[0041] Reference FIG. 1 The WL driver 130 (which may include a row decoder and word line voltage supply unit) is responsible for activating the word lines within memory arrays 102 and 104. When a word line is needed from memory cell 10 (see memory cell 10) in memory arrays 102 and 104... FIG. 2 When reading or writing data to a row of the memory device 100A, word line driver 130 selects the appropriate word line by driving the corresponding word line to a high voltage level. Subsequently, a sense amplifier or write driver connected to the bit line (extending vertically and intersecting the word line) can perform read or write operations on the cells of the selected row. I / O circuitry 110 is a hardware component that allows access (e.g., read, program) to each asserted memory cell via a region decoder (such as a row decoder and a column decoder). Control logic circuitry 120 is a hardware component that controls the various coupled components of the memory device 100A (e.g., components 110, 120, and 130).

[0042] Still referencing FIG. 1In embodiments where the memory block 101 of the memory device 100A includes an array (102 and 104) of CFET-based memory cells 10, power (e.g., a reference voltage signal) can be transmitted from a back metal line configured as a power distribution network (PDN) to a front metal line (e.g., ground VSS) via a power tap unit 140. Therefore, the power tap unit 140 extends along a third direction through the substrate and multiple dielectric layers (e.g., a front isolation layer including shallow trench isolation (STI), an interlayer dielectric (ILD) layer, etc.). In various examples, power transmission of the power tap unit 140 relies on one or more via structures, such as vertical local interconnect (VLI) structures. Once power is transmitted to the front side of the substrate, it is continuously transmitted within the memory block 101 by multiple front interconnect structures (e.g., contact elements, vias, metal lines, etc.). In the prior art, since the power tap unit 140 is arranged along the edge of the memory block 101 (e.g., ...), the power supply is distributed in a specific manner. FIG. 1 As shown, memory device 100A experiences significant IR voltage drops (e.g., substantial voltage drops due to high resistance) during power delivery, especially as the size of memory arrays 102 and 104 and the bit line (BL) load continue to increase at advanced technology nodes. Therefore, there is a need to improve the power delivery system of CFET-based memory devices.

[0043] This disclosure provides memory devices configured with additional power delivery options, implemented by providing one or more power strip cells within various memory arrays (e.g., memory arrays 102 and 104), rather than relying solely on edge-arranged power tap cells (e.g., power tap cell 140). Such power strip cells may be referred to as intermediate strip cells (MSCs) or in-array (relative to edge) strip cells, compared to power tap cell 140. In various embodiments, by electrically coupling the PDN to ground VSS via one or more VLIs (e.g., VLI 60) in the in-array strip MSC cells (as a complement and / or alternative to edge-arranged power tap cells), the power delivery path (e.g., the path through various interconnect structures) can be shortened, thereby reducing the IR voltage drop between the front and back sides and ultimately improving device performance.

[0044] For example, refer to again FIG. 1 The storage device 100A also includes a first MSC array 152A and a second MSC array 154A (in a top view of the device 100A) extending from the first MSC array 152A along a second direction, wherein the first MSC array 152A and the second MSC array 154A each include a plurality of MSCs 150. In this embodiment, as will be described in detail below, each MSC 150 includes a VLI 60, which is centered on the MSC 150 along the first and second directions.

[0045] In the illustrated embodiment, the first MSC array 152A divides the first storage array 102 into a first array portion 102A and a second array portion 102B along a first direction. Similarly, the second MSC array 154A divides the second storage array 104 into a first array portion 104A and a second array portion 104B. In this respect, the first array portions 102A and 104A are aligned along a second direction, and the second array portions 102B and 104B are also aligned along a second direction.

[0046] In this embodiment, each MSC 150 in a given MSC array corresponds to a row of memory cells 10 in adjacent first and second memory array portions and is horizontally aligned therewith. For example, each MSC 150 in the first MSC array 152A is inserted along a first direction between memory cells 10 in the first array portion 102A and memory cells 10 in the second array portion 102B. In some embodiments, a plurality of MSCs 150 in each of the first MSC array 152A and the second MSC array 154A are aligned along a second direction in a top view (see [link to top view]). FIG. 5 and FIG. 6 Therefore, as FIG. 2 As shown, the number of MSCs 150 in each MSC array 152A and 154A corresponds to the number M of rows of storage cells 10 in the corresponding storage arrays 102 and 104, respectively. For example, the number of MSCs 150 (the number of VLIs) in the first MSC array 152A corresponds to the number M of rows of storage cells 10 in storage array 102, and the number of MSCs 150 in the second MSC array 154A corresponds to the number M of rows of storage cells 10 in storage array 104.

[0047] although FIG. 1 The word line driver 130 shown separates the first memory array 102 (and a portion thereof) and the second memory array 104 (and a portion thereof) along a second direction. However, within the scope of this disclosure, memory arrays 102 and 104 may be arranged adjacent to each other along the second direction without any intervening elements. Regardless of the arrangement of peripheral circuitry, each MSC array 152A and 154A is arranged or interposed between the two memory array portions along a first direction. In other words, each MSC array 152A and 154A has a first vertical boundary (i.e., extending along the second direction in the top view) adjacent to the vertical boundary of the corresponding first array portion 102A or 104A, and a second vertical boundary adjacent to the vertical boundary of the corresponding second array portion 102B or 104B, respectively. In contrast, the power tap unit 140 has only one vertical boundary adjacent to the vertical boundary of the first array portion 102A or 104A, such that the power tap unit 140 is not adjacent to any vertical boundary of the second array portion 102B / 104B.

[0048] In some embodiments, such as FIG. 1 As shown, the storage device 100A includes one MSC array (152A or 154A) in each storage array (102 or 104, respectively). In some embodiments, reference is made to... FIG. 4 A semiconductor memory device 100B (hereinafter referred to as memory device 100B) similar to memory device 100A is shown, which may include multiple MSC arrays in each memory array 102, 104. For example, memory device 100B may include three MSC arrays 152A, 152B, and 152C (collectively referred to as MSC array 152) spaced apart along a first direction in memory array 102, and three MSC arrays 154A, 154B, and 154C (collectively referred to as MSC array 154) spaced apart along a first direction in memory array 104. Thus, multiple MSC arrays divide a given memory array into several parts, the number of array parts depending on the number of MSC arrays contained therein.

[0049] For example, in the illustrated embodiment, MSC arrays 152A-152C divide storage array 102 into four array sections 102A, 102B, 102C, and 102D, while MSC arrays 154A-154C divide storage array 104 into four array sections 104A, 104B, 104C, and 104D. The increased number of MSCs allows for a corresponding increase in the number of VLIs capable of transmitting reference voltage signals from the back of the storage device to the front (e.g., grounded VSS), thereby further reducing IR voltage drop during power distribution and ultimately improving the overall performance of the storage device.

[0050] According to various embodiments, FIG. 5 An example layout of a portion of the upper layer of a semiconductor memory device 100C (hereinafter referred to as memory device 100C) is shown, the layout being along... FIG. 3A The plane AA' is intercepted, and FIG. 6 An example layout of a portion of the lower level of the storage device 100C is shown, which is along... FIG. 3A The plane BB' intercepts the corresponding FIG. 5 The portions depicted. In the illustrated embodiment, components in storage device 100C similar to those in storage device 100A or storage device 100B are described using the same reference numerals for simplicity. It should be noted that in FIG. 5 and FIG. 6 The peripheral circuitry of the storage device 100B is omitted in order to depict a portion of the storage block 101 in more detail.

[0051] refer to FIG. 5 and FIG. 6Each of the first array portions 102A, 104A and the second array portions 102B, 104B shows three example memory cells 10 arranged along a second direction. Each MSC 150 is inserted between the memory cells 10 in the first array portions 102A, 104A and the memory cells 10 in the second array portions 102B, 104B, and is substantially aligned along the first direction. FIG. 5 and FIG. 3A Each of the three MSC 150s is depicted such that their respective VLI 60s are substantially aligned along the second direction.

[0052] In this embodiment, adjacent rows of memory cells 10 and their corresponding MSCs 150 are separated by horizontal boundaries 11A extending along a first direction in a top view. Each MSC 150 includes two vertical boundaries 11B extending along a second direction, which separate the MSC 150 from adjacent memory cells 10. In some embodiments, each VLI 60 is located at the center of the MSC 150 along both the first and second directions, wherein the height H of the VLI 60 is the same as the height H' of each memory cell 10 along the second direction. The width W of the MSC 150 may be defined by the spacing between the two vertical boundaries 11B, which are disposed adjacent to each of the two active region isolation structures 40A and 40B extending along the second direction. In some embodiments, the active region isolation structures 40A and 40B are configured as continuous polysilicon on diffusion edges (CPODE) structures. In some examples, the width W of each MSC 150 is at least approximately 5 times the center polysilicon pitch (CPP), and the active region isolation structures 40A and 40B are set to be spaced 0.5 CPP apart.

[0053] refer to FIG. 3B For example, memory device 100C includes multiple upper active regions 22A, 22B, 22C, 22D, 22E, and 22F (collectively referred to as upper active regions 22), each extending along a first direction and spaced apart along a second direction. The memory device 100C also includes multiple metal gate structures 32A, 32B, 32C, 32D, 32E, 32F, and 32G (collectively referred to as metal gate structures 32) on its front side, each extending along the second direction and spaced apart along the first direction. Each metal gate structure 32 is coupled to each upper active region 22, thereby providing multiple NMOS transistors, such as PG1, PG2, PD1, and PD2, in each memory cell 10 (see [link to relevant documentation]). FIG. 5 and FIG. 5 In this configuration, the upper active region 22 may be doped with a p-type dopant as described herein.

[0054] Still referencing FIG. 7The memory device 100C also includes a plurality of gate isolation structures 50A, 50B, and 50C (collectively referred to as gate isolation structures 50), each gate isolation structure extending along a first direction and inserted along a second direction between two adjacent upper active regions 22. For example, gate isolation structure 50A is inserted between upper active regions 22A and 22B; gate isolation structure 50B is inserted between upper active regions 22C and 22D; and gate isolation structure 50C is inserted between upper active regions 22E and 22F. In this embodiment, the gate isolation structures 50 are configured to cut (sever or isolate) each metal gate structure 32 into separate portions along the second direction.

[0055] As shown, still refer to FIG. 6 The upper active region 22 and the gate isolation structure 50 extend along a first direction across each of the first array portions 102A, 104A, the corresponding MSC arrays 152, 154, and the corresponding second array portions 102B, 104B. In this regard, each VLI 60 is formed above a portion of the gate isolation structure 50 between two adjacent upper active regions 22 in the MSC 150. In this embodiment, the gate isolation structure 50 and the corresponding VLI 60 formed above it both extend along a third direction to the substrate of the memory device 100C (e.g., ...). FIG. 3A The substrate 12 extends through both the upper and lower layers. In this embodiment, each VLI 60 also extends through the substrate in a third direction to electrically couple conductive structures (e.g., back metal line 90) formed on the back side of the substrate (e.g., PDN) to front metal lines (e.g., front metal line 80). As described herein, introducing multiple VLI 60s within the MSC 150 of the array provides additional conductive paths for transmitting power (i.e., reference voltage signals) from the back side of the substrate to the front side, thereby reducing the IR voltage drop between the front and back sides of the memory device.

[0056] Similarly, refer to FIG. 3B The memory device 100C includes a plurality of lower active regions 20A, 20B, 20C, 20D, 20E, and 20F (collectively referred to as lower active regions 20) extending in a first direction and spaced apart in a second direction. The memory device 100C also includes a plurality of metal gate structures 30A, 30B, 30C, 30D, 30E, 30F, and 30G (collectively referred to as metal gate structures 30) extending in the second direction and spaced apart in the first direction on its back surface. Each metal gate structure 30 is coupled to the plurality of lower active regions 20, thereby forming a plurality of PMOS transistors (e.g., PU1 and PU2, see [reference]) in each memory cell 10. FIG. 7 to FIG. 22 and FIG. 7 In this regard, the lower active region 20 may be doped with an n-type dopant as described herein.

[0057] The following will combineFIG. 11 The components of storage device 100C are described in detail. Specifically: FIG. 15 , FIG. 19 , FIG. 5 and FIG. 8 Show each FIG. 12 The storage device 100C portion within the dashed box (i.e., the example layout of storage device 100C cut along the AA' plane); FIG. 16 , FIG. 20 , FIG. 7 and FIG. 11 Corresponding to FIG. 15 , FIG. 19 , FIG. 6 and FIG. 9 , showing FIG. 13 An embodiment of a portion of the storage device 100C shown (i.e., an example layout of the storage device 100C taken along the BB' plane); FIG. 17 , FIG. 21 , FIG. 7 and FIG. 8 Show along FIG. 11 (or FIG. 12 ), FIG. 15 (or FIG. 16 ), FIG. 19 (or FIG. 20 )and FIG. 10 (or FIG. 14 A cross-sectional view of the storage device 100C taken by line CC' in the diagram; FIG. 18 , FIG. 22 , FIG. 7 and FIG. 8 Show along FIG. 11 (or FIG. 12 ), FIG. 15 (or FIG. 16 ), FIG. 19 (or FIG. 20 )and FIG. 7 to FIG. 22 (or FIG. 7 A cross-sectional view of the storage device 100C taken by line DD' in the diagram. FIG. 11 Each part of the storage device 100C shown includes at least a portion of the storage cells 10 and a complete MSC 150 including VLI 60. FIG. 15 , FIG. 19 , FIG. 3A and FIG. 5 The memory device 100C portion is shown from a front view of the substrate 12, thereby demonstrating at least the upper layer of the memory device 100C (see, for example, [reference]). FIG. 9 and FIG. 13 );and FIG. 17 , FIG. 21 , FIG. 3A and FIG. 6All views of the memory device 100C are taken from the back side of the substrate 12, thereby showing at least the lower layers of the memory device 100C (see, for example, [reference]). FIG. 7 and FIG. 8 ).

[0058] Reference FIG. 7 and FIG. 7 The memory device 100C includes a substrate 12 located beneath each of the transistors described herein. In some embodiments, the substrate 12 comprises an elemental semiconductor material such as silicon. In some embodiments, the substrate 12 has a semiconductor-on-insulator (SOI) structure. For example, the substrate 12 may comprise a buried oxide layer (BOX) formed by a SIMOX process or other suitable techniques such as wafer bonding and polishing. The substrate 12 may comprise other suitable semiconductor materials.

[0059] The memory device 100C also includes an isolation structure 14 disposed above the substrate 12. The isolation structure 14 may include shallow trench isolation (STI), comprising oxides such as silicon oxide, nitrides, low-k dielectric materials (e.g., dielectric materials with a dielectric constant less than silicon oxide), or combinations thereof. The isolation structure 14 is used to electrically isolate adjacent conductive components (e.g., the upper active region 22) formed on the electrical isolation substrate 12. FIG. 8 In the isometric view, the isolation structure 14 overlaps with a portion of the substrate 12. Furthermore, each gate isolation structure 50 (and the VLI 60 disposed therein) is formed above a portion of the isolation structure 14 between two adjacent (upper) active regions. Therefore, the VLI 60 requires no additional device area allocation and can be easily integrated into existing device manufacturing processes.

[0060] In this embodiment, refer to FIG. 7 Each upper active region 22 includes a multilayer structure protruding from the substrate 12. Each upper active region 22 contains a plurality of nanosheets (or other suitable nanostructures, such as nanowires or nanorods) stacked along a third direction, configured as channels for transistors (e.g., NMOS transistors) in the upper layers of the memory device 100C. The nanosheets in the upper active regions 22 may be doped with a p-type dopant to form the NMOS transistors described herein.

[0061] Metal gate structures 32 are formed above substrate 12 and extend over upper active region 22 along a second direction. Each metal gate structure 32 includes a gate electrode (not shown) disposed above a gate dielectric layer (not shown). In this embodiment, a portion of each metal gate structure 32 surrounds a nanosheet stack in upper active region 22 to form a transistor in upper layer of memory device 100C.

[0062] Similarly, refer to FIG. 8Each lower active region 20 comprises a multilayer structure protruding from the substrate 12 and surrounded by an isolation structure 14. Each lower active region 20 comprises a plurality of nanosheets stacked along a third direction, which are configured as channels for each transistor (e.g., a PMOS transistor) in the lower layer of the memory device 100C. The nanosheets in the lower active regions 20 may be doped with n-type dopants to form the PMOS transistors described herein. Metal gate structures 30 are formed along a third direction below a corresponding metal gate structure 32, and each metal gate structure 30 comprises a gate electrode (not shown) disposed above a gate dielectric layer (not shown). A portion of each metal gate structure 30 surrounds the nanosheet stack in the lower active regions 20 to form transistors in the lower layer of the memory device 100C.

[0063] Reference FIG. 7 The memory device 100C includes multiple source / drain components 26 (26A, 26B, etc.) adjacent to each metal gate structure 32 (i.e., adjacent to the nanosheet stack in the upper active region 22). For example, source / drain component 26A is formed adjacent to the nanosheet stack in the upper active region 22A, and source / drain component 26B is formed adjacent to the nanosheet stack in the upper active region 22B. Similarly, referring to... FIG. 8 The memory device 100C includes a plurality of source / drain components 24 (24A, 24B, etc.) adjacent to each metal gate structure 30 (i.e., adjacent to the nanosheet stack in the lower active region 20). For example, source / drain component 24A is formed adjacent to the nanosheet stack in the lower active region 20A, and source / drain component 24B is formed adjacent to the nanosheet stack in the lower active region 20B.

[0064] For an embodiment in which the transistors formed in the upper layer of the memory device 100C are configured as NMOS transistors (see [reference]...) FIG. 7 The source / drain components 26 may include silicon (Si) or silicon carbide (SiC) doped with the n-type dopant described herein. For an embodiment in which the transistor formed in the lower layer of the memory device 100C is configured as a PMOS transistor (see [link to embodiment]),... FIG. 9 The source / drain component 24 may include silicon germanium (SiGe) doped with the p-type dopant described herein.

[0065] refer to FIG. 10 , FIG. 7 and FIG. 9The memory device 100C also includes multiple front-side contact structures that electrically couple the various components of the transistors in the upper layers to the front-side interconnect structures and further to the front-side metal lines. For example, the memory device 100C includes multiple front-side source / drain contacts 70A, 70B, 70C, 70D, 70E, 70F, 70G, 70H, 70I, and 70J (collectively referred to as front-side source / drain contacts 70), each extending along a second direction and inserted or disposed between two adjacent metal gate structures 32 along a first direction. Each front-side source / drain contact 70 may continuously span multiple upper active regions 22 (e.g., front-side source / drain contact 70G) or span a single upper active region 22 (e.g., front-side source / drain contact 70A) along the second direction. Each front-side source / drain contact 70 is electrically coupled to a source / drain component 26. For example, the front-side source / drain contacts 70 may each be electrically coupled to one of the source / drain components 26A and / or one of the source / drain components 26B. In some embodiments, the memory device 100C further includes interlayer source / drain contacts 72A and 72B, each electrically coupling one of the source / drain contacts 26 disposed in the upper layer to one of the source / drain contacts 24 disposed in the lower layer. The memory device 100C also includes a plurality of front-side gate contacts 74A and 74B (collectively referred to as gate contacts 74), each extending vertically in a third direction and electrically coupling one of the metal gate structures 32 to a front-side interconnect structure (e.g., a front-side metal line 80).

[0066] In addition, see also FIG. 10 , FIG. 7 and FIG. 7-FIG. 10 The memory device 100C may include multiple front-side interconnect structures electrically connected to the contact structures described herein. For example, the memory device 100C includes multiple front-side via contacts 78A, 78B, 78C, 78D, 78E, and 78F (collectively referred to as front-side via contacts 78). Each front-side via contact 78 extends vertically along a third direction and electrically connects a contact structure (e.g., front-side source / drain contacts 70, front-side gate contacts 74, etc.) to one of the front-side metal lines 80A, 80B, 80C, 80D, and 80E (collectively referred to as front-side metal lines 80). The front-side metal line 80 may alternatively be referred to as the M0 metal line because it is disposed in the metallization layer M0 closest to the front side of the substrate 12.

[0067] Specifically, see FIG. 8 The front metal line 80C is configured as a ground VSS, which extends continuously along a first direction through the center of the memory cell 10 and the MSC 150. In this configuration, the front metal line 80C is equidistant from each horizontal boundary 11A of the memory cell 10. In this embodiment, the ground VSS is provided through at least VLI 60 in the MSC 150. FIG. 7(One of which is shown and will be detailed below) is electrically connected to the PDN above the back side of substrate 12. Furthermore, metal lines 80B and 80D are configured as bit lines BL and complementary bit lines BLB, respectively, and metal lines 80A and 80E are configured as two front-side word lines (i.e., active metal lines). In some embodiments, at least a portion of the front-side source / drain contacts 70 are each electrically connected to one of the front-side metal lines 80 via corresponding front-side via contacts 78. Additionally, the metal gate structures 32 provided in the memory cell 10 are each electrically connected to one of the metal lines 80A and 80E via corresponding gate contacts 74.

[0068] Similarly, refer to FIG. 8 The memory device 100C further includes a plurality of back-side source / drain contacts 82A, 82B, 82C, 82D, 82E, 82F, 82G, 82H, 82I, and 82J (collectively referred to as back-side source / drain contacts 82), each contact being disposed on the back side of the substrate 12 and electrically coupled to one of the source / drain components 24. The memory device 100C also includes a plurality of back-side gate contacts 84A, 84B, 84C, and 84D (collectively referred to as back-side gate contacts 84). In this embodiment, the back-side source / drain contacts 82 and the front-side source / drain contacts 70 are configured to have uniform dimensions and pitch or spacing along a first direction. The memory device 100C further includes a plurality of back-side via contacts 88A, 88B, 88C, and 88D (collectively referred to as back-side via contacts 88), which are electrically coupled to a back-side metal line. Each back-side source / drain contact 82 electrically couples one of the source / drain components 24A and / or one of the source / drain components 24B to the corresponding back-side via contact 88.

[0069] In addition, the memory device 100C also includes multiple back metal lines (e.g., BMO metal lines) 90A, 90B, 90C, 90D, 90E, 90F, and 90G (collectively referred to as back metal lines 90). Each back via contact 88 electrically couples one of the back source / drain contacts 82 to one of the corresponding back metal lines 90, and each back gate contact 84 electrically couples one of the metal gate structures 30 to one of the corresponding back metal lines 90. (Refer to...) FIG. 7 and FIG. 8 Each front metal line 80 extends along a first direction and is therefore substantially parallel to each other, while the back metal lines 90 may extend in different directions. For example, back metal lines 90A and 90B each extend along the first direction, and back metal lines 90C and 90D each extend along a second direction and are substantially perpendicular to back metal lines 90A and 90B.

[0070] In some embodiments, the storage device 100C further includes back via contacts 86A and 86B (collectively referred to as back via contacts 86), each back via contact electrically coupling one of the back source / drain contacts 82 to one of the back metal lines 90. For example, back via contact 86A electrically couples back source / drain contact 82B to back metal line 90C, and back via contact 86B electrically couples back source / drain contact 82E to back metal line 90D. In some embodiments, back metal lines 90C and 90D are configured to power supply voltage VDD.

[0071] In various embodiments, the front / back source / drain contacts 70 / 82, the interlayer source / drain contacts 72, the front / back gate contacts 74 / 84, the front / back via contacts 78 / 86 / 88, and the front / back metal lines 80 / 90 all comprise conductive materials such as tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), platinum (Pt), and combinations thereof (or alloys thereof). In some embodiments, one or more of the above contact structures, interconnect structures, and metal lines may include a barrier layer having TiN, TaN, etc., a silicide layer having a metal silicide material such as NiSi, other suitable materials, or combinations thereof.

[0072] Furthermore, although omitted for brevity, each of the above contact structures, interconnect structures and metal lines may be formed or embedded in a dielectric layer, including one or more of an interlayer dielectric (ILD) layer, a contact etch stop layer (CESL), etc., or combinations thereof, which is configured to electrically isolate the above structures from surrounding conductive components.

[0073] As stated in this article, still refer to FIG. 7-FIG. 10 and FIG. 7 to FIG. 10 Each active region isolation structure 40 extends along a second direction and truncates active regions 20 and 22 into separate portions. In various embodiments, each active region isolation structure 40 is disposed near the vertical boundary 11B of the memory cell MSC150 to prevent or reduce short circuits between each vertical interconnect structure VLI 60 and adjacent memory cells 10. In some embodiments, the active region isolation structure 40 is configured to be located at a distance of 0.5 CPP from the vertical boundary 11B. On the other hand, each gate isolation structure 50 extends along a first direction and truncates metal gate structures 30 and 32 into separate portions. FIG. 7 In the illustrated embodiment, each gate isolation structure 50 extends through the center of the memory cell 10 such that the gate isolation structure 50 is equidistant from each horizontal boundary 11A of the memory cell 10. The active region isolation structure 40 and the gate isolation structure 50 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, etc., or combinations thereof.

[0074] In some embodiments, in conjunction with reference FIG. 8 The memory cell assembly 150 includes a VLI 60 corresponding to each adjacent memory cell 10 along a first direction. The VLI 60 is disposed within the gate isolation structure 50 (e.g., FIG. 7 to FIG. 10 and FIG. 11-FIG. 14 The gate isolation structure 50A shown is located in or above an extension 61 that extends vertically through the center of memory cell 10 and MSC 150 in a third direction. In the illustrated embodiment, a front metal line 80C configured as ground VSS also extends through the center of memory cell 10 and MSC 150, such that ground VSS is at least partially vertically aligned with VLI 60 in a third direction.

[0075] In a top view, VLI 60 extends with a width W1 along a first direction and a height H1 along a second direction. In some embodiments, a portion of the gate isolation structure 50A adjacent to the extension 61 is defined by a height H3, while the extension 61 is defined by a height H2, which is greater than the height H1. In some embodiments, height H1 and height H3 are substantially equal. In some embodiments, height H1 is greater than height H3 but less than height H2. While this disclosure does not limit the specific dimensions of VLI 60, to reduce the total area of ​​the memory device 100C, the width W1 may be maintained at least about 2 CPPs, i.e., spanning at least the three metal gate structures 32 on the front side and the three metal gate structures 30 on the back side.

[0076] In this embodiment, VLI 60 extends along a third direction to electrically couple the front source / drain contact 70 to the corresponding back source / drain contact 82. For example, refer to... FIG. 7-FIG. 10 VLI 60 electrically couples a pair of adjacent front-side source / drain contacts 70H and 70I to a corresponding pair of adjacent back-side source / drain contacts 82H and 82I. The front-side source / drain contacts 70H and 70H are further electrically coupled to a front-side metal line 80C configured as ground VSS via front-side via contacts 78A and 78B, respectively. Similarly, the back-side source / drain contacts 82H and 82I are further electrically coupled to a back-side metal line 90G via back-side via contacts 88A and 88B, respectively, which is configured as part of a power delivery network. In this respect, the corresponding contact and interconnect structures on the front and back sides of VLI 60 and substrate 12 allow power (i.e., a reference voltage signal) to be transmitted between PND (e.g., back-side metal line 90G) and ground VSS (e.g., front-side metal line 80C).

[0077] As described herein, VLI 60 is embedded in or surrounds an extension 61 of the gate isolation structure 50A, such that VLI 60 is electrically isolated from the adjacent upper active region 22. Furthermore, since VLI 60 is disposed along a second direction between two adjacent upper active regions 22, it is arranged above and extends through a portion of the isolation structure 14 between the adjacent upper active regions 22. In various embodiments, MSC 150 has essentially no electrical contact with the front / back metal lines 80 / 90 except through VLI 60 and its corresponding front / back source / drain contacts 70 / 82 and front / back via contacts 78 / 88. In this embodiment, MSC 150 does not contain any electrical connection to the front metal line 80 configured as BL or BLB, nor does it contain any electrical connection to the back metal line 80 configured as a power supply voltage VDD or WL. Specifically, the VLI 60 is electrically coupled only to the front metal line 80C configured as ground VSS and the back metal line 90G configured as PDN.

[0078] In some embodiments, the storage device 100C may not include two active front metal lines 80A and 80E (which may be configured as word lines of the storage cell 10) extending along the respective horizontal boundary 11A of the storage cell 10, but instead includes two passive or dummy front metal lines in their location. For example, FIG. 11 The storage device 100C embodiment shown is similar to FIG. 15-FIG. 18 The storage device 100C shown is basically similar, except that two dummy (DMY) front metal lines 80F and 80G replace two active front metal lines 80A and 80E, respectively. In this respect, as FIG. 7-FIG. 10 As shown, each dummy front metal line 80F and 80G extends continuously across memory cell 10 and MSC 150 and is configured as a floating metal line not electrically coupled to any front via contact 78, thus becoming a dummy or non-active metal line for the transistors formed in the upper layer of memory cell 10. In some embodiments, since the dummy front metal lines 80F and 80G are respectively interposed between two bit lines or two complementary bit lines (e.g., front metal lines 80B / 80D) of adjacent memory cells 10, these dummy front metal lines can provide a shielding effect, helping to reduce or prevent coupling between BL or BLB.

[0079] In some embodiments, the storage device 100C may not include a single front metal line 80C configured as a ground VSS for the storage cell 10 and extending through the center of the storage cell 10 and the MSC 150, but instead includes two separate front metal lines, each configured as a ground VSS and extending along the boundary of the storage cell 10. For example, FIG. 15 to FIG. 18 The storage device 100C embodiment shown is similar to FIG. 18The storage device 100C shown is substantially similar, except that two front metal lines 80C-1 and 80C-2 (each configured as ground VSS) are provided along the horizontal boundary 11A of the storage cell 10 and are spaced apart along the second direction. Accordingly, each front metal line 80C-1 and 80C-2 is shared by two adjacent storage cells 10 arranged along the second direction.

[0080] For compatibility with front metal wires 80C-1 and 80C-2, refer to FIG. 7 to FIG. 14 The storage device 100C includes two front-side via contacts 78G and 78I—electrically coupled to corresponding ends of the front-side source / drain contact 70H—and two front-side via contacts 78H and 78J—electrically coupled to corresponding ends of the front-side source / drain contact 70I. Accordingly, VLI 60 is electrically coupled to each front-side metal line 80C-1 and 80C-2 via portions of the front-side source / drain contacts 70H and 70I, which are subsequently coupled to each front-side metal line 80C-1 and 80C-2 via corresponding front-side via contact sets 78G / 78H and 78I / 78J, respectively.

[0081] refer to FIG. 19-FIG. 22 Unlike the direct extension along a third direction, the reference voltage signal (i.e., power supply) between the back metal line 90G and the respective front metal lines 80C-1 and 80C-2 is transmitted along a two-dimensional conduction path CP2. For example, conduction path CP2 first starts from the back metal line 90G, passing through the back via contact 88B and VLI 60 along a third direction. Conduction path CP2 continues along a second direction, passing through portions of the front source / drain contacts 70H and 70I towards their respective ends. Conduction path CP2 then extends along a third direction through the front via contacts 78G / 78H and 78I / 78J to the corresponding front metal lines 80C-1 and 80C-2, respectively. In contrast, the reference... FIG. 15-FIG. 18 The one-dimensional conduction path CP1 extends vertically along the third direction from the back metal line 90G through VLI 60 and various front and back contact structures and interconnect structures to the front metal line 80C.

[0082] In some embodiments, the storage device 100C may have additional front-side interconnect structures and metal lines above the ground terminal VSS to accommodate power transmission from the rear-side PDN to the ground VSS. For example, FIG. 21 The embodiment of the storage device 100C shown is similar to FIG. 22The devices shown are basically similar, with the difference being that each front metal line 80H, 80C-1, and 80C-2 is coupled to front metal lines 92A and 92B (collectively referred to as front metal lines 92) through one or more of a plurality of front through-hole contacts 89A, 89B, 89C, 89D, 89E, and 89F (collectively referred to as front through-hole contacts 89). Since the front metal lines 92 are disposed above or vertically stacked on the front metal lines 80 along a third direction and are located in the metallization layer M1, they can be referred to as M1 metal lines; and the front through-hole contacts 89 can be referred to as V0 through-hole contacts.

[0083] In the illustrated embodiment: front-side through-hole contacts 89A and 89B are electrically coupled to the central portions of front-side metal lines 92A and 92B, respectively, and aligned with VLI 60 along a third direction; front-side through-hole contacts 89C and 89E are electrically coupled to both ends of front-side metal line 92A, respectively; front-side through-hole contacts 89D and 89F are electrically coupled to both ends of front-side metal line 92B, respectively. Correspondingly, front-side metal line 80H, extending along the first direction through the center of memory cell 10 and MSC 150, is electrically coupled to front-side metal lines 92A and 92B via front-side through-hole contacts 89A and 89B, respectively; front-side metal line 80C-1 is electrically coupled to front-side metal lines 92A and 92B via front-side through-hole contacts 89C and 89D, respectively; front-side metal line 80C-2 is electrically coupled to front-side metal lines 92A and 92B via front-side through-hole contacts 89E and 89F, respectively.

[0084] refer to FIG. 18 and FIG. 7 to FIG. 22 The reference voltage signal (i.e., power supply) between the back metal line 90G and each of the front metal lines 80C-1 and 80C-2 is transmitted along the two-dimensional conduction path CP3, which is similar to... FIG. 7-FIG. 22 The conductive path CP2 is shown. For example, conductive path CP3 first extends from the back metal line 90G along a third direction through the back via contact 88B and VLI 60, and then continues along a second direction through portions of each front source / drain contact 70H and 70I to their respective ends. However, unlike conductive path CP2, conductive path CP3 is spun into three different paths, which extend along a third direction between front source / drain contacts 78A, 78B, 78G, 78H, 78I, and 78J, corresponding front metal lines 80H, 80C-1, and 80C-2, and corresponding front via contacts 89A-89F, between front source / drain contacts 70H and 70I and their corresponding parallel-coupled front metal lines 92A and 92B. Accordingly, the reference voltage signal is transmitted from the back PDN to the front ground VSS through multiple paths, thereby reducing the overall IR voltage drop along conductive path CP3.

[0085] FIG. 5-FIG. 6 An exemplary embodiment of electrically coupled VLI 60 of MSC 150 within the array is shown to support power transfer from the PDN on the back of storage device 100C to the grounded VSS on the front. It should be noted that, although... FIG. 5-FIG. 6 Only the first storage cell 10 adjacent to the storage cell connection structure 150 is depicted (e.g., FIG. 23 The storage cells 10 of the first array portion 102A, 104A are described herein, but the details described herein also apply to the second storage cell 10 adjacent to the MSC 150 (e.g., FIG. 23 The memory cells 10 of the second array portions 102B and 104B. For example, the various upper / lower active regions 22 / 20, the front metal line 80, and the gate isolation structure 50 also extend across the second memory cell 10. Specifically, the transistors in the upper layers of the second memory cell 10 are also electrically coupled to ground VSS (configured as the front metal line 80C) in a manner similar to that shown in the first memory cell 10.

[0086] FIG. 24 This is a flowchart of part or all of a method 400 for forming or manufacturing a semiconductor device (e.g., any one of memory devices 100A-100C) according to some embodiments. It will be understood that... FIG. 5-FIG. 8 Additional operations may be performed before, during, and / or after the method 400 described in the text.

[0087] In operation 410 of method 400, a layout design for a semiconductor device is generated. Operation 410 is performed by a processing device (e.g., configured to execute instructions for generating the layout design) that is used to generate the layout design. FIG. 11 The processor 502 executes the process. In one method, a layout design is generated by placing a layout design of one or more standard cells through a user interface. In another method, the layout design is automatically generated by a processor-executed synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is presented in a Graphical Database System (GDSII) file format. In some embodiments, the layout design includes... FIG. 12 , FIG. 15 , FIG. 16 , FIG. 19 , FIG. 20 , FIG. 24 and FIG. 24 The example layouts depicted herein are any similar to those described herein, each layout depicting an embodiment of the storage device 100C described herein.

[0088] In operation 420 of method 400, a semiconductor device is manufactured based on a layout design. In some embodiments, operation 420 of method 400 includes: manufacturing at least one mask based on a layout design, and manufacturing a semiconductor device based on the at least one mask. Exemplary manufacturing processes of operation 420 may include patterning, ion implantation, deposition, etching, planarization, and combinations thereof to form a plurality of front-end process device components (e.g., active regions 20 / 22, source / drain components 24 / 26, metal gate structures 30 / 32, gate isolation structures 40, active region isolation structures 50, etc.), device-level (or mid-end process) contacts (e.g., front / back source / drain contacts 70 / 82, interlayer source / drain contacts 72, front / back gate contacts 74 / 84, etc.), interconnect structures (or back-end process structures; e.g., front / back via contacts 78 / 86 / 88, etc.), and metal lines (or back-end process structures; e.g., front / back metal lines 80 / 92 / 90, etc.).

[0089] In some embodiments, method 400 is implemented as a standalone software application executed by a processor. In some embodiments, method 400 is implemented as a component of an additional software application. In some embodiments, method 400 is implemented as a plug-in to a software application. In some embodiments, method 400 is implemented as part of a software application of an EDA tool. In some embodiments, method 400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium. In some embodiments, the layout design is generated based on a netlist created according to a schematic design.

[0090] FIG. 24This is a schematic diagram of a system 500 for designing and manufacturing IC layout designs according to some embodiments. System 500 generates or places one or more IC layout designs, as described herein. In some embodiments, system 500 manufactures one or more semiconductor devices based on the one or more IC layout designs, as described herein. System 500 includes (e.g., hardware) a processor 502 and a non-transitory computer-readable storage medium 504 encoded with (e.g., stored) computer program code 506 (e.g., a set of executable instructions). The computer-readable storage medium 504 is configured to interface with a manufacturing machine that produces the semiconductor devices. Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 508. Processor 502 is also electrically coupled to I / O interface 510 via bus 508. Network interface 512 is also electrically connected to processor 502 via bus 508. Network interface 512 is connected to network 514, enabling processor 502 and computer-readable storage medium 504 to be connected to external components via network 514. Processor 502 is configured to execute computer program code 506 encoded in computer-readable storage medium 504 so that system 500 can be used to perform some or all of the operations described in method 400.

[0091] In some embodiments, processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit. In some embodiments, computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, computer-readable storage medium 504 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0092] In some embodiments, computer-readable storage medium 504 stores computer program code 506 configured to cause system 500 to perform method 400. In some embodiments, computer-readable storage medium 504 also stores information required to perform method 400 and information generated during the performance of method 400, such as layout design 516, user interface 518, manufacturing unit 520, and / or a set of executable instructions for performing operations of method 400.

[0093] In some embodiments, computer-readable storage medium 504 stores instructions (e.g., computer program code 506) for interfacing with manufacturing equipment. The instructions (e.g., computer program code 506) enable processor 502 to generate manufacturing instructions readable by the manufacturing equipment to effectively implement method 400 during the manufacturing process.

[0094] System 500 includes an I / O interface 510. The I / O interface 510 is coupled to external circuitry. In some embodiments, the I / O interface 510 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor arrow keys for transmitting information and commands to processor 502.

[0095] System 500 also includes a network interface 512 coupled to processor 502. Network interface 512 enables system 500 to communicate with network 514, to which one or more other computer systems are connected. Network interface 512 includes a wireless network interface (such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA) or a wired network interface (such as Ethernet, USB, or IEEE-13154). In some embodiments, method 400 is implemented in two or more systems 500, and information such as layout design, user interface, and processing units is exchanged between different systems 500 via network 514.

[0096] System 500 is configured to receive layout design-related information via I / O interface 510 or network interface 512. This information is transmitted via bus 508 to processor 502 to determine a layout design for manufacturing an integrated circuit (IC). This layout design is then stored as layout design 516 in computer-readable storage medium 504. System 500 is configured to receive user interface-related information via I / O interface 510 or network interface 512. This information is stored as user interface 518 in computer-readable storage medium 504. System 500 is configured to receive manufacturing unit-related information via I / O interface 510 or network interface 512. This information is stored as manufacturing unit 520 in computer-readable storage medium 504. In some embodiments, manufacturing unit 520 contains manufacturing information used by system 500.

[0097] In some embodiments, method 400 is implemented by a manufacturing apparatus to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs generated by system 500. In some embodiments, system 500 includes manufacturing equipment (e.g., manufacturing tool 522) that fabricates the integrated circuit using a set of masks fabricated based on one or more layout designs of this disclosure. FIG. 25 The integrated circuit layout design generated by System 500 is smaller than that of other methods. In some embodiments, FIG. 25The system 500 generates semiconductor device layout designs that occupy less area than other methods.

[0098] FIG. 25 This is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 600 and its associated IC manufacturing process according to at least one embodiment of the present disclosure.

[0099] exist FIG. 26 In this IC manufacturing system 600, entities such as design room 620, mask room 630, and IC manufacturing plant / manufacturer (“fab”) 640 interact in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices (semiconductor devices) 660 (e.g., corresponding to any memory device 100A-100C). The entities in the IC manufacturing system 600 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 620, mask room 630, and IC manufacturing plant 640 are owned by a single company. In some embodiments, two or more of the design room 620, mask room 630, and IC manufacturing plant 640 coexist in a shared facility and use shared resources.

[0100] Design studio (or design team) 620 generates IC design layout 622. IC design layout 622 includes various geometric patterns designed for IC device 660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 660 to be manufactured. Various layers are combined to form various IC components. For example, a portion of IC design layout 622 includes various IC components such as active regions, gate structures, source / drain regions, interconnect structures, and openings for bonding pads, which will be formed on a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design studio 620 implements appropriate design procedures to form IC design layout 622. Design procedures include one or more of logic design, physical design, or place-and-route. IC design layout 622 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 622 may be represented in GDSII file format or DFII file format.

[0101] Mask chamber 630 includes mask data preparation 632 and mask fabrication 634. Mask chamber 630 uses an IC design layout 622 to fabricate one or more masks, which will be used to fabricate various layers of an IC device 660 according to the IC design layout 622. Mask chamber 630 performs mask data preparation 632, in which the IC design layout 622 is converted into a representative data file ("RDF"). Mask data preparation 632 provides the RDF to mask fabrication 634. Mask fabrication 634 includes a mask writer. The mask writer converts the RDF into an image on a substrate (such as a mask or semiconductor wafer). The design layout is manipulated by mask data preparation 632 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 640. FIG. 26 In this embodiment, mask data preparation 632 and mask manufacturing 634 are shown as separate elements. In some embodiments, mask data preparation 632 and mask manufacturing 634 may be collectively referred to as mask data preparation.

[0102] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 622. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0103] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout processed by OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 634, which may undo some modifications performed by OPC to satisfy the mask creation rules.

[0104] In some embodiments, mask data preparation 632 includes a lithography process check (LPC), which simulates the process performed by an IC manufacturing plant 640 to manufacture an IC device 660. The LPC simulates this process based on an IC design layout 622 to create a simulated manufactured device, such as IC device 660. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after the LPC creates a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 622.

[0105] It should be understood that, for clarity, the above description of mask data preparation 632 has been simplified. In some embodiments, mask data preparation 632 includes additional features, such as logical operations (LOPs) that modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 622 during mask data preparation 632 can be performed in various different sequences.

[0106] Following mask data preparation 632 and during mask fabrication 634, a mask or mask set is fabricated based on the modified integrated circuit design layout. In some embodiments, an electron beam or multi-electron beam mechanism is used to pattern the mask (photomask or mask slab) according to the modified integrated circuit design layout. The mask can be formed using various techniques: in some embodiments, a binary technique is used to fabricate the mask, where the mask pattern includes opaque and transparent regions; when a radiation beam, such as an ultraviolet beam, irradiates a photosensitive material layer (e.g., photoresist) coated on the wafer, the opaque regions block the beam while the transparent regions allow the beam to pass through. One example is a binary mask, which consists of a transparent substrate (such as fused silica) and a light-shielding material (such as chromium) coated on the opaque regions of the mask. Another example is a phase-shifting technique used to fabricate the mask, in which the various features of the mask pattern are configured to have an appropriate phase difference to improve resolution and imaging quality. In specific implementations, the phase-shifting mask can employ an attenuating or alternating structure. The mask produced by mask manufacturing 634 is used in a variety of processes, such as forming doped regions within a semiconductor wafer in an ion implantation process, forming etched regions within a semiconductor wafer in an etching process, and / or other applicable processes.

[0107] IC manufacturing plant 640 is an integrated circuit manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different integrated circuit products. In some embodiments, IC manufacturing plant 640 is a semiconductor foundry. For example, there may be a first manufacturing facility for front-end manufacturing of multiple integrated circuit products (e.g., active regions 20 / 22, source / drain components 24 / 26, metal gate structures 30 / 32, gate isolation structures 40, active region isolation structures 50, etc.), a second manufacturing facility for providing mid-end manufacturing for interconnects of integrated circuit products (e.g., front / back source / drain contacts 70 / 82, interlayer source / drain contacts 72, front / back gate contacts 74 / 84, etc.), a third manufacturing facility for providing back-end manufacturing for interconnects and packaging of integrated circuit products (e.g., front / back via contacts 78 / 86 / 88, front / back metal lines 80 / 92 / 90, etc.), and a fourth manufacturing facility for providing other services to the foundry entity.

[0108] IC manufacturing plant 640 uses a mask manufactured by mask chamber 630 to manufacture IC device 660. Therefore, IC manufacturing plant 640 uses IC design layout 622 at least indirectly to manufacture IC device 660. In some embodiments, IC manufacturing plant 640 uses a mask to manufacture semiconductor wafer 642 to form IC device 660. Semiconductor wafer 642 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric features, multilevel interconnect structures, etc. (formed in subsequent manufacturing steps).

[0109] IC manufacturing system 600 is shown having a design room 620, a mask room 630, and an IC manufacturing plant 640 as separate components or entities. However, it should be understood that one or more of the design room 620, mask room 630, and IC manufacturing plant 640 may be part of the same component or entity.

[0110] FIG. 27 A flowchart of a method 700 for forming a semiconductor device (e.g., any of the memory devices 100A-100C described above) according to one or more embodiments of the present disclosure is shown. This method may be implemented in part or in whole. It should be noted that method 700 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be understood that additional operations may be performed before, during, and after method 700, and some other operations may be described herein only briefly.

[0111] refer to FIG. 28-FIG. 33In operation 702, components of a memory device (e.g., any of memory devices 100A-100C) are formed on the front side of a substrate (e.g., substrate 12). The memory device includes a first memory array portion (e.g., first array portion 102A, 104A), a second memory array portion (e.g., second array portion 102B, 104B), and an intermediate band cell array (MSC array; e.g., MSC array 152A, 154A) disposed along a first direction. The memory device also includes a plurality of metal gate structures (e.g., metal gate structures 30, 32) that engage vertically stacked active regions (e.g., lower active region 20 and upper active region 22) extending across the first memory array portion, the second memory array portion, and the MSC array. In some embodiments, each memory array portion includes a plurality of memory cells (e.g., memory cell 10), and the MSC array includes a plurality of MSC cells, each MSC cell aligned with an adjacent memory cell along the first direction.

[0112] In some embodiments, a portion or all of each memory cell corresponds to a semiconductor memory device 900 (hereinafter referred to as device 900) as described below, which may be manufactured by method 800 according to one or more embodiments of the present disclosure. In this regard, consistent with the description of memory devices 100A-100C and device 900, each of the memory devices provided herein includes a plurality of upper transistors (e.g., upper transistor 910U) stacked vertically above a plurality of lower transistors (e.g., lower transistor 910L) along a third direction.

[0113] FIG. 27 A flowchart of a method 800 for forming device 900 is shown. In some embodiments, method 800 may be implemented at operation 702 described above. It should be noted that method 800 is merely illustrative and not intended to limit the scope of this disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and after method 800, and only some other operations may be briefly described herein. In some embodiments, the operation of method 800 may be related to, as... FIG. 29 The perspective and sectional views of device 900 shown (discussed in detail below) are associated at different manufacturing stages.

[0114] Reference FIG. 27 and FIG. 29At operation 802, a multilayer structure (e.g., multilayer structure 922') of alternating first semiconductor layers (e.g., first semiconductor layers or nanosheets 924'A, 924'B) and second semiconductor layers (e.g., second semiconductor layers or nanosheets 926'U, 926'L) is formed over a substrate (e.g., substrate 920). Specifically, the multilayer structure includes: an upper portion having alternating first semiconductor material (e.g., first semiconductor layer 924'A) and second semiconductor material (e.g., second semiconductor layer 926'U); a lower portion having alternating first semiconductor material and second semiconductor material (e.g., second semiconductor layer 926'L); and an intermediate layer of a third semiconductor material (e.g., intermediate first semiconductor layer 924'B) with a composition different from the first and second semiconductor materials. This intermediate layer of the third semiconductor material is sandwiched between two second semiconductor material layers (e.g., intermediate second semiconductor layer 926'M) configured as dummy layers.

[0115] In operation 804, multiple fins (e.g., fin 928; alternatively referred to as active regions) are defined in the multilayer structure by one or more etching processes. Isolation structures (e.g., isolation structure 932) may be formed above the substrate and between the fins. Subsequently, referring to... FIG. 27 and FIG. 30 In operation 806, a sacrificial gate structure (e.g., sacrificial gate structure 942) is formed over the fin. The structure includes a sacrificial gate dielectric layer (e.g., sacrificial gate dielectric layer 936), a sacrificial gate electrode layer (e.g., sacrificial gate electrode layer 938), and a mask structure (e.g., mask structure 940).

[0116] Reference FIG. 27 and FIG. 31 In operation 808, corresponding spacers (e.g., spacer 944) are formed on the sidewalls of the sacrificial gate structure 942. In operation 810, trenches (e.g., trench 946; also referred to as source / drain trenches) are formed within each fin. Subsequently, in operation 812, the first semiconductor material (e.g., the exposed edge portions of each first semiconductor layer 924A') and the entire third semiconductor material (e.g., the intermediate first semiconductor layer 924B') within the trench are recessed to form an intermediate opening. During the recessing process in operation 812, the second semiconductor material (e.g., second semiconductor layers 926'U, 926'L) remains substantially intact. Next, in operation 814, dielectric material is deposited within the trench to form internal spacers (e.g., internal spacer 954) and internal isolation structures (e.g., internal isolation structure 956).

[0117] refer to FIG. 27 and FIG. 32In operation 816, a lower source / drain epitaxial structure (e.g., source / drain epitaxial structure 962L) and an upper source / drain epitaxial structure (e.g., source / drain epitaxial structure 962U) are formed on the internal spacers and internal isolation structures within the trench, collectively referred to as source / drain epitaxial structures. In some embodiments, before forming the upper epitaxial structure, a pad (e.g., pad 963) and a dielectric material (e.g., dielectric material 968) are formed on the upper surface of the lower source / drain epitaxial structure. Subsequently, in operation 818, an interlayer dielectric layer (e.g., ILD layer 972) is formed over the source / drain epitaxial structure. In some embodiments, before forming the interlayer dielectric layer, a contact etch stop layer (e.g., CESL 970) is formed over the source / drain epitaxial structure. A chemical mechanical polishing (CMP) process is then performed to planarize the contact etch stop layer and / or the interlayer dielectric layer.

[0118] Then refer to FIG. 28 and FIG. 27 In operation 820, the dummy gate structure and the remaining portion of the first semiconductor layer (e.g., the remaining portion of the first semiconductor layer 924A') are replaced with metal gate structures. Each metal gate structure includes a gate dielectric layer (e.g., gate dielectric layer 978) and gate electrodes (e.g., gate electrodes 980U and 980L). In the illustrated embodiment, the gate structure formed in the upper portion of the device 900 (i.e., above the internal isolation structure 956) is called the upper gate structure (e.g., upper gate structure 982U), each of which includes a gate electrode 980U; while the gate structure formed in the lower portion of the device 900 (i.e., below the internal isolation structure 956) is called the lower gate structure (e.g., lower gate structure 982L), each of which includes a gate electrode 980L.

[0119] FIG. 29 A perspective view of part or all of a device 900 according to some embodiments of the present disclosure is schematically shown. The device 900 may be employed with reference to... FIG. 28 The method 800 is used to manufacture the device 900. The device 900 may correspond to a portion of memory cell 10 in any memory device 100A-100C described herein. The device 900 includes a multilayer structure 910 comprising a lower (or first) transistor 910L and an upper (or second) transistor 910U. The lower transistor 910L is disposed on a substrate 920 (see [link to documentation]). FIG. 28 ).like FIG. 28 As shown, the upper transistor 910U is physically stacked above the lower transistor 910L along the third direction. In this configuration, the lower transistor 910L is disposed between the substrate 920 and the upper transistor 910U along the third direction.

[0120] In some embodiments, the upper transistor 910U and the lower transistor 910L have different conductivity types. In one such example, the upper transistor 910U is an NMOS device and the lower transistor 910L is a PMOS device, and the multilayer structure 910 is called a P-on-N structure (e.g., a P-on-N CFET). In another such example, the upper transistor 910U is a PMOS transistor and the lower transistor 910L is an NMOS transistor, and the multilayer structure 910 is called an N-on-P structure (e.g., an N-on-P CFET). In some embodiments, the upper transistor 910U and the lower transistor 910L have the same conductivity type, for example, both are n-type (forming an N-on-N structure) or both are p-type (forming a P-on-P structure). In this embodiment, the upper transistor 910U may correspond to one of PD1 or PD2 of memory cell 10 in any memory device 100A-100C, and the lower transistor 910L may correspond to one of PU1 or PU2 of memory cell 10 in any memory device 100A-100C.

[0121] In some embodiments, both the upper transistor 910U and the lower transistor 910L are configured as multi-channel devices, such as nanosheet transistors, nanowire transistors, etc. In the example configuration described herein, the upper transistor 910U and the lower transistor 910L are nanosheet transistors. Other device configurations may also be applied to embodiments of this disclosure.

[0122] The upper transistor 910U includes a metal gate structure 982U and source / drain epitaxial structures 962U located on opposite sides of the metal gate structure 982U along a first direction. The metal gate structure 982U extends or elongates along a second direction. The first, second, and third directions are transverse to each other. In some embodiments, the first, second, and third directions are perpendicular to each other. The upper transistor 910U also includes a channel region configured with nanosheets 926'U (also referred to as a second semiconductor layer 926'U), which extend along the first direction and connect to the source / drain epitaxial structures 962U. In some embodiments, the nanosheets 926'U correspond to the individual nanosheets of the upper active region 22. FIG. 29 In the example configuration, the upper transistor 910U comprises two nanosheets 926'U. Other numbers of nanosheets per transistor are also within the scope of the embodiments. The upper transistor 910U includes a gate dielectric layer 978 extending around each nanosheet 926'U, which electrically isolates the metal gate structure 982U from the nanosheets 926'U. The metal gate structure 982U extends around the gate dielectric layer 978 and the nanosheets 926'U in a gate all-around (GAA) configuration. Other gate configurations are also within the scope of the embodiments.

[0123] The lower transistor 910L includes a metal gate structure 982L, a source / drain epitaxial structure 962L, a channel region configured with nanosheets 926'L (also referred to as a second semiconductor layer 926'L), and a gate dielectric layer 978 extending around each nanosheet 926'L. The metal gate structure 982L, the source / drain epitaxial structure 962L, and the nanosheets 926'L are perpendicularly aligned with the metal gate structure 982U, the source / drain epitaxial structure 962U, and the nanosheets 926'U, respectively. The metal gate structure 982U, the source / drain epitaxial structure 962U, and the nanosheets 926'U overlap with the metal gate structure 982L, the source / drain epitaxial structure 962L, and the nanosheets 926'L respectively along a third direction. FIG. 29 In the example configuration, the source / drain epitaxial structures 962U and 962L comprise epitaxial structures with different conductivity types. For example, source / drain epitaxial structure 962U comprises an n-type doped epitaxial structure, and source / drain epitaxial structure 962L comprises a p-type doped epitaxial structure. In some embodiments, source / drain epitaxial structures 962U and 962L comprise epitaxial structures with the same conductivity type.

[0124] In some embodiments, nanosheets 926'L correspond to the nanosheets of the lower active region 20, the metal gate structure 982L and the gate dielectric layer 978 together correspond to the metal gate structure 30, and the source / drain epitaxial structure 962L corresponds to the source / drain component 24. Similarly, nanosheets 926'U correspond to the nanosheets of the upper active region 22, the metal gate structure 982U and the gate dielectric layer 978 together correspond to the metal gate structure 32, and the source / drain epitaxial structure 962U corresponds to the source / drain component 26.

[0125] The multilayer structure 910 also includes an intermediate layer 990 located between the metal gate structure 982U and the metal gate structure 982L. ​​In some embodiments, the intermediate layer 990 includes a dielectric layer and is configured as a gate isolation structure (similar to gate isolation structures 160 and 280) to electrically isolate the metal gate structure 982U and the metal gate structure 982L. ​​This configuration is referred to as an isolated gate configuration, wherein the metal gate structure 982U and the metal gate structure 982L can be controlled independently of each other.

[0126] As can be seen in the CFET structures (e.g., memory devices 100A-100C) provided herein, stacking a transistor (e.g., PD1 of memory device 10) on top of another FET (e.g., PU1 of memory device 10) can save approximately 50% of the required chip area compared to other methods that do not stack semiconductor devices. In some embodiments, IC devices comprising multiple device stacks can be fabricated using CFET processes with minimal or no changes to the fabrication process.

[0127] FIG. 28This is a schematic perspective view of device 900 according to some embodiments. Device 900 includes a plurality of device stacks formed on a substrate 920 corresponding to substrate 12. In some embodiments, substrate 920 is a semiconductor substrate. In some embodiments, substrate 920 includes a single-crystal semiconductor layer located at least partially on its surface. Substrate 920 may have a composition similar to that of the substrate of the aforementioned device 200.

[0128] The multilayer structure 922' is formed on the substrate 920. FIG. 28 The multilayer structure 922' shown is in the state after the fin structure has been formed as described herein. This multilayer structure 922' includes alternating first semiconductor layers 924'A, 924'B and a second semiconductor layer 926'U (i.e., FIG. 29 The nanosheets 926'U and 926'L. The second semiconductor layers 926'U and 926'L correspond to FIG. 30 For simplicity, the nanosheets are referred to using the same reference numerals as those in the accompanying drawings. The first semiconductor layers 924'A, 924'B and the second semiconductor layers 926'U, 926'L comprise semiconductor materials with different etch selectivity and / or oxidation rates. For example, in some embodiments, the first semiconductor layers 924'A, 924'B comprise silicon-germanium (SiGe), and the second semiconductor layers 926'U, 926'L comprise silicon (Si). In some embodiments, the first semiconductor layers 924'A, 924'B have different germanium concentrations, resulting in different etch selectivity and / or oxidation rates therebetween. In some embodiments, the first and second semiconductor layers 924'A, 924'B, 926'U, 926'L are formed by a deposition process, such as epitaxial growth. Specifically, the epitaxial growth of the layers of the multilayer structure 922' is achieved by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0129] After forming the multilayer structure 922', fins 928 are formed. In some embodiments, each fin 928 corresponds to a pair of lower active regions 20 and upper active regions 22 vertically aligned along a third direction. Each fin 928 includes a substrate portion 920' of the substrate 920 and a portion 934 of the multilayer structure 922'. The portion 934 of the multilayer structure 922' is sometimes referred to as the semiconductor layer stack 934. In some embodiments, the fins 928 are fabricated using suitable processes, such as dual patterning or multiple patterning processes. For example, in one or more embodiments, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed on the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fins 928 are patterned using the remaining spacers by etching the multilayer structure 922' and the substrate 920. Exemplary etching processes include, but are not limited to, dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. FIG. 30 Two fins 928 are shown; however, the number of fins is not limited to two. In this embodiment, the fins 928 extend along a first direction and span multiple portions above the substrate 920, such as a first array portion (e.g., first array portion 102A or 104A), a second array portion (e.g., second array portion 102B or 104B), and an MSC array (e.g., MSC arrays 152A, 152B, 152C, 154A, 154B, or 154C).

[0130] In some embodiments, an isolation structure 932 comprising insulating material is formed over a substrate 920 and within a trench (not shown) between fins 928. In some embodiments, isolation structure 932 corresponds to isolation structure 14. For example, insulating material is deposited over the substrate 920 and fins 928. Exemplary insulating materials for isolation structure 932 include, but are not limited to, silicon oxide (SiO2), fluorine-doped silicate glass (FSG), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), low dielectric constant materials, etc., or combinations thereof. The insulating material is deposited using a suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). A planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is then performed to expose the top of the fins 928 from the insulating material. A portion of the insulating material between adjacent fins 928 is removed. The remaining insulating material is used to configure isolation structure 932. Partial removal of the insulating material includes dry etching, wet etching, etc.

[0131] In some embodiments, a sacrificial (dummy) gate dielectric layer 936, a sacrificial (dummy) gate electrode layer 938, and a mask structure 940 are deposited over the isolation structure 932 and the fin 928. In some embodiments, the sacrificial gate dielectric layer 936 comprises one or more layers of dielectric material, such as SiO2, SiN, high dielectric constant materials, or combinations thereof. In some embodiments, the sacrificial gate dielectric layer 936 is deposited using a CVD process, a sub-atmospheric CVD process, an FCVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or other suitable processes. In at least one embodiment, the sacrificial gate electrode layer 938 comprises polysilicon. In some embodiments, the mask structure 940 comprises a multilayer structure. In some embodiments, the sacrificial gate electrode layer 938 and the mask structure 940 are formed by one or more processes, such as layer deposition processes, for example, CVD (including LPCVD and PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, to fabricate the device 900.

[0132] refer to FIG. 30 The sacrificial gate structure 942 is formed by performing one or more patterning and / or etching processes on the deposited sacrificial gate dielectric layer 936, sacrificial gate electrode layer 938, and mask structure 940. Example patterning processes include photolithography. Example etching processes include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. Each sacrificial gate structure 942 includes a portion of each of the sacrificial gate dielectric layer 936, sacrificial gate electrode layer 938, and mask structure 940. The sacrificial gate structure 942 extends or elongates along a second direction. FIG. 30 The diagram shows three sacrificial gate structures 942; however, the number of sacrificial gate structures 942 is not limited to two.

[0133] Spacer 944 is formed on the sidewall of sacrificial gate structure 942. For example, spacer 944 is formed by first depositing a conformal layer, which is then etched back to form spacer 944. Spacer 944 includes a dielectric material such as SiO2, SiN, silicon carbide, silicon oxycarbide, SiON, SiCN, SiOCN, the like, or combinations thereof. In some embodiments, spacer 944 includes multiple layers.

[0134] Exposed portions of the semiconductor layer stack 934 of fin 928 that are not covered by the sacrificial gate structure 942 and spacer 944 are selectively removed, for example by one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof, to form trench 946. FIG. 31In this configuration, the bottommost layer of the second semiconductor layer 926'U and the topmost layer of the second semiconductor layer 926'L are designated as the intermediate second semiconductor layer 926'M, which is sandwiched between the intermediate first semiconductor layer 924'B. The intermediate second semiconductor layer 926'M and the intermediate first semiconductor layer 924'B are not configured to form the channel regions of the upper transistor 910U and the lower transistor 910L. The edge portions of the first semiconductor layers 924'A, 924'B and the second semiconductor layers 926'U, 926'L, 926'M are exposed in the trench 946. The trench 946 also exposes a portion of the substrate portion 920', and obtains a... FIG. 31 The device shown is 900.

[0135] refer to FIG. 31 The exposed edge portion of the first semiconductor layer 924'A is replaced. In some embodiments, removal includes a selective wet etching process. The selective wet etching process further completely (or substantially completely) removes the first semiconductor layer 924'B in the middle of the semiconductor layer stack 934. For example, in an embodiment where the first semiconductor layers 924'A, 924'B comprise SiGe and the second semiconductor layers 926'U, 926'L, 926'M comprise Si, the selective wet etching is configured to etch the first semiconductor layer 924'B at the highest etch rate, etch the first semiconductor layer 924'A at a second high etch rate, and etch the second semiconductor layers 926'U, 926'L, 926'M at the slowest etch rate. As a result, the exposed edge portion of each first semiconductor layer 924'A and the entirety (or substantially the entirety) of each first semiconductor layer 924'B are removed, while the second semiconductor layers 926'U, 926'L, 926'M remain substantially unchanged.

[0136] Dielectric material is deposited over and inside the space formed by removing the edge portion of the first semiconductor layer 924'B and partially removing the edge portion of the first semiconductor layer 924'A. Internal spacers 954 are configured to fill the space formed by the partial removal of the edge portion of the first semiconductor layer 924'A. Internal isolation structures 956 are configured to fill the space formed by the removal of the first semiconductor layer 924'B. Examples of dielectric materials forming the internal spacers 954 and internal isolation structures 956 include, but are not limited to, low-k dielectric materials (such as SiO2, SiN, SiCN, SiOC, or SiOCN) or high-k dielectric materials (such as HfO2, ZrOx, ZrAlOx, HfAlOx, HfSiOx, AlOx, or other suitable dielectric materials). In some embodiments, the internal spacers 954 and internal isolation structures 956 comprise different dielectric materials. In an exemplary process, a conformal dielectric layer is deposited by a conformal deposition process (such as atomic layer deposition), followed by anisotropic etching to remove portions of the conformal layer other than the internal spacer 954 and the internal isolation structure 956.

[0137] The source / drain epitaxial structure 962L is formed above and in contact with the exposed portion of the substrate portion 920' and the exposed edge portion of the second semiconductor layer 926'L. FIG. 31 In the example configuration shown, the source / drain epitaxial structure 962L includes an epitaxial structure, also referred to herein as source / drain epitaxial structure 962L. In some embodiments, similar to any of the devices 100A-100C described herein, the source / drain epitaxial structure 962L includes one or more layers of silicon-germanium doped with the p-type dopant described herein to configure the lower transistor 910L as a PMOS transistor. In some embodiments, the epitaxial structure 962L includes one or more layers of silicon or silicon carbide doped with the n-type dopant described herein to configure the lower transistor 910L as an NMOS transistor. Exemplary epitaxial growth processes for growing the source / drain epitaxial structure 962L include, but are not limited to, CVD, ALD, and MBE. In some embodiments, after the source / drain epitaxial structure 962L is grown to a height higher than the uppermost second semiconductor layer 926'L, its top is partially removed (e.g., by dry etching or wet etching), so that the upper surface of the remaining source / drain epitaxial structure 962L is flush with the uppermost first semiconductor layer 924'A immediately below the lower middle second semiconductor layer 926'M, such as... FIG. 31 As shown.

[0138] Pad 963 is formed at least on the upper surface of the source / drain epitaxial structure 962L, the exposed side of the intermediate second semiconductor layer 926'M, and the internal isolation structure 356. In some embodiments, pad 963 comprises silicon. In example processes, pad 963 is a conformal layer formed by a conformal process (such as an ALD process).

[0139] Dielectric material 968 is formed above pad 963 and source / drain epitaxial structure 962L. In some embodiments, dielectric material 968 comprises the same material as isolation structure 932 and / or is formed by the same method as isolation structure 932. Pad 963 and dielectric material 968 are removed outside trench 946 and partially removed inside trench 946 (e.g., by dry etching or wet etching). As a result, the upper surfaces of pad 963 and dielectric material 968 are at a horizontal plane immediately above the upper intermediate second semiconductor layer 926'M and the lowermost first semiconductor layer 924'A, as shown. FIG. 31 As shown. The pad 963 and dielectric material 968 configure an isolation structure between the source / drain epitaxial structure 962L and the source / drain epitaxial structure 962U that will subsequently be formed thereon.

[0140] A source / drain epitaxial structure 962U is formed and contacted on the upper surface of the pad 963 and the dielectric material 968, as well as the exposed edge portion of the second semiconductor layer 926'U.FIG. 31 In the example configuration, the source / drain epitaxial structure 962U includes an epitaxial structure, sometimes referred to as source / drain epitaxial structure 962U. In some embodiments, the conductivity type of the source / drain epitaxial structure 962U is different from that of the source / drain epitaxial structure 962L. In some embodiments, the source / drain epitaxial structure 962U is fabricated using the same manufacturing process as the source / drain epitaxial structure 962L. In at least one embodiment, the source / drain epitaxial structure 962U has the same configuration as the source / drain epitaxial structure 962L, such as the same dimensions, shape, height, and material. In some embodiments, similar to any of the devices 100A-100C described herein, when the source / drain epitaxial structure 962L includes one or more silicon-germanium layers doped with p-type dopant to configure a PMOS transistor, the source / drain epitaxial structure 926'U includes one or more silicon layers or silicon carbide layers doped with n-type dopant to configure an NMOS transistor. In some embodiments, when the source / drain epitaxial structure 962L includes one or more silicon or silicon carbide layers doped with n-type dopant to configure an NMOS transistor, the source / drain epitaxial structure 926'U includes one or more silicon-germanium layers doped with p-type dopant to configure a PMOS transistor.

[0141] In some embodiments, the source / drain epitaxial structure 962U is grown to a height higher than the sacrificial gate dielectric layer 936, and then the top portion of the source / drain epitaxial structure 962U is partially removed, for example by dry etching or wet etching, such that the upper surface of the remaining source / drain epitaxial structure 962U is at the level of the sacrificial gate dielectric layer 936, as shown below. FIG. 32 As shown. This is an example, and the height of the source / drain epitaxial structure 962U can be controlled according to application and / or process requirements.

[0142] A contact etch stop layer (CESL) 970 is formed over the source / drain epitaxial structure 962U. Examples of materials for CESL 970 include, but are not limited to, silicon nitride, silicon carbonitride, silicon oxynitride, carbonitride, silicon oxide, silicon carbide, the like, or combinations thereof. CESL 970 is formed using CVD, PECVD, ALD, or any suitable deposition technique.

[0143] ILD 972 is formed on top of CESL 970. Example materials for ILD layer 972 include, but are not limited to, tetraethoxysilane (TEOS) oxide, undoped silicate glass, or silicon-doped oxides such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. ILD layer 972 is deposited using a PECVD process or other suitable deposition techniques to achieve the desired effect. FIG. 28 The device shown is 900.

[0144] refer to FIG. 26 A planarization process, such as a CMP process, is performed to remove the mask structure 940 and expose the sacrificial gate electrode layer 938. This planarization process also removes portions of the ILD layer 972 and CESL 970. The exposed sacrificial gate electrode layer 938 and sacrificial gate dielectric layer 936 are removed, for example, by one or more suitable processes, such as dry etching, wet etching, or a combination thereof.

[0145] Subsequently, the first semiconductor layer 924'A is removed, for example by any suitable process, such as dry etching, wet etching, or a combination thereof. Removing the first semiconductor layer 924'A exposes the internal spacer 954 and the second semiconductor layers 926'U, 926'L, forming spaces between and around the exposed portions of the second semiconductor layers 926'U, 926'L not covered by the internal spacer 954. The exposed portions of the second semiconductor layers 926'U, 926'L are configured as follows: FIG. 7 The nanosheets 926'U and 926'L have a second semiconductor layer 926'M and an internal isolation structure 956 covered by a pad 963 and a dielectric material 968, and are substantially unaffected during the removal of the first semiconductor layer 924'A.

[0146] A gate dielectric layer 978 is formed on and around the nanosheets 926'U and 926'L. In some embodiments, the gate dielectric layer 978 comprises the same material as the sacrificial gate dielectric layer 936. In some embodiments, the gate dielectric layer 978 comprises a high-k dielectric material. In some embodiments, the gate dielectric layer 978 is formed by a conformal process, such as an ALD process.

[0147] Gate electrodes 980U are formed on and around the gate dielectric layer 978 and nanosheets 926'U and 926'L. Gate electrodes 980U surround each nanosheet 926'U, i.e., are disposed above the internal isolation structure 956, and are configured to form each upper metal gate structure 982U. Gate electrodes 980L surround each nanosheet 926'L, i.e., are disposed below the internal isolation structure 956, and are configured to form each lower metal gate structure 982L. In some embodiments, gate electrodes 980U and 980L each comprise, but are not limited to, polycrystalline silicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), nickel silicide, cobalt silicide, tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium aluminum alloy (TiAl), titanium tantalum nitride (TiTaN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, and combinations thereof. In some embodiments, the gate electrode material comprises one or more work function metals. Exemplary processes for depositing the gate electrode material include, but are not limited to, PVD, CVD, ALD, electroplating, or other suitable methods.

[0148] In some embodiments, gate electrode 980U and gate electrode 980L are each configured to form a corresponding nanosheet structure, and the upper gate structure 982U and the lower gate structure 982L can be partially separated from each other by an intermediate second semiconductor layer 926'M and an internal isolation structure 956. In some embodiments, the combination of the intermediate second semiconductor layer 926'M and the internal isolation structure 956 corresponds to an intermediate layer 990 formed by the dielectric material in the isolated gate configuration. The formation of gate electrode 980U and gate electrode 980L completes the fabrication of upper transistor 910U and lower transistor 910L in the front-end process (FEOL).

[0149] Continue with operation 704 of method 700, refer to... FIG. 8 One or more metal gate structures in the memory device are replaced with a first isolation structure (e.g., active region isolation structure 40), which truncates or isolates vertically stacked active regions. For example, refer to FIG. 7 and FIG. 8 The metal gate structure 30 in the upper layer and the corresponding metal gate structure 32 in the lower layer, located near the vertical boundary 11B between the memory cell 10 and the MSC 150, are replaced by active region isolation structures 40A and 40B, respectively. In this embodiment, the vertically stacked active regions and the first isolation structure continuously span the memory cells of the memory array portion and the MSC disposed therebetween.

[0150] In some embodiments, replacing the metal gate structure includes forming a patterned mask over a substrate, wherein the patterned mask exposes the metal gate structure to be removed. The patterned mask may include a photoresist layer capable of being patterned using photolithography. Subsequently, the exposed metal gate structure is removed by a suitable etching process (e.g., dry etching, wet etching, reactive ion etching (RIE), or other suitable processes) to form a trench. The patterned mask can then be removed by any suitable method (e.g., plasma ashing or photoresist stripping). A dielectric layer comprising a suitable material (e.g., SiO2, SiN, combinations thereof, or other suitable materials) is then deposited in the trench using a suitable deposition process (e.g., CVD, ALD, PVD, combinations thereof, or other suitable processes). The dielectric layer is planarized using a CMP process to form a first isolation structure substantially coplanar with the metal gate structure.

[0151] At operation 706, a second isolation structure (e.g., gate isolation structure 50) is formed above the metal gate structure and the first isolation structure. This second isolation structure cuts off or separates the metal gate structures in the upper and lower layers. In some embodiments, each of the second isolation structures extends across the memory array portion and the MSC along a first direction and is positioned between two adjacent active regions along a second direction. For example, refer to... FIG. 7-FIG. 10 and FIG. 34-FIG. 36 Each gate isolation structure 50 is disposed above the isolation structure 14 and is located between two adjacent upper active regions 20 and lower active regions 22, thereby cutting the corresponding metal gate structures 30 and 32 into multiple parts arranged along the second direction.

[0152] In operation 708, a through-hole structure (e.g., VLI60) is formed in a portion of a second isolation structure within the MSC. This through-hole structure extends through the second isolation structure in a third direction, thereby embedding itself in or being surrounded by the second isolation structure. For example, see reference... FIG. 7 VLI 60 is formed in or above an extension 61 of the gate isolation structure 50A and extends vertically between the back metal line 90G and the front metal line 80C in a third direction.

[0153] In some embodiments, the via structure and the second isolation structure are formed simultaneously. For example, forming the second isolation structure and the via structure includes: removing portions of the metal gate structure and the isolation structure above the substrate to form a trench extending along a first direction and located between two adjacent active regions. In this embodiment, the trench includes an extension portion whose height along a second direction is greater than the height of the portion of the trench outside the extension portion. Subsequently, a dielectric layer comprising a suitable dielectric material similar to the first isolation structure is deposited in the trench to partially fill the extension portion of the trench. Thereafter, a conductive material is deposited over the trench to completely fill the extension portion, forming a via structure surrounded by the dielectric layer. Any portions of the dielectric and conductive materials are then planarized using one or more CMP processes to form the via structure formed in the extension portion of the trench.

[0154] Taking storage device 100C as an example, FIG. 34 Each of these depicts a portion of the layout of the MSC 150 in a top view of the front side of substrate 12, similar to... FIG. 35 The view. In some embodiments, reference FIG. 36 The formation of the gate isolation structure 50 and VLI 60 includes patterning the metal gate structure 32 and the isolation structure 14 using a series of photolithography and etching techniques to form a trench 48, similar to the techniques described above for forming the first isolation structure. The trench 48 extends into the isolation structure 14 along a third direction. The trench 48 includes an extension 57 having a height H2 along a second direction. The portion of the trench 48 outside the extending trench has a height H3, which is generally less than the height H2.

[0155] refer to FIG. 33 A dielectric layer 62 is deposited in the trench 48, including an extension 57. The dielectric layer 62 may include any suitable dielectric material, such as SiO2, SiN, or combinations thereof. In some embodiments, the deposition process is an isotropic and conformal deposition process implemented using CVD or any other suitable method. Due to the difference between height H2 and height H3, the deposited dielectric layer 62 first fills the portion of the trench 48 outside the extension 57, leaving a cavity 59 in the extension 57 surrounded by the conformal dielectric layer 62.

[0156] refer to FIG. 7-FIG. 10A conductive layer 63 is deposited on trench 48 to completely fill cavity 59. The conductive layer 63 may comprise any suitable conductive material, such as W, Cu, Co, Ru, Al, Ti, Ta, TiN, TaN, Pt, the like, or combinations thereof (or alloys), and may be deposited by any suitable process, such as CVD, ALD, PVD, electroplating, similar processes, or combinations thereof. One or more CMP processes may then be performed to remove excess dielectric layer 62 and conductive layer 63, thereby planarizing the top surfaces of gate isolation structures 50A and VLI 60.

[0157] Alternatively, in some embodiments, the via structure is formed after the second isolation structure is formed. For example, after trench 48 is formed, a dielectric layer 62 may be deposited to completely fill trench 48, which includes the extension portion 57. The dielectric layer 62 is then planarized using a CMP process and patterned using a series of photolithography and etching techniques described herein to form a cavity 59. A conductive layer 63 is then deposited to fill the cavity 59 and planarized such that the top surface of VLI 60 is substantially coplanar with the top surface of the gate isolation structure 50A.

[0158] At operation 710, a front contact structure is formed and electrically coupled to the front side of the memory device, including the upper transistor of the memory device in each memory cell and the via structure in each MSC. FIG. 33 Taking the device 900 as an example, the front contact structure may include a front source / drain contact 996U (e.g., front source / drain contact 70) that is electrically coupled from the front side of the substrate 920 to at least a portion of the source / drain epitaxial structure 962U (e.g., source / drain component 26) in the upper layer of the device 900. The contact structure may also include a front gate contact 1008 (e.g., front gate contact 74, etc.) that is electrically coupled from the front side of the substrate 920 to the upper metal gate structure 982U.

[0159] In some embodiments, forming the front source / drain contact 996U includes patterning the ILD layer 972 to form trenches exposing the source / drain epitaxial structure 962U. A silicide layer 994 is formed on the exposed source / drain epitaxial structure 962U in the trenches, and then the front source / drain contact 996U is formed in each trench and over the silicide layer 994. Exemplary conductive materials for the front source / drain contact 996U include Cu, Co, Ru, Al, Ti, Ta, TiN, TaN, Pt, the like, or combinations (or alloys) thereof. The conductive material of the front source / drain contact 996U can be deposited by any suitable process, such as PVD, ECP, or CVD, and planarized by a CMP process. In some embodiments (although not shown here), front source / drain contacts similar to the front source / drain contact 996U are also formed on and electrically coupled to a via structure formed in the MSC (see [link to documentation]). FIG. 33 For example, front-side source / drain contacts 70H and 70I are formed on and electrically coupled to VLI 60 in MSC 150.

[0160] Similarly, continuing with device 900 as an example, forming the front gate contact 1008 may include forming a mask structure 992 over the upper metal gate structure 982U, forming a CESL 1004 over the mask structure 992, and forming an ILD layer 1006 over the CESL 1004. The composition of the mask structure 992, ILD layer 1006, and CESL 1004 can be similar to that of the mask structure 940, ILD layer 972, and CESL 970, respectively. Then, the stack of the mask structure 992, ILD layer 1006, and CESL 1004 is patterned to form a trench, wherein the front gate contact 1008 is formed through a series of deposition and planarization techniques, similar to those described above regarding the formation of the front source / drain contact 996U.

[0161] In operation 712, a front-side interconnect structure and a metallization layer are formed above the front-side contact structure and electrically coupled to the front-side contact structure of the memory device. FIG. 3A Taking the device 900 depicted as an example, forming a front-side via contact 1010 (e.g., front-side via contact 78) may include stacking a patterned mask structure 992, an ILD layer 1006, and a CESL 1004 to form a via opening, and then filling the via opening with the conductive material described above. Subsequently, the conductive material can be planarized using a CMP process to form the front-side via contact 1010.

[0162] After that, it was still based on FIG. 3BFor example, a multilayer interconnect (MLI) structure 1014 is formed on and electrically coupled to a front gate contact 1008 and a front source / drain contact 996U. The MLI structure 1014 includes a plurality of front metal lines 1018A (e.g., front metal line 80 in front metallization layer M0), 1018B (e.g., front metal line 92 in front metallization layer M1), and 1018C, and front via contacts 1017A (e.g., front via contact 89) and 1017B, sequentially and alternately formed on the front gate contact 1008 and the front via contact 1010. In some embodiments, front metal line 1018A is formed in metallization layer M0, and the front metal line 1018B immediately above it is formed in metallization layer M1, and so on. The MLI structure 1014 also includes various ILD layers 1016 in which metal lines and via contacts are embedded. Although not depicted here, additional dielectric layers, front via contacts, and front metal lines may be formed on the front metal line 1018C as part of the MLI structure 1014.

[0163] In some embodiments, the plurality of front-side metal lines 1018A of the MLI structure 1014 correspond to grounds VSS, BL, BLB, and optional ground WL, respectively. FIG. 7-FIG. 22 , FIG. 1-FIG. 22 and FIG. 7-FIG. 22 As shown. In this respect, each front-side metal line 1018A is configured to be electrically coupled to one or more transistors of device 900, such as upper transistor 910U, in a manner similar to FIG. 37 Electrical connections between components of the memory devices 100A-100C shown. In some embodiments, the upper transistor 910U is configured as an NMOS transistor (corresponding to PD1 or PD2), and the lower transistor 910L is configured as a PMOS transistor (corresponding to PU1 or PU2 of memory cell 10), and the power supply voltage VDD is configured as the back metal line in the back metallization layer BMO described herein.

[0164] In this embodiment, with FIG. 38 Taking the device 100C shown as an example, in operation 712, the front source / drain contacts 70, front via contacts 78, and front metal lines 80 of the first subset are formed above and electrically coupled to the upper transistor in each memory cell 10, while the front source / drain contacts 70, front via contacts 78, and front metal lines 80 of the second subset are formed above and electrically coupled to the VLI 60 in each MSC 150. As described herein, on the front side of the memory device, no electrical connection is formed between the portion of the MSC 150 and the front metal lines 80 corresponding to BL, BLB, or WL (if present).

[0165] In operation 714, the substrate is flipped to expose the back side of the substrate, preparing for the fabrication of the back-side assembly of the memory device. FIG. 7-FIG. 22 Taking the device 900 shown as an example, the flipped substrate 920 can be polished (e.g., by CMP process) along the FF' line to remove excess parts of the substrate 920 and expose the back side of the lower transistor 910L.

[0166] In operation 716, back contact structures, interconnect structures, and metallization layers are formed and electrically coupled above and to the back of the lower transistor in each memory cell and the back of the via structure in each MSC. These structures are similar to the corresponding structures on the front of the memory device. The formation process of the back contact structures, interconnect structures, and metallization layers is similar to that of the corresponding features on the front, and therefore will only be briefly described below.

[0167] by ​ Taking the device 900 shown as an example, dielectric layers 1028 and 1030 are formed on the back side of the lower transistor 910L. The dielectric layers 1028 and 1030 are patterned to form trenches, in which a silicide layer 1034 and a back-side source / drain contact 1040 (e.g., back-side source / drain contact 82) are formed above the silicide layer 1034. In this respect, the back-side source / drain contact 1040 is electrically coupled to the back side of the source / drain epitaxial structure 962L (e.g., source / drain component 24). Subsequently, dielectric layers 1048 and 1050, similar to dielectric layers 1028 and 1030 respectively, are formed above the back-side source / drain contact 1040. Dielectric layers 1048 and 1050 are patterned to form trenches, wherein back via contacts 1060 (e.g., back via contacts 88 and 86) are formed and electrically coupled to the corresponding back source / drain contacts 1040. Subsequently, dielectric layers 1068 and 1070, similar to dielectric layers 1028 and 1030, are formed over the back via contacts 1040. Dielectric layers 1068 and 1070 are then patterned to form trenches, wherein back metal lines 1080 (e.g., back metal lines 90) are formed as portions of the back metallization layer BMO. Although not shown here, additional dielectric layers, back via contacts, and back metal lines may be formed over the back metal lines 1080.

[0168] In this embodiment, with ​Taking the device 100C as an example, a first subset of the back source / drain contacts 82, back via contacts 88, and back metal lines 90 are formed on top of and electrically connected to the lower transistor in each memory cell 10, while a second subset of the back source / drain contacts 82, back via contacts 88, and back metal lines 90 are formed on top of and electrically connected to the VLI 60 in each MSC 150 during operation 716. In this embodiment, the back metal lines 90 may be partially or fully configured as the PDN of the memory device, responsible for providing a reference voltage signal to the ground VSS on the front side of the memory device (e.g., as one of the front metal lines 80) through the VLI 60 in each MSC 150.

[0169] Although the structures and methods will be discussed in relation to CFET structure devices, those skilled in the art will understand that the structures and methods are not limited thereto, and that certain aspects of the embodiments discussed are suitable for inclusion in manufacturing processes for other categories and configurations of IC devices. The structures and methods disclosed herein are equally applicable to various manufacturing processes for implementing vertically stacked structures, including monolithic CFET manufacturing processes and sequential CFET manufacturing processes.

[0170] It should be understood that not all advantages have been discussed herein, not all embodiments or examples require a particular advantage, and other embodiments or examples may provide different advantages.

[0171] In one aspect, this disclosure provides a memory device. The memory device includes a substrate, the substrate including a front side and a back side opposite to the front side. The device includes a cell array disposed above the substrate. The cell array includes a first array portion and a second array portion separated along a first direction in a top view of the memory device. Each of the first array portion and the second array portion includes a plurality of cells. The device includes an intermediate band cell array disposed along the first direction between the first array portion and the second array portion. The intermediate band cell array includes a plurality of intermediate band cells arranged along a second direction perpendicular to the first direction in a top view, and each intermediate band cell includes a via structure configured to transmit a reference voltage signal from the back side of the substrate to the front side of the substrate.

[0172] In some embodiments, each unit includes: a first active region and a second active region extending along a first direction and spaced apart along a second direction, and a gate isolation structure disposed between the first active region and the second active region, wherein a via structure is disposed in the gate isolation structure.

[0173] In some embodiments, the via structure has a first height extending in a second direction, and the gate isolation structure includes an extension portion having a second height extending in the second direction, the second height being greater than the first height.

[0174] In some embodiments, each unit further includes a third active region, which is disposed below the first active region and aligned with the first active region along a third direction perpendicular to the first and second directions.

[0175] In some embodiments, each unit has a first height extending in a second direction, and each intermediate strip unit has a second height extending in the second direction, the second height being the same as the first height.

[0176] In some embodiments, each intermediate strip unit is aligned along a first direction with a first unit in a first array portion and a second unit in a second array portion.

[0177] In some embodiments, the through-hole structure is centrally located in each intermediate strip unit along both the first and second directions.

[0178] In some embodiments, the storage device further includes an active region isolation structure extending along a second direction, the active region isolation structure being disposed between the via structure of each intermediate band cell and an adjacent cell in the first array portion or the second array portion.

[0179] In another aspect, this disclosure provides a storage device. The storage device includes a first cell disposed above the front side of a substrate, with the front side facing the back side of the substrate. The device includes a second cell disposed above the front side of the substrate, spaced apart from the first cell along a first direction in a top view of the storage device. The device includes a first metal line disposed above the front side of the substrate, electrically coupled to the first cell and a second cell. The device includes a second metal line disposed above the back side of the substrate. The device includes an intermediate strip cell inserted along the first direction between and aligned with the first and second cells, the intermediate strip cell including a through-hole structure electrically coupling the first metal line to the second metal line.

[0180] In some embodiments, the first metal line is configured for grounding the first unit and the second unit, and the second metal line is configured to provide a reference voltage signal to the first metal line through a via structure.

[0181] In some embodiments, the first unit includes: a first active region extending along a first direction, a second active region extending parallel to the first active region, and an isolation structure extending parallel to the first active region. The isolation structure is inserted between the first active region and the second active region in a second direction perpendicular to the first direction in a top view, wherein a through-hole structure extends through the isolation structure in the intermediate strip unit in a third direction perpendicular to the first and second directions.

[0182] In some embodiments, the first unit further includes a third active region, which is disposed below the first active region and aligned with the first active region along a third direction.

[0183] In some embodiments, the first active region and the third active region are respectively configured to provide an upper transistor and a lower transistor with different conductivity types.

[0184] In some embodiments, the memory device further includes: a first source / drain contact disposed on the front side of the substrate and electrically coupled to an upper transistor; a first via contact disposed on the front side of the substrate and electrically coupled to the first source / drain contact and a first metal line; a second source / drain contact disposed on the back side of the substrate and electrically coupled to a lower transistor; and a second via contact disposed on the back side of the substrate and electrically coupled to the second source / drain contact and a second metal line.

[0185] In some embodiments, the isolation structure extends along a first direction through the center of the first unit, the intermediate strip unit, and the second unit.

[0186] In some embodiments, the first metal wire extends along a first direction through the center of the first unit, the intermediate strip unit, and the second unit.

[0187] In some embodiments, the first metal wire extends along a first direction through the boundary of the first unit, the intermediate strip unit, and the second unit.

[0188] In another aspect, this disclosure provides a method for forming a memory device. The method includes forming a first array portion, a second array portion, and an intermediate band cell array in the memory device, the intermediate band cell array being inserted between the first array portion and the second array portion along a first direction. The first array portion, the second array portion, and the intermediate band cell array include: a first active region and a second active region, each extending along the first direction above the front surface of a substrate and spaced apart along a second direction perpendicular to the first direction in a top view of the memory device, wherein the first active region and the second active region provide first cells in the first array portion, second cells in the second array portion, and intermediate band cells in the intermediate band cell array; and a third active region extending along the first direction and vertically stacked below the first active region along a third direction perpendicular to both the first and second directions. In the intermediate band cell, a via structure is formed between the first active region and the second active region along the second direction. The via structure extends along the third direction between the front side of the substrate and the back side away from the front side. A first metal line is formed above the first active region and the second active region along the third direction. The first metal line is electrically coupled to the first active region and the second active region. A second metal line is formed above the back side of the substrate. The second metal line is electrically coupled to the third active region. The via structure is electrically coupled to the second metal line and the first metal line.

[0189] In some embodiments, the method further includes forming an isolation structure above the front side of the substrate, the isolation structure extending along a first direction and located between the second active regions along a second direction, such that the via structure is surrounded by the isolation structure.

[0190] In some embodiments, forming an isolation structure and forming a via structure are performed simultaneously, including: forming a trench extending along a first direction and disposed along a second direction between a first active region and a second active region, the trench including an extension portion having a first height along the second direction greater than a second height of a portion of the trench outside the extension portion; depositing a dielectric material in the trench, the dielectric material partially filling the extension portion; depositing a conductive material over the dielectric material to completely fill the extension portion, forming a via structure surrounded by the dielectric material; and planarizing the dielectric material and the conductive material to form a via structure surrounded by an isolation structure.

[0191] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A storage device, comprising: A substrate, the substrate including a front side and a back side opposite to the front side; A cell array is disposed above the substrate. The cell array includes a first array portion and a second array portion separated along a first direction from a top view of the storage device. Each of the first array portion and the second array portion includes a plurality of cells. as well as An intermediate band cell array is disposed between the first array portion and the second array portion along the first direction. The intermediate band cell array includes a plurality of intermediate band cells arranged along a second direction perpendicular to the first direction in the top view, and each intermediate band cell includes a via structure configured to transmit a reference voltage signal from the back side of the substrate to the front side of the substrate.

2. The storage device according to claim 1, wherein, Each unit includes: A first active region and a second active region extending along the first direction and spaced apart along the second direction, and A gate isolation structure is disposed between the first active region and the second active region, wherein the via structure is disposed in the gate isolation structure.

3. The storage device according to claim 2, wherein, The via structure has a first height extending along the second direction, and the gate isolation structure includes an extension portion having a second height extending along the second direction, the second height being greater than the first height.

4. The storage device according to claim 2, wherein, Each unit also includes a third active region, which is disposed below the first active region and aligned with the first active region along a third direction perpendicular to the first direction and the second direction.

5. The storage device according to claim 1, wherein, Each unit has a first height extending along the second direction, and each intermediate strip unit has a second height extending along the second direction, the second height being the same as the first height.

6. The storage device according to claim 1, wherein, Each intermediate band unit is aligned along the first direction with the first unit in the first array portion and the second unit in the second array portion.

7. The storage device of claim 1, further comprising an active region isolation structure extending along the second direction, the active region isolation structure being disposed between the via structure of each intermediate band cell and an adjacent cell in the first array portion or the second array portion.

8. A storage device comprising: The first unit is disposed above the front side of the substrate, the front side being opposite to the back side of the substrate; The second unit disposed above the front surface of the substrate is arranged at a distance from the first unit along a first direction from the top view of the storage device. A first metal line is disposed above the front side of the substrate, and the first metal line is electrically coupled to the first unit and the second unit; A second metal line is disposed above the back side of the substrate; as well as An intermediate strip unit is inserted along a first direction between the first unit and the second unit and aligned with the first unit and the second unit, the intermediate strip unit including a through-hole structure for electrically coupling the first metal wire to the second metal wire.

9. A method of forming a storage device, comprising: A first array portion, a second array portion, and an intermediate band cell array are formed in a storage device. The intermediate band cell array is inserted between the first array portion and the second array portion along a first direction. The first array portion, the second array portion, and the intermediate band cell array include: A first active region and a second active region, each extending along the first direction above the front surface of the substrate, and spaced apart along a second direction perpendicular to the first direction from a top-view perspective of the memory device, wherein the first active region and the second active region provide a first cell in the first array portion, a second cell in the second array portion, and an intermediate band cell in the intermediate band cell array; and The third active region extends along the first direction and is vertically stacked below the first active region along a third direction perpendicular to the first direction and the second direction. In the intermediate band unit, a via structure is formed between the first active region and the second active region along the second direction, and the via structure extends along the third direction between the front side of the substrate and the back side facing away from the front side; A first metal line is formed above the first active region and the second active region along the third direction, and the first metal line is electrically coupled to the first active region and the second active region; and A second metal line is formed above the back side of the substrate, the second metal line is electrically coupled to the third active region, and the via structure is electrically coupled to the second metal line and the first metal line.

10. The method of claim 9, further comprising forming an isolation structure above the front side of the substrate, the isolation structure extending along the first direction and located between the second active regions along the second direction, such that the via structure is surrounded by the isolation structure.

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