Efficient processing on a dual core processing system

Abstract

A system may include: a plurality of processing cores including at least a first processing core and a second processing core; a shared memory communicatively coupled to each of the plurality of processing cores, and accessible by each of the plurality of processing cores; a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive access to the memory by each of the plurality of processing cores; and a software architecture embodied in a non-transitory computer readable medium and configured to divide a plurality of processing tasks between the first processing core and the second processing core when read and executed by the multi-core processor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to circuitry for electronic devices, including but not limited to personal portable devices such as wireless telephones and media players, and more specifically to systems and methods for efficient processing in multi-core processing devices. BACKGROUND

[0002] Many mobile devices (e.g., mobile telephones) include one or more cameras for capturing images. To provide image stabilization and focusing, the position of the camera in a plane substantially parallel to the subject of the image and the position of the camera's lens in a direction perpendicular to such a plane can be controlled by a plurality of motors under the control of a camera controller. The control system can be implemented using an application processor of the mobile device that is coupled to the camera controller local to the camera and its various motors via a communication interface (e.g., an Inter-Integrated Circuit or I2C interface). For example, the application processor can communicate a data vector to the camera controller regarding the application processor's target position, while the camera controller can communicate a vector to the application processor regarding the camera's actual position as sensed by a plurality of magnetic sensors (e.g., Hall sensors) and / or other suitable sensors.

[0003] As mobile devices become more complex, camera control on such mobile devices also becomes more complex. As a result, camera controllers are increasingly implemented using multi-core processors that can include multiple processing cores and multiple peripheral blocks on a single integrated circuit. Multi-core implementations can enable improved system performance (e.g., more operations per clock cycle) and / or can enable processing cores to be executed at lower clock frequencies. In addition to use for camera controllers, multi-core processors can also be used for other compute-intensive applications.

[0004] In multi-core processors, it can be desirable to provide logical separation of mathematical algorithmic tasks and other system tasks to allow for easy patching and scalability. It can also be desirable to synchronize activities executing on various cores, as well as to maximize parallelism of cooperating tasks running on various cores. In addition, it can also be desirable to prevent concurrent access to shared resources, to minimize waiting on cross-core dependencies, and to minimize waiting on potential system updates or reporting system status. SUMMARY

[0005] In accordance with the teachings of the present disclosure, certain drawbacks and problems associated with existing approaches to managing access to system peripherals in multi-core systems can be reduced or eliminated.

[0006] According to embodiments of the present disclosure, a system can include a plurality of processing cores including at least a first processing core and a second processing core; a shared memory communicatively coupled to and accessible by each of the plurality of processing cores; a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive access to the memory by each of the plurality of processing cores; and a software architecture embodied in a non-transitory computer-readable medium and configured to divide a plurality of processing tasks between the first processing core and the second processing core when read and executed by the multi-core processor.

[0007] According to these and other embodiments of the present disclosure, a method, performed in a system having a plurality of processing cores including at least a first processing core and a second processing core and including a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, includes controlling exclusive access to the memory by each of the plurality of processing cores by a global monitor communicatively coupled to each of the plurality of processing cores; and dividing a plurality of processing tasks between the first processing core and the second processing core using a software architecture embodied in a non-transitory computer-readable medium and configured to divide a plurality of processing tasks between the first processing core and the second processing core when read and executed by the multi-core processor.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the claims set forth in this disclosure as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0009] A more complete understanding of examples, embodiments, and certain advantages thereof can be acquired by referring to the following description in consideration with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

[0010] Figure 1 A block diagram of selected components of an example mobile device is shown in accordance with embodiments of the present disclosure; and

[0011] Figure 2 A block diagram of selected components of an example multi-core processor that can be used to implement a control subsystem of a camera controller is shown in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] With the data transfer scheme in accordance with the present disclosure, a plurality of device controllers can be connected in series and communicate with a desired target device without a large loss of latency. For custom protocols, the data transfer scheme can simply reuse existing command structures as all communications will act like regular single-layer data transfers. At the same time, the data transfer scheme can avoid the need to consume additional memory and processing power of the processor.

[0013] The systems and methods disclosed herein are not limited in any way to particular applications and can be used in various ways and in any suitable manner. For example, in some embodiments, the system controller of the communication system can be a camera system controller, the device controller can be a lens stabilization controller for stabilizing a camera lens or a lens focus controller for controlling the focus of a camera lens, and the device target can be a sensor for detecting a camera lens position.

[0014] Figure 1 A block diagram of selected components of an example mobile device 101 is shown in accordance with embodiments of the present disclosure. As shown, the mobile device 101 can include a housing 102, an application processor 103, a microphone 106, a radio transmitter / receiver 108, a speaker 110, and a camera module 109 including a camera 107 and a camera controller 112. Figure 1

[0015] The housing 102 can include any suitable housing, casing, or other enclosure for containing the various components of the mobile device 101. The housing 102 can be constructed of plastic, metal, and / or any other suitable material. Additionally, the housing 102 can be adapted (e.g., sized and shaped) so that the mobile device 101 can be conveniently carried and used by a user of the mobile device 101. Thus, the mobile device 101 can include, but is not limited to, a smartphone, a tablet computing device, a handheld computing device, a personal digital assistant, a notebook computer, a video game controller, or any other device that can be readily carried and used by a user of the mobile device 101.

[0016] The application processor 103 can be housed within the housing 102 and can include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and can include, but is not limited to, a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and / or execute program instructions and / or process data. In some embodiments, the application processor 103 can interpret and / or execute program instructions and / or process data stored in a memory (not explicitly shown) and / or other computer-readable media accessible to the application processor 103.

[0017] ​The microphone 106 can be housed at least partially within the housing 102, can be communicatively coupled to the application processor 103, and can include any system, device, or apparatus configured to convert an incoming sound at the microphone 106 into an electrical signal that can be processed by the application processor 103, with such sound being converted into the electrical signal using a diaphragm or a membrane having a capacitance that varies based on sound vibrations received at the diaphragm or the membrane. The microphone 106 can include an electrostatic microphone, a condenser microphone, an electret microphone, a microelectromechanical systems (MEMS) microphone, or any other suitable condenser microphone.

[0018] The radio transmitter / receiver 108 can be housed within the housing 102, can be communicatively coupled to the application processor 103, and can include any system, device, or apparatus configured to generate and transmit radio frequency signals with the help of an antenna, as well as receive radio frequency signals and convert information carried by such received signals into a form that can be used by the application processor 103. The radio transmitter / receiver 108 can be configured to transmit and / or receive various types of radio frequency signals, including but not limited to cellular communications (e.g., 2G, 3G, 4G, LTE, etc.), short-range wireless communications (e.g., Bluetooth), commercial radio signals, television signals, satellite radio signals (e.g., GPS), wireless fidelity, etc.

[0019] The speaker 110 can be housed at least partially within the housing 102 or can be external to the housing 102, can be communicatively coupled to the application processor 103, and can include any system, device, or apparatus configured to produce sound in response to an electrical audio signal input. In some embodiments, the speaker 110 can include a dynamic speaker that employs a lightweight diaphragm mechanically coupled to a rigid frame via a flexible suspension that constrains the movement of the voice coil axially through the magnetic gap. When an electrical signal is applied to the voice coil, a magnetic field is created by the electric current in the voice coil, making it a variable electromagnet. The voice coil and the magnetic system of the driver interact, producing a mechanical force that causes the voice coil (and thus the attached cone) to move back and forth, reproducing sound under the control of the applied electrical signal from the amplifier.

[0020] The camera 107 can be housed at least partially within the housing 102 (and partially housed external to the housing 102 to enable light to enter a lens of the camera 107), and can include any suitable system, device, or apparatus for recording an image (moving or still) into one or more electrical signals that can be processed by the application processor 103. As shown, the camera 107 can include a plurality of motors 114, sensors 116, and image capture components 118. Figure 1

[0021] ​The image capture components 118 can include a collection of components configured to capture images, including but not limited to one or more lenses and image sensors to sense the intensity and wavelength of received light. Such image capture components 118 can be coupled to the application processor 103 such that the camera 107 can transmit captured images to the application processor 103.

[0022] The motors 114 can be mechanically coupled to one or more of the image capture components 118, and each motor 114 can include any suitable system, device, or apparatus configured to cause such one or more image capture components 118 to mechanically move to a desired camera position based on control signals received from the camera controller 112 indicating the desired camera position.

[0023] The sensors 116 can be mechanically coupled to one or more of the image capture components 118 and / or the motors 114, and can be configured to sense a position associated with the camera 107. For example, a first sensor 116 can sense a first position (e.g., an x-position) of the camera 107 relative to a first linear direction, a second sensor 116 can sense a second position (e.g., a y-position) of the camera 107 relative to a second linear direction perpendicular to the first linear direction, and a third sensor 116 can sense a third position (e.g., a z-position) of the camera 107 relative to a third linear direction perpendicular to the first and second linear directions (e.g., a position of a lens).

[0024] The camera controller 112 can be housed within the housing 102, can be communicatively coupled to the camera 107 and the application processor 103 (e.g., via an Inter-Integrated Circuit (I2C) interface), and can include any system, device, or apparatus configured to control the motors 114 or other components of the camera 107 to place components of the camera 107 into desired positions. The camera controller 112 can also be configured to receive signals from the sensors 116 regarding the actual position of the camera 107 and / or regarding the state of the camera 107. As Figure 1 shown, the camera controller 112 can include a control subsystem 111 and a motor driver 113.

[0025] The control subsystem 111 can be integrated with the camera controller 112 and can include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and can include, but is not limited to, a microprocessor, microcontroller, digital signal processor (DSP), application-specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and / or execute program instructions and / or process data. In some embodiments, the control subsystem 111 can interpret and / or execute program instructions and / or process data stored in memory and / or other computer-readable media accessible to the control subsystem 111. In particular, the control subsystem 111 can be configured to perform the functions of the camera controller 112, including, but not limited to, controlling the motors 114 and receiving and processing data from the sensors 116. In some embodiments, the control subsystem 111 can include a multi-core processor.

[0026] The motor drivers 113 can include a plurality of circuits, each such circuit configured to receive one or more control signals from the control subsystem 111 (including, but not limited to, signals indicative of a desired target current for a motor 114) and drive a drive signal (e.g., a current mode signal) to a corresponding motor 114 in accordance with the one or more control signals in order to control operation of such corresponding motor 114.

[0027] Figure 2 A block diagram showing selected components of an exemplary multi-core processor 200 that can be used to implement the control subsystem 111 of the camera controller 112 in accordance with embodiments of the present disclosure is shown. As shown, the multi-core processor 200 can include a plurality of cores 202, including an operating system (OS) core 202a and an application (APP) core 202b, a memory 204, a bus matrix 206, bridges 208 (e.g., bridges 208a and 208b), an inter-process communication (IPC) global monitor 210, an IPC OS interrupt register 212, and an IPC APP interrupt register 214. Figure 2

[0028] Each core 202 can include a separate processing unit that can read and execute program instructions such that the multi-core processor 200 can execute instructions on multiple cores 202 simultaneously, which can increase the overall execution speed of programs of instructions that support multi-threading or other parallel computing techniques. In some embodiments, the cores 202 can interpret and / or execute program instructions and / or process data stored in the memory 204 and / or another component of the multi-core processor 200. Although for purposes of clarity and exposition, Figure 2 ​Only two cores 202 are depicted, but it should be understood that the multi-core processor 200 can include any suitable number of cores 202 and / or controllers.

[0029] In operation, a software architecture executing on the multi-core processor 200 can divide certain tasks among the cores 202. For example, the following table sets forth an example of allocating tasks between the OS core 202a and the APP core 202b:

[0030]

[0031] The memory 204 can be communicatively coupled to the cores 202 via the bus matrix 206, and can include any system, device, or apparatus (e.g., computer readable medium) configured to retain program instructions and / or data for a period of time. The memory 204 can include RAM, EEPROM, PCMCIA cards, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and / or array of volatile or non-volatile memory.

[0032] The bus matrix 206 can include any suitable communication bus for communicatively coupling the cores 202, the memory 204, and the bridge 208 to one another. In some embodiments, the bus matrix 206 can include an Advanced High-performance Bus (AHB) according to the Advanced Microcontroller Bus Architecture (AMBA) specification.

[0033] The bridge 208 can include a peripheral bus interface configured to communicatively couple the interrupt registers (e.g., IPC OS interrupt register 212, IPC APP interrupt register 214) to the respective cores 202 via the bus matrix 206. In some embodiments, the bridge 208 can include an Advanced Peripheral Bus (APB) bridge according to the AMBA specification.

[0034] The IPC global monitor 210 can include any system, device, or apparatus that enables the acquisition and release of exclusive access that can be required to manage locks for shared resources (e.g., addresses in the memory 204) among the plurality of cores 202. For example, the IPC global monitor 210 can tag addresses accessed by exclusive load instructions (e.g., LDREX instructions) for each core 202, which can include two operations: changing the lock state of the address, and detecting and rejecting the change if the core that performs the change is not aware of the current state. Exclusive read operations by the cores 202 can check the lock state and can also inform the hardware of other writes, for example, to determine whether another core 202 is attempting to write a value to the address, thereby violating the core’s 202 view of the lock on the address.

[0035] Accordingly, a particular core 202 can use an exclusive load instruction to check whether a particular memory address is available. If so, the particular core 202 can execute an exclusive store instruction to claim the memory address. Detection of a change in the lock state by another core 202 can cause the exclusive store instruction to fail. If the memory address lock has not changed, the exclusive store instruction can succeed because the particular core 202 can obtain exclusive access to the memory address that was tagged in the exclusive load instruction. On the other hand, if another core 202 modifies the lock state as a result of the particular core executing the exclusive load instruction, the exclusive store instruction failure can be critical. Accordingly, the core 202 can claim and own the memory address (or other shared resource). The following table demonstrates an example arbitration that can be performed when two cores 202 attempt to store to the same memory address at the same time:

[0036]

[0037] Accordingly, the IPC global monitor 210 can be used to manage shared resources, for example, by enabling the plurality of cores 202 to safely implement mutexes to lock shared resources for exclusive access and unlock such resources after use, in order to achieve atomicity and consistency of command updates and read data preparation.

[0038] Accordingly, the memory 204 can include a shared memory wrapper to interface between one or more shared memory banks in the memory 204 and the bus matrix 206. Such a shared memory wrapper can include write protection logic that selectively protects write operations to memory addressed by the cores 202 depending on which particular core owns each address.

[0039] The IPC OS interrupt register 212 can include a memory register for sending an interrupt request to the APP core 202b. Similarly, the IPC APP interrupt register 214 can include a memory register for sending an interrupt request to the OS core 202a. Each interrupt register can include a plurality of fields or bits, each field or bit associated with a different interrupt, each different interrupt having a unique priority. For example, in a particular embodiment, the IPC OS interrupt register 212 can include two bits, bit 1 and bit 0, and the OS core 202a can send an interrupt request to the APP core 202b by writing a value (e.g., a logical 1) to either bit, with one bit (e.g., bit 1) associated with a higher priority interrupt request than the other bit (e.g., bit 0). Likewise, in such a particular embodiment, the IPC APP interrupt register 214 can include two bits, bit 1 and bit 0, and the application core 202b can send an interrupt request to the OS core 202a by writing a value (e.g., a logical 1) to either bit, with one bit (e.g., bit 1) associated with a higher priority interrupt request than the other bit (e.g., bit 0). Each interrupt register can be coupled to an interrupt controller of the other core 202. The IPC OS interrupt register 212 and the IPC APP interrupt register 214 can provide a low-overhead scheme for communicating interrupt requests that are prioritized for servicing the appropriate context.

[0040] Such a priority interrupt scheme can allow for the use of priority queues for inter-core messaging, with messages in higher priority queues being handled urgently, and messages in lower priority queues being handled timely, but never lost. For example, if the APP core 202b is to place a message in a high-priority execution queue, the APP core 202b can issue a high-priority interrupt request to the OS core 202a, which can then handle the message. Conversely, as another example, if the OS core 202a places a message in a low-priority queue, the corresponding low-priority interrupt request can be handled by the APP core 202b, which has a low priority. Thus, messages residing in queues are preserved and can be preserved and can be handled based on their priority in non-time critical processing segments, while time critical processing segments are not interrupted, with predictable latency.

[0041] Also as shown, the OS core 202a and the APP core 202b can communicate dedicated event signals to each other (e.g., via the IPC OS event register 216 and the IPC APP event register 218). The IPC OS event register 216 can include a memory register for sending an event request to the APP core 202b. Similarly, the IPC APP event register 218 can include a memory register for sending an event request to the OS core 202a. Each event register can include a plurality of fields or bits, each field or bit associated with a different event, each different event having a unique priority. For example, in a particular embodiment, the IPC OS event register 216 can include two bits, bit 1 and bit 0, and the OS core 202a can send an event request to the APP core 202b by writing a value (e.g., a logical 1) to either bit, with one bit (e.g., bit 1) associated with a higher priority event request than the other bit (e.g., bit 0). Likewise, in such a particular embodiment, the IPC APP event register 218 can include two bits, bit 1 and bit 0, and the application core 202b can send an event request to the OS core 202a by writing a value (e.g., a logical 1) to either bit, with one bit (e.g., bit 1) associated with a higher priority event request than the other bit (e.g., bit 0). Each event register can be coupled to an event controller of the other core 202. The IPC OS event register 216 and the IPC APP event register 218 can provide a low-overhead scheme for communicating event requests that are prioritized for servicing the appropriate context. Figure 2 Figure 2 ​The connection marked "SEV / RXEV" can be used in conjunction with monitoring of cross-core hibernation and wake-up activities to achieve load balancing. Sending core 202 can wake up hibernation core 202 by using a dedicated event signal and switching the task to hibernation core 202, thus allowing core 202 to hibernate while waiting for shared resources (e.g., shared memory) to become available. When the shared resource becomes available and any hibernation core 202 can be woken up in response to the event, core 202 can transmit the event to other cores 202, regardless of their hibernation state. Furthermore, in some embodiments, IPC interrupts can also be used to wake up hibernation core 202.

[0042] Therefore, in typical operating scenarios, neither core 202 needs to wait for the other core 202, with the maximum wait time in the worst-case scenario being the duration required for the memory copy operation. The aforementioned interrupt request and queuing mechanism allows for rapid generation of cross-core interrupts and allows for flexible message processing based on message priority schemes.

[0043] As used herein, when two or more elements are referred to as being “coupled” to each other, such a term indicates that the two or more elements are in electronic or mechanical communication, whether indirectly or directly connected, with or without intermediate elements.

[0044] This disclosure covers all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims cover all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Furthermore, references in the appended claims to means or systems or components adapted to, arranged to, capable of, configured to, enabled, operable, or operated to perform a particular function cover such means, whether or not it or the particular function is activated, turned on, or unlocked, provided that the means or system or component is so adapted, arranged, capable of, configured, enabled, operable, or operated. Therefore, modifications, additions, or omissions may be made to the systems, means, and methods described herein without departing from the scope of this disclosure. For example, components of systems and devices may be integrated or separate. Furthermore, the operation of the systems and means disclosed herein may be performed by more, fewer, or other components, and the described methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used herein, “each” means each member of a set or each member of a subset of a set.

[0045] Although the example embodiments are illustrated and described in the drawings and the foregoing description, the principles of the disclosure can be implemented using any number of techniques, whether currently known or not. The disclosure should not be limited to the example implementations and techniques described above and shown in the drawings.

[0046] The articles of manufacture depicted in the drawings are not necessarily drawn to scale unless otherwise specifically noted.

[0047] All examples and conditional language recited herein are intended to be construed to cover all processes, products, and compositions of matter similar to those described in each example and / or conditionally recited. All such similar processes, products, and compositions of matter are intended to be within the scope of the disclosure. The disclosure should not be interpreted as being limited to the specific examples and conditions recited.

[0048] While specific advantages have been enumerated above, various embodiments can include some, none, or all of the enumerated advantages. Additionally, other technical advantages can become readily apparent to those of ordinary skill in the art after review of the foregoing figures and description.

[0049] To help readers of the patent office and any patent issued on this application interpret the appended claims, the applicants wish to note that they are not intending to invoke any of the appended claims or claim elements, unless the word “means” is expressly used in a particular claim.

Claims

1. A system comprising: Multiple processing cores, including at least a first processing core and a second processing core; Shared memory, communicatively coupled to each of the plurality of processing cores, and accessible by each of the plurality of processing cores; A global monitor is communicatively coupled to each of the plurality of processing cores and is configured to control exclusive access to memory for each of the plurality of processing cores; as well as The software architecture, embodied in a non-transitory computer-readable medium, is configured to divide multiple processing tasks between the first processing core and the second processing core when read and executed by the multi-core processor.

2. The system according to claim 1, wherein, The processing tasks assigned to the first processing core include one or more of the following: mode management of a device including the plurality of processing cores, updating the system state of the system, updating the analog-to-digital controller code in an open-loop system controlled by the multi-core processor in response to commands received by the multi-core processor, and receiving and transmitting commands associated with a closed-loop system controlled by the multi-core processor. And report system status data to application processors outside the multi-core processor.

3. The system according to claim 1, wherein, The processing tasks assigned to the first processing core include one or more of the following: performing control mathematical operations on the system controlled by the multi-core processor, generating analog-to-digital controller code for the closed-loop system controlled by the multi-core processor, and updating the internal state in response to commands received from the first processing core.

4. The system according to any one of claims 1-3, further comprising: A first interrupt register is communicatively coupled between the first processing core and the second processing core; and The second interrupt register is communicatively coupled between the first processing core and the second processing core; in: The first processing core is configured to send a first interrupt request to the second processing core by writing information to the first interrupt register; and The second processing core is configured to send a second interrupt request to the first processing core by writing information to the second interrupt register.

5. The system according to claim 4, wherein: The information written to the first interrupt register includes the priority associated with the first interrupt request; and The information written to the second interrupt register includes the priority associated with the second interrupt request.

6. The system according to claim 5, wherein, Messages between the first processing core and the second processing core are prioritized in the queue based on the priority associated with the first interrupt request and the priority associated with the second interrupt request.

7. The system according to claim 6, wherein, Messages residing in the queue are retained and processed based on their priority in non-time-critical processing segments, while ensuring that time-critical processing segments are not interrupted and have predictable latency.

8. The system according to any one of claims 1-7, further comprising an interrupt register indicating the sleep state of the first processing core and the second processing core, wherein, The interrupt can be read by the first processing core and the second processing core for use in conjunction with event signals, or interrupted to achieve dynamic load balancing between the first processing core and the second processing core.

9. A method, performed in a system having a plurality of processing cores, the plurality of processing cores including at least a first processing core and a second processing core, and a shared memory including a memory communicatively coupled to and accessible by each of the plurality of processing cores, the method comprising: A global monitor communicatively coupled to each of the plurality of processing cores controls the exclusive access of each of the plurality of processing cores to memory; as well as By utilizing a software architecture embodied in a non-transitory computer-readable medium, when the software architecture is read and executed by the multi-core processor, multiple processing tasks are divided between the first processing core and the second processing core.

10. The method according to claim 9, wherein, The processing tasks assigned to the first processing core include one or more of the following: mode management of a device including the plurality of processing cores, updating the system state of the system, updating the analog-to-digital controller code in an open-loop system controlled by the multi-core processor in response to commands received by the multi-core processor, and receiving and transmitting commands associated with a closed-loop system controlled by the multi-core processor. And report system status data to application processors outside the multi-core processor.

11. The method according to claim 9, wherein, The processing tasks assigned to the first processing core include one or more of the following: performing control mathematical operations for the system controlled by the multi-core processor, generating analog-to-digital controller code for the closed-loop system controlled by the multi-core processor, and updating the internal state in response to commands received from the first processing core.

12. The method according to any one of claims 9-11, further comprising: By writing information into a first interrupt register communicatively coupled between the first processing core and the second processing core, the first processing core transmits a first interrupt request to the second processing core. and By writing information into a second interrupt register communicatively coupled between the first processing core and the second processing core, the second processing core transmits a second interrupt request to the first processing core.

13. The method according to claim 12, wherein: The information written to the first interrupt register includes the priority associated with the first interrupt request; and The information written to the second interrupt register includes the priority associated with the second interrupt request.

14. The method of claim 13, further comprising prioritizing messages between the first processing core and the second processing core in a queue according to the priority associated with the first interrupt request and the priority associated with the second interrupt request.

15. The method of claim 14, further comprising retaining messages residing in the queue and processing them based on their priority in non-time-critical processing segments, while ensuring that time-critical processing segments are not interrupted and have predictable delays.

16. The method according to any one of claims 9-15, further comprising using an interrupt register to indicate the sleep state of the first processing core and the second processing core, wherein, The interrupt can be read by the first processing core and the second processing core for use in conjunction with event signals, or interrupted to achieve dynamic load balancing between the first processing core and the second processing core.

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