A method for predicting aging effects of integrated circuits and evaluating reliability of circuit life

Abstract

This invention relates to the field of circuit performance testing technology, specifically a method for predicting integrated circuit aging effects and assessing circuit lifetime reliability. The specific implementation process includes: acquiring the physical design netlist and basic process library; parsing the test load into transient flip-flop density and generating a time-varying excitation flow based on layout geometry information; dividing the aging-sensitive region using a dual-track aging differential mechanism; quantifying circuit aging parameters by integrating the time-varying excitation flow; performing full-chip timing simulation on the circuit aging parameters to predict the performance erosion index; calculating the dynamic redundancy shrinkage vector and adjusting the guard band reduction magnitude to converge the evaluation to the target design range. This invention utilizes time-varying excitation flow and sensitivity partitioning topology to effectively capture the multi-physics coupling effect under dynamic loads, improving the prediction distortion problem caused by static assumptions. By optimizing the guard band design through dynamic redundancy shrinkage vector, a balance between chip area, power consumption, and reliability lifetime is achieved.

Description

Technical Field

[0001] This invention relates to the field of circuit performance testing technology, specifically to a method for predicting the aging effect of integrated circuits and assessing the reliability of circuit lifespan. Background Technology

[0002] During the long-term operation of integrated circuits, aging effects such as negative bias temperature instability, hot carrier injection, and time-induced dielectric breakdown can cause drift in critical transistor electrical parameters, leading to shortened circuit lifespan or even functional failure. To assess these risks, existing technologies generally extract aging parameters of devices under specific voltage and temperature stresses through experiments or TCAD simulations, constructing an aging model library. Using SPICE circuit simulation or static timing analysis methods, these aging parameters are substituted into the circuit netlist to calculate the delay degradation or signal integrity changes after a preset operating period, thereby predicting the circuit's lifespan and determining whether its reliability meets standards.

[0003] However, existing technologies have inherent limitations in practical applications. High-precision transistor-level SPICE simulations are computationally extremely complex and time-consuming for very large-scale integrated circuits (VLSI), failing to achieve rapid coverage of the entire chip. While simplified lookup table methods or logic-level static analysis improve speed, they often neglect complex internal physical state changes and transient signal characteristics, leading to a significant decrease in prediction accuracy. Furthermore, they typically employ worst-case static assumptions, assuming the circuit operates under extreme process angles, voltages, and temperatures throughout its entire lifespan. In summary, existing technologies ignore the dynamic changes in actual workloads and the complex coupling effects between multiple physical fields (such as heat, electricity, and stress). They also reserve excessively large design protection bands in the circuit, resulting in chip area redundancy, increased power consumption, and wasted nominal performance, failing to accurately reflect the actual lifespan and reliability level of the circuit under real-world complex operating conditions.

[0004] To address this, a method for predicting integrated circuit aging effects and assessing circuit lifetime reliability is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a method for predicting the aging effect of integrated circuits and assessing the reliability of circuit life, thereby enabling the prediction of the aging effect and the assessment of the reliability of integrated circuit life.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for predicting aging effects and assessing circuit lifetime reliability in integrated circuits includes:

[0008] The physical design netlist and basic process library of the integrated circuit are obtained, and the test load sequence is parsed into the transient flip-flop density of the chip node. The transient flip-flop density is thermally mapped with the chip layout geometry information to generate a time-varying excitation flow that includes node power consumption characteristics and thermal field coupling state.

[0009] The time-varying excitation flow is used to perform sensitivity partitioning topology based on the dual-track aging differential mechanism to divide the aging sensitive domain; the time-varying excitation flow is subjected to time-domain integration within the aging sensitive domain to quantify circuit aging parameters that include negative bias temperature instability and hot carrier injection cumulative damage.

[0010] The circuit aging parameters are back-mapped to the physical design netlist, and full-chip timing simulation is performed under the boundary conditions of the thermal coupling state to generate timing simulation data. The performance erosion index of the integrated circuit is predicted based on the timing simulation data, and the dynamic redundancy shrinkage vector between the performance erosion index and the circuit lifespan is calculated. The dynamic redundancy shrinkage vector is used in conjunction with the basic process library to adjust the guard band reduction range, and the reliability assessment of the integrated circuit is converged within the target design range.

[0011] Preferably, the specific implementation process of obtaining the physical design netlist and basic process library of the integrated circuit and parsing the test load sequence into the transient flip-flop density of the chip node includes:

[0012] The physical design netlist of the integrated circuit is obtained, and the capacitance and resistance parameters associated with the chip node locations are extracted. Combined with the cell delay characteristics in the basic process library, a static timing analysis map is constructed. The test load sequence is deconstructed into a discrete time-domain signal vector flow, and the signal vector flow is injected into the static timing analysis map according to the timing constraints to perform step-by-step logic state propagation deduction. The voltage level transition behavior of all chip nodes is monitored, and the rising edge and falling edge switching actions are independently statistically accumulated to form an original switching count matrix characterizing the dynamic behavior of the nodes. The original switching count matrix is ​​normalized according to the circuit operating frequency and clock cycle constraints, and the instantaneous switching density reflecting the node activity level is calculated.

[0013] Preferably, the specific implementation process of thermally mapping the transient flip-over density with the chip layout geometry to generate a time-varying excitation flow containing node power consumption characteristics and thermal field coupling state includes:

[0014] The transient flip density is combined with the chip layout geometry information to transform it into an instantaneous power sequence that fluctuates over time for each chip node. A three-dimensional thermal resistance-capacitance network is established based on the thermal conductivity and specific heat capacity characteristics of the chip material. The instantaneous power sequence is used as a heat source excitation and mapped to the corresponding thermal analysis grid cell. The heat flow diffusion process is transiently solved within the three-dimensional thermal resistance-capacitance network to calculate the local temperature field evolution curve formed by the superposition of device self-heating effect and mutual heating effect of adjacent regions. The local temperature field evolution curve is time-domain synchronized and data correlated with the original voltage logic signal to integrate it into a time-varying excitation flow.

[0015] Preferably, the specific implementation process of using the time-varying excitation flow to perform sensitivity partitioning topology based on the dual-track aging differential mechanism to divide the aging sensitive domain includes:

[0016] The dual-track aging differential mechanism includes two evaluation channels. In the first evaluation channel, the accumulation rate of oxide interface state traps in the circuit chip is calculated by combining local temperature field data and the duration of static low level. In the second evaluation channel, the hot carrier collision ionization intensity of the circuit chip is calculated by combining signal edge transition rate and channel peak current density. The accumulation rate of oxide interface state traps and the hot carrier collision ionization intensity are fused according to the time-varying excitation current to generate a comprehensive sensitivity distribution matrix that maps the aging susceptibility of the entire chip device. The comprehensive sensitivity distribution matrix is ​​projected onto the topology of the integrated circuit to screen out the set of circuit paths with accumulated damage potential values ​​higher than the safety threshold and classify them into aging sensitive regions.

[0017] Preferably, the specific implementation process of performing time-domain integration on the time-varying excitation current within the aging sensitive domain to quantify it into circuit aging parameters including negative bias temperature instability and accumulated damage from hot carrier injection includes:

[0018] Chip nodes within the aging-sensitive domain are extracted, and the time-varying excitation current is decoupled into voltage stress components and dynamic thermal distribution components. The stress phase and recovery phase in the voltage stress components are tracked, and the interface state trap density modulated by the dynamic thermal distribution components is calculated to obtain the negative bias temperature instability. The kinetic energy gain of channel carriers under electric field acceleration is monitored, and the defect accumulation rate in the oxide layer is calculated by combining the drain current density integral to obtain the hot carrier injection cumulative damage. The interface state trap density and defect accumulation rate are converted into time-increasing damage functions using a multiphysics superposition algorithm, and quantified into circuit aging parameters through a sensitivity coefficient matrix.

[0019] Preferably, the circuit aging parameters are back-mapped to the physical design netlist, and full-chip timing simulation is performed under the boundary conditions of the thermal coupling state. The specific implementation process for generating timing simulation data includes:

[0020] Based on the hierarchical topology of the physical design netlist, an index mapping relationship is established between circuit aging parameters and chip nodes. Non-uniform temperature distribution data in the thermal field coupling state is read, and spatially related environmental process corner constraints are constructed and covered to all chip nodes. Under the environmental process corner constraints, a static timing analysis engine is started to perform delay simulation of the circuit path. The changes in the setup time and hold time margin of the circuit path are monitored, and timing violation nodes caused by circuit aging parameters are extracted to generate timing simulation data characterizing circuit performance degradation.

[0021] Preferably, the specific implementation process of predicting the performance erosion index of the integrated circuit based on the timing simulation data and calculating the dynamic redundancy shrinkage vector between the performance erosion index and the circuit lifetime includes:

[0022] Identify timing violation nodes in the timing simulation data, correlate the delay increment of the corresponding circuit path with the failure rate, and generate a performance erosion index that quantifies the rate of degradation of circuit health. Construct a reliability interval based on the circuit's lifespan, project the performance erosion index onto the reliability interval for probability assessment, and calculate the theoretical failure time under the current process conditions. Convert the theoretical failure time into a compressible space of clock frequency protection band and voltage design margin through sensitivity inversion, and calculate the dynamic redundancy shrinkage vector.

[0023] Preferably, the specific implementation process of converging the reliability assessment of the integrated circuit within the target design range by utilizing a dynamic redundancy reduction vector and adjusting the guard band reduction magnitude in conjunction with the basic process library includes:

[0024] A multi-dimensional design space coordinate system is established using a dynamic redundant shrinkage vector and process angle deviation data from the basic process library. The target design interval is mapped to a multi-objective constraint hyperplane within the coordinate system, and the Euclidean distance between the projection coordinates of the current performance erosion index in the coordinate system and the constraint hyperplane is calculated. A gradient descent search strategy is adopted to convert the Euclidean distance into the adjustment step size of the guard band parameters, and the clock cycle guard band and voltage design margin are iteratively shrunk and corrected. In each correction iteration, the circuit yield prediction curve is updated synchronously, and the degree of fit between the yield prediction curve and the confidence boundary of the target design interval is monitored. When the overlapping area of ​​the two satisfies the presignificance test, the evaluation is determined to be converged and the guard band configuration parameters at this time are locked.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1. This invention generates a time-varying excitation flow by combining transient flip-flop density with chip layout geometry information through thermal conduction mapping, and fully considers the dynamic changes of the actual circuit workload and the complex coupling effects between multiple physical fields such as heat and electricity using a dual-track aging differential mechanism. This improves upon the problem of significantly reduced prediction accuracy caused by worst-case static assumptions or neglecting the transient characteristics of signals, and can more realistically reflect the complex physical state changes inside the device.

[0027] 2. This invention divides the aging sensitive region into a sensitivity partitioning topology, and performs high-precision time-domain integration and aging parameter quantization only within the sensitive region. This method avoids the extremely high computational complexity and time cost of performing high-precision transistor-level SPICE simulation on the entire chip, and is also more accurate than simple logic-level static analysis or lookup table methods, achieving a combination of rapid coverage and accurate testing across the entire chip.

[0028] 3. This invention calculates a dynamic redundancy reduction vector between the performance erosion index and circuit lifetime, and adjusts the guard band reduction accordingly, thus converging the reliability assessment within the target design range. This allows designers to accurately grasp the compressible space, avoiding chip area redundancy, increased power consumption, and wasted nominal performance caused by reserving excessively large design guard bands, accurately reflecting the actual lifetime and reliability level of the circuit under real-world operating conditions. Attached Figure Description

[0029] Figure 1 This is a flowchart of a method for predicting integrated circuit aging effects and assessing circuit lifetime reliability proposed in this invention.

[0030] Figure 2 This is a schematic diagram of the dual-track aging differential mechanism proposed in this invention.

[0031] Figure 3 This is a schematic diagram of the dynamic redundancy shrinkage vector proposed in this invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It must be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to constitute any limitation on the scope of protection of this invention. Therefore, all equivalent changes or modifications conceived by those skilled in the art based on the content disclosed in this invention without inventive effort should fall within the scope of protection claimed by this invention.

[0033] Reference Figures 1 to 3 This invention provides a method for predicting the aging effect of integrated circuits and assessing circuit lifetime reliability. The technical solution is as follows:

[0034] Example 1:

[0035] Reference Figure 1 This embodiment proposes a method for predicting the aging effect of integrated circuits and assessing circuit lifetime reliability, including:

[0036] The physical design netlist and basic process library of the integrated circuit are obtained, and the test load sequence is parsed into the transient flip-flop density of the chip node. The transient flip-flop density is thermally mapped with the chip layout geometry information to generate a time-varying excitation flow that includes node power consumption characteristics and thermal field coupling state.

[0037] The time-varying excitation flow is used to perform sensitivity partitioning topology based on the dual-track aging differential mechanism to divide the aging sensitive domain; the time-varying excitation flow is subjected to time-domain integration within the aging sensitive domain to quantify circuit aging parameters that include negative bias temperature instability and hot carrier injection cumulative damage.

[0038] The circuit aging parameters are back-mapped to the physical design netlist, and full-chip timing simulation is performed under the boundary conditions of the thermal coupling state to generate timing simulation data. The performance erosion index of the integrated circuit is predicted based on the timing simulation data, and the dynamic redundancy shrinkage vector between the performance erosion index and the circuit lifespan is calculated. The dynamic redundancy shrinkage vector is used in conjunction with the basic process library to adjust the guard band reduction range, and the reliability assessment of the integrated circuit is converged within the target design range.

[0039] Furthermore, the specific implementation process of obtaining the physical design netlist and basic process library of the integrated circuit and parsing the test load sequence into the transient flip-flop density of the chip node includes:

[0040] The physical design netlist of the integrated circuit is obtained, and the capacitance and resistance parameters associated with the chip node locations are extracted. Combined with the cell delay characteristics in the basic process library, a static timing analysis map is constructed. The test load sequence is deconstructed into a discrete time-domain signal vector flow, and the signal vector flow is injected into the static timing analysis map according to the timing constraints to perform step-by-step logic state propagation deduction. The voltage level transition behavior of all chip nodes is monitored, and the rising edge and falling edge switching actions are independently statistically accumulated to form an original switching count matrix characterizing the dynamic behavior of the nodes. The original switching count matrix is ​​normalized according to the circuit operating frequency and clock cycle constraints, and the instantaneous switching density reflecting the node activity level is calculated.

[0041] Specifically, the physical design netlist of the target integrated circuit is read through the electronic design automation interface. This netlist typically contains a standard parasitic parameter exchange format file and a gate-level netlist file. From this netlist, parasitic capacitance and parasitic resistance parameters that are highly correlated with the physical location of each chip node are accurately extracted. At the same time, the pre-calibrated standard cell delay characteristic data in the basic process library are called, including the transmission delay and output conversion time of the cell under different loads and slopes. The above physical parameters and timing characteristics are deeply integrated to construct a static timing analysis map that can completely characterize the circuit topology and signal transmission delay in the form of a directed acyclic graph.

[0042] Based on this, the input test load sequence, typically derived from a standard value change dump file, is preprocessed and deconstructed into a discrete-time domain signal vector stream arranged by timestamps. Each vector represents a combination of input states within one clock cycle. According to the timing constraints of the circuit design, including setup time, hold time, and clock skew constraints, the signal vector stream is sequentially injected into the primary input port of the static timing analysis graph. The delay path information in the graph is used to perform a step-by-step logic state propagation deduction, simulating the actual flow of signals in combinational and sequential logic. During this deduction process, a chip-wide node monitoring mechanism is activated to capture the voltage level transition behavior of each circuit node at each moment. The rising edge transition from logic low to high and the falling edge transition from logic high to low are independently statistically analyzed and accumulated, thereby constructing a high-dimensional original flip count matrix in memory. Each element of this matrix corresponds to the absolute number of flips of a circuit node within a specific test time window.

[0043] The original flip-count matrix is ​​normalized based on the circuit operating frequency and clock cycle constraints. The instantaneous flip density, reflecting the node's activity level under the current workload, is calculated by dividing the total number of recorded flips by the total number of clock cycles or the corresponding physical time length. In a preferred embodiment, the chip's main frequency is set to 1 GHz, i.e., the clock cycle is 1 nanosecond. A typical video decoding task containing 10,000 clock cycles is selected as the test load sequence. After constructing the static timing analysis graph, this load is injected. Through logic propagation deduction, it is detected that the output node of a NAND gate on a critical path inside the chip experienced 2,500 rising edge flips and 2,500 falling edge flips during this period, totaling 5,000 level transitions. At this time, the count value of this node is recorded in the original flip-count matrix and normalized. Dividing the 5,000 transitions by the baseline of 10,000 clock cycles, the instantaneous flip density of this node is calculated to be 0.5. This data precisely indicates that the node undergoes a logical state change on average every two clock cycles, classifying it as a highly active node.

[0044] This embodiment improves upon the accuracy bias caused by relying solely on average toggle rate or static probability estimation by combining static circuit topology parameters with dynamic time-domain signal vectors. Instantaneous toggle density not only accurately captures the true dynamic behavior of the circuit under specific functional modes and can identify local high-frequency toggle hotspots caused by logic depth or fan-in / fan-out characteristics, but also provides a highly discriminative data foundation for subsequent accurate calculation of different types of aging mechanisms by distinguishing between rising and falling edges, significantly improving the spatial resolution and quantization accuracy of aging prediction.

[0045] Furthermore, the specific implementation process of thermally mapping the transient flip density with the chip layout geometry to generate a time-varying excitation flow containing node power consumption characteristics and thermal field coupling state includes:

[0046] The transient flip density is combined with the chip layout geometry information to transform it into an instantaneous power sequence that fluctuates over time for each chip node. A three-dimensional thermal resistance-capacitance network is established based on the thermal conductivity and specific heat capacity characteristics of the chip material. The instantaneous power sequence is used as a heat source excitation and mapped to the corresponding thermal analysis grid cell. The heat flow diffusion process is transiently solved within the three-dimensional thermal resistance-capacitance network to calculate the local temperature field evolution curve formed by the superposition of device self-heating effect and mutual heating effect of adjacent regions. The local temperature field evolution curve is time-domain synchronized and data correlated with the original voltage logic signal to integrate it into a time-varying excitation flow.

[0047] Specifically, the layout geometry information file of the integrated circuit, such as GDSII or OASIS format data, is read to parse the specific coordinates, dimensions, and interconnect routing levels of each standard cell in the chip's physical space. Based on the parasitic parameters extracted from the layout, the load capacitance of each node is calculated. The obtained transient switching density is then combined with this load capacitance and operating voltage. Using dynamic power consumption calculation principles, the abstract switching density value is transformed into a time-varying instantaneous power sequence for each chip node. This sequence accurately depicts the transient changes in energy consumption in various tiny regions within the chip on a nanosecond timescale.

[0048] To simulate the heat conduction process within the chip, a high-resolution three-dimensional thermal resistance-capacitance (TRC) network is constructed by meshing the chip's physical structure using the inherent physical properties of the substrate material (e.g., single-crystal silicon), dielectric layer material (e.g., silicon dioxide), and metal interconnect layer material (e.g., copper or aluminum) employed in chip manufacturing. These properties include thermal conductivity and specific heat capacity. The TRC network discretizes the chip in three-dimensional space into numerous tiny thermal analysis grid cells, each composed of equivalent thermal resistance and heat capacity. The previously calculated instantaneous power sequence is used as a time-varying heat flow source excitation, precisely loaded onto the center of the corresponding thermal analysis grid cell according to the physical coordinate mapping relationship, serving as the input to drive the evolution of the thermal network. The heat flow diffusion process is solved transiently within the three-dimensional TRC network based on a time step. This process not only calculates the temperature rise of each device due to its own power consumption (i.e., the device self-heating effect) but also calculates the impact of lateral heat diffusion from adjacent high-power regions on the current region through the thermal resistance connections of the network (i.e., the neighboring region mutual heating effect). Through this multi-physics coupling calculation, the local temperature field evolution curve of each grid cell across the entire chip is output. The local temperature field evolution curve in the thermal dimension is strictly aligned with the original voltage logic signal in the electrical dimension on the time axis, ensuring that each circuit node at any given moment not only has voltage state data but also precise instantaneous temperature data. This integrates and generates a time-varying excitation stream that includes node power consumption characteristics and thermal field coupling state. The data structure of the time-varying excitation stream uses the unique node index in the physical design netlist as the row address and the discretized simulation time step or clock cycle sequence as the column address. Each memory cell encapsulates a composite state vector containing multiple physical attributes. This vector specifically includes values ​​in four dimensions: first, the current voltage logic level state, used to establish the aging bias condition; second, a signal toggle identifier, clearly recording whether a rising or falling edge transition occurred at that moment; third, the transient power consumption value, quantifying the energy dissipation of the node at the current time step; and fourth, the local absolute temperature value calculated by thermal conduction. This structured definition makes the time-varying excitation flow essentially a physical field lookup table that is strictly aligned in time and space, ensuring that the electrical and thermal stress data of the same node at any time can be directly read through a unified time index.

[0049] In a preferred embodiment, a region of 2 square millimeters is divided into 20-micrometer by 20-micrometer grid cells. During a high-intensity floating-point arithmetic test load, severe power fluctuations were identified in the arithmetic logic unit region located at the core. Transient solving of the three-dimensional thermal resistive-capacitive network revealed that although the average temperature of this region was only 65 degrees Celsius, significant mutual heating was triggered within a clock cycle due to the simultaneous full-load switching of two adjacent adder units, causing the local hotspot temperature to spike sharply to 92 degrees Celsius within 50 nanoseconds before rapidly decreasing. Correlating this local temperature field evolution curve, including the 92-degree Celsius peak, with the clock and data signals of the node generated a time-varying excitation current.

[0050] This embodiment, by constructing a three-dimensional thermal resistive-capacitive network and performing transient solutions, can accurately capture thermal spikes caused by rapid switching of circuit operating modes and spatial thermal coupling effects. Since the circuit aging mechanism is extremely sensitive to temperature changes and exhibits a nonlinear dependence, this high-precision spatiotemporal thermal distribution mapping allows subsequent aging parameter calculations to be based on real physical conditions. This significantly improves the accuracy of lifetime prediction for local hot spots and avoids the risk of overestimating or underestimating reliability due to neglecting transient thermal effects.

[0051] Furthermore, the specific implementation process of using the time-varying excitation flow to perform sensitivity partitioning topology based on the dual-track aging differential mechanism to divide the aging sensitive domain includes:

[0052] The dual-track aging differential mechanism includes two evaluation channels. In the first evaluation channel, the accumulation rate of oxide interface state traps in the circuit chip is calculated by combining local temperature field data and the duration of static low level. In the second evaluation channel, the hot carrier collision ionization intensity of the circuit chip is calculated by combining signal edge transition rate and channel peak current density. The accumulation rate of oxide interface state traps and the hot carrier collision ionization intensity are fused according to the time-varying excitation current to generate a comprehensive sensitivity distribution matrix that maps the aging susceptibility of the entire chip device. The comprehensive sensitivity distribution matrix is ​​projected onto the topology of the integrated circuit to screen out the set of circuit paths with accumulated damage potential values ​​higher than the safety threshold and classify them into aging sensitive regions.

[0053] Reference Figure 2Specifically, the dual-track aging differential mechanism logically constructs two independent evaluation channels to handle static and dynamic aging effects respectively. In the first evaluation channel, the negative bias temperature instability effect is primarily evaluated. Local temperature field data from the time-varying excitation current is read, and combined with the duration of the static low level of the circuit node within the operating cycle, the dynamics of silicon-hydrogen bond breaking at the transistor gate oxide interface in the circuit chip are calculated based on the Arrhenius equation and reaction-diffusion calculations, thereby quantifying the accumulation rate of the oxide interface state traps. In the second evaluation channel, the hot carrier injection effect is evaluated. The edge transition rate (i.e., slew rate) and peak current density in the channel are extracted during the signal switching process. The collisional ionization probability of high-energy carriers under the strong electric field at the drain is calculated, thereby quantifying the hot carrier collisional ionization intensity.

[0054] Based on the time axis information of the time-varying excitation flow, the accumulation rate of oxide interface state traps calculated by the first channel and the hot carrier collisional ionization intensity calculated by the second channel are weighted and superimposed. To ensure the accuracy of data fusion and eliminate the problem of inconsistent dimensions between different physical effects, before weighting and superimposing, a maximum value normalization algorithm is used to map the accumulation rate of oxide interface state traps calculated by the first channel and the hot carrier collisional ionization intensity calculated by the second channel to a dimensionless numerical range of 0 to 1, respectively. On this basis, the weighting and superimposing process adopts a dynamic weight allocation strategy according to the device type and the physical field dominance mechanism. For P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), which are more sensitive to negative bias temperature instability, the weight coefficient of the first evaluation channel is set to the main proportion, for example, between 0.6 and 0.8, while the second evaluation channel is set to the secondary proportion. Conversely, for N-type MOSFETs, which are more significantly affected by the hot carrier injection effect, the weight allocation ratio is reversed, and the weight coefficient of the second evaluation channel is increased accordingly. An adaptive correction mechanism triggered by temperature is introduced. When the local temperature field data shows that the temperature in a certain area exceeds the process specification, the weight value of the first evaluation channel will be further nonlinearly increased by using the logarithmic linear relationship of the Arrhenius acceleration factor to reflect the exponential acceleration effect of the high temperature environment on the interface state generation rate.

[0055] This process comprehensively considers the accelerating effect of temperature on negative bias temperature instability and the cumulative effect of switching frequency on hot carrier injection, generating a comprehensive sensitivity distribution matrix that maps the aging susceptibility of all devices on the entire chip under current operating conditions. Each value in this matrix represents the expected aging loss of the corresponding device per unit time. The comprehensive sensitivity distribution matrix is ​​projected onto the netlist topology of the integrated circuit, mapping the abstract aging values ​​back to specific logic gates and interconnect paths. A safety threshold based on process design rules and reliability specifications is set, and the entire chip path is traversed and scanned to identify the set of circuit paths whose cumulative damage potential exceeds the safety threshold. The region formed by these high-risk paths and their associated devices is defined as the aging sensitivity domain, serving as the focus for subsequent high-precision lifetime prediction. In a preferred embodiment, a dual-track aging differential mechanism is used to analyze a key clock tree driver module within the chip. In the first evaluation channel, a certain PMOS buffer in the module was found to be in a low-level logic state for 85% of the operating time due to the clock gating logic. Furthermore, the dense surrounding wiring caused the local temperature to remain at 95 degrees Celsius for an extended period. Calculations showed that the accumulation rate of the oxide layer interface state traps was extremely high, with a normalization coefficient of 0.85. In the second evaluation channel, the signal rise edge of the buffer in the active state was found to be extremely steep, with a transition time of only 20 picoseconds, resulting in a high instantaneous peak current density. The normalization coefficient for the hot carrier collisional ionization intensity was calculated to be 0.4. Combining these two results, the overall sensitivity score for this node was 1.25. The safety threshold for the clock tree drive module is 0.6. Since the node's score of 1.25 is significantly higher than the threshold of 0.6, the clock drive path was determined to be in a high-risk area and successfully classified into the aging sensitive domain.

[0056] This embodiment improves the trade-off between computational resources and prediction accuracy in full-chip aging analysis by employing a dual-track aging differential mechanism and sensitivity partitioning topology. By distinguishing between two different physical mechanisms—negative bias temperature instability and hot carrier injection—and combining them with thermoelectric coupling states for comprehensive scoring, it can pinpoint aging-sensitive regions that are truly at risk of failure, thus significantly improving evaluation efficiency.

[0057] Furthermore, the specific implementation process of performing time-domain integration on the time-varying excitation current within the aging sensitive domain to quantify it into circuit aging parameters that include negative bias temperature instability and accumulated damage from hot carrier injection includes:

[0058] Chip nodes within the aging-sensitive domain are extracted, and the time-varying excitation current is decoupled into voltage stress components and dynamic thermal distribution components. The stress phase and recovery phase in the voltage stress components are tracked, and the interface state trap density modulated by the dynamic thermal distribution components is calculated to obtain the negative bias temperature instability. The kinetic energy gain of channel carriers under electric field acceleration is monitored, and the defect accumulation rate in the oxide layer is calculated by combining the drain current density integral to obtain the hot carrier injection cumulative damage. The interface state trap density and defect accumulation rate are converted into time-increasing damage functions using a multiphysics superposition algorithm, and quantified into circuit aging parameters through a sensitivity coefficient matrix.

[0059] Specifically, all chip nodes of interest and their associated transistors within the aging-sensitive domain are extracted. The time-varying excitation currents applied to these nodes are decoupled into two independent but time-synchronized physical components: a voltage stress component characterizing the node voltage logic state switching and electric field strength, and a dynamic thermal distribution component characterizing the real-time temperature fluctuations of the nodes. To quantify the negative bias temperature instability effect, the voltage stress component is phase-tracked cycle-by-cycle to identify the stress phase (i.e., gate low level) and recovery phase (i.e., gate high level) when the PMOS transistor is in the on state. Reaction-diffusion calculations are introduced to calculate the generation rate of interface state traps during the stress phase and the annealing healing rate of the traps during the recovery phase. During this process, the dynamic thermal distribution component is introduced in real-time as a temperature variable in the Arrhenius equation to nonlinearly modulate the reaction rate constant. The reaction-diffusion calculations are specifically a set of first-order differential equations describing the kinetics of silicon-hydrogen bond breaking and recombination. The moment when the PMOS transistor gate voltage is at a logic low level is strictly defined as the stress phase, and the moment when it is at a logic high level is defined as the recovery phase. In the numerical solution process, the forward difference iterative method is used to discretize the differential equation and calculate the increment of the interface state trap density within each tiny time step. This increment is determined by the difference between the forward dissociation rate and the reverse annealing rate, where the forward reaction rate constant is updated in real time according to the Arrhenius equation.

[0060] By integrating over the entire time axis, the instantaneous interface state trap density modulated by thermoelectric dynamic stress is calculated, thus obtaining accurate data on the negative bias temperature instability. To quantify the hot carrier injection effect, the carrier behavior within the transistor channel is monitored. Based on the drain-source voltage difference and gate-source voltage difference in the voltage stress components, the channel electric field distribution is calculated, and the kinetic energy gain of channel carriers under strong electric field acceleration is monitored. High-energy electrons (i.e., hot electrons) with energies exceeding the oxide barrier height are identified, and by integrating with the drain current density, the accumulation rate of these hot electrons impacting the oxide interface and generating permanent lattice defects is calculated, thus obtaining the accumulated damage from hot carrier injection.

[0061] A multiphysics superposition algorithm is employed to physically fuse the calculated interface state trap density and defect accumulation rate. Since negative bias temperature instability primarily causes a negative shift in threshold voltage, and hot carrier injection mainly affects transconductance and saturation current, a time-increasing comprehensive damage function is constructed. This damage function is then mapped and converted into circuit aging parameters recognizable by a circuit simulator using a sensitivity coefficient matrix. The specific construction process of the sensitivity coefficient matrix involves selecting representative standard transistor cells from the process library and introducing gradient oxide charge density and interface state density as perturbation variables in the simulation environment to simulate different levels of physical damage. DC characteristic scans are performed on transistors under each damage level to monitor changes in key electrical indicators such as threshold voltage drift, carrier mobility degradation rate, and saturation current decay. By performing linear regression or polynomial fitting between the physical damage variables and the changes in electrical indicators, the electrical parameter drift caused by a unit increase in defect density is calculated, and these values ​​are defined as sensitivity coefficients. The sensitivity coefficients corresponding to transistors with different aspect ratios and threshold types are integrated into a matrix for storage. In subsequent processing, the cumulative damage calculated in real time is multiplied by this matrix to quickly obtain aging model parameters that can be directly recognized by the circuit simulator, thus opening up the mapping path from microscopic physical damage to macroscopic circuit performance degradation.

[0062] In a preferred embodiment, a key inverter PMOS transistor in the circuit path is extracted for analysis. By decoupling the time-varying excitation current, it was observed that the device operates at high temperatures (average 105 degrees Celsius) and frequently switches under heavy graphics rendering tasks. Instead of simply using the constant stress assumption in the negative bias temperature instability analysis, the self-recovery effect of the device during idle periods was accurately captured, and the threshold voltage drift component caused by the interface state trap density was calculated to be 25 mV. In the hot carrier injection analysis, the threshold voltage drift component caused by hot carrier injection was calculated to be 15 mV due to high-frequency switching. Through the multiphysics superposition algorithm and sensitivity coefficient matrix processing, the total threshold voltage drift of the device is finally output. This set of precise circuit aging parameters is then backfeeded into the netlist to evaluate whether the circuit will experience timing violations due to device aging.

[0063] This embodiment does not neglect the recovery effect of negative bias temperature instability and the nonlinear modulation of the aging rate by temperature fluctuations, greatly improving the physical realism and quantification accuracy of aging prediction. By decoupling and integrating the time-varying excitation flow in the time domain, and especially by accurately tracking the dynamic alternation of stress and recovery phase and the real-time modulation of the thermal field, the physical process of device aging is reproduced. This provides reliability assessment data that matches the actual operating life of the chip, helping designers find the optimal balance between performance and reliability.

[0064] Furthermore, the circuit aging parameters are inversely mapped to the physical design netlist, and full-chip timing simulation is performed under the boundary conditions of the thermal field coupling state. The specific implementation process for generating timing simulation data includes:

[0065] Based on the hierarchical topology of the physical design netlist, an index mapping relationship is established between circuit aging parameters and chip nodes. Non-uniform temperature distribution data in the thermal field coupling state is read, and spatially related environmental process corner constraints are constructed and covered to all chip nodes. Under the environmental process corner constraints, a static timing analysis engine is started to perform delay simulation of the circuit path. The changes in the setup time and hold time margin of the circuit path are monitored, and timing violation nodes caused by circuit aging parameters are extracted to generate timing simulation data characterizing circuit performance degradation.

[0066] Specifically, a unique index mapping is established between the instance name of each transistor device and the circuit aging parameters across the entire chip, based on the hierarchical topology of the physical design netlist. This mapping is accomplished by constructing a hash-based lookup table structure in memory, using the hierarchical full path name of each device in the physical design netlist as the unique key and storing the circuit aging parameters as attribute values. For a logic cell containing multiple timing arcs or multiple physical finger transistors, the single circuit aging parameter belonging to that device instance is automatically broadcast and mapped to all input / output timing paths and parallel structures within that cell, ensuring that all relevant setup and hold time checkpoints synchronously inherit the same aging state. Non-uniform temperature distribution data in the thermal coupling state is read and mapped to the chip's physical coordinate system, constructing spatially correlated environmental process angle constraints. Corresponding local real-time temperature values ​​are assigned to logic gates and interconnects at different coordinate positions, thus forming fine-grained operating condition settings covering all chip nodes. Based on this, the static timing analysis engine is launched, loading the physical design netlist and the modified process library containing aging information. Under the environmental process corner constraints, the delay of each circuit path is simulated one by one. When calculating the propagation delay and interconnect delay of each logic gate, the degradation of device driving capability caused by the circuit aging parameters and the delay drift caused by local temperature are considered simultaneously. During the simulation, the setup time and hold time margin changes of each critical circuit path are monitored in real time. The currently calculated path delay is compared with the clock cycle requirement to accurately extract the timing violation nodes caused by the circuit aging parameters. The start and end points of all violation paths, the violation type (setup time violation or hold time violation), and the violation magnitude (i.e., negative margin value) are summarized to generate a detailed timing simulation data characterizing the circuit performance degradation.

[0067] In a preferred embodiment, mapping the circuit aging parameters revealed that an adder module located in the chip's central region experienced a 40 mV threshold voltage drift in its critical path due to prolonged exposure to a high temperature of 90 degrees Celsius and frequent switching. The non-uniform temperature distribution data showed that this region's temperature was 30 degrees Celsius higher than the edge regions. After activating the static timing analysis engine, under the environmental process corner constraints, the total delay of this adder path was calculated to have increased from 420 picoseconds initially designed to 515 picoseconds. Given a clock cycle of 500 picoseconds, this means the path exhibited a -15 picosecond settling time margin. This settling time violation was detected, and the adder output node was marked as an aging failure node, generating timing simulation data containing the detailed delay structure of the path and the -15 picosecond violation value.

[0068] This embodiment improves upon the problems of overly pessimistic design caused by the use of globally uniform worst-case assumptions or optimistic misjudgments caused by ignoring local hotspots in timing analysis methods by constructing a dual-constraint environment of aging awareness and thermal awareness. By accurately mapping spatially relevant temperature distributions back to the netlist with device-level aging parameters, the performance of the chip at the end of its life cycle can be pre-simulated during the design phase. This allows designers to pinpoint the weak links that will fail first due to thermal aging coupling effects, thereby optimizing weak links in a targeted manner without sacrificing the overall chip area and power consumption.

[0069] Furthermore, the specific implementation process of predicting the performance erosion index of the integrated circuit based on the timing simulation data, and calculating the dynamic redundancy shrinkage vector between the performance erosion index and the circuit lifetime includes:

[0070] Identify timing violation nodes in the timing simulation data, correlate the delay increment of the corresponding circuit path with the failure rate, and generate a performance erosion index that quantifies the rate of degradation of circuit health. Construct a reliability interval based on the circuit's lifespan, project the performance erosion index onto the reliability interval for probability assessment, and calculate the theoretical failure time under the current process conditions. Convert the theoretical failure time into a compressible space of clock frequency protection band and voltage design margin through sensitivity inversion, and calculate the dynamic redundancy shrinkage vector.

[0071] Reference Figure 3Specifically, the timing simulation data is analyzed, which contains the delay distribution of the entire chip's critical paths after aging. All timing violation nodes marked as setup or hold-up violations are identified, as well as critical nodes that, while not violating timing rules, have significantly reduced margins. The specific calculation process for the performance erosion index is as follows: The Weibull distribution shape parameter (usually set to a value greater than 1 to characterize the device entering the wear-out phase) and characteristic lifetime parameter for the current semiconductor process node are retrieved from the basic process library. For each marked critical node, the ratio of the absolute value of its delay increment calculated in the current aging simulation to the initial timing margin is used as a normalized stress variable and substituted into the Weibull cumulative distribution function to calculate the conditional failure probability of a single path at the current moment. Based on the weakest-cycle theory, assuming that the failure mechanisms of each critical path are statistically independent, the joint survival probability of all paths simultaneously remaining unfailed is first calculated using the probability multiplication rule. Then, the result of subtracting this joint survival probability from the value of 1 is output as the performance erosion index. This index intuitively characterizes the rate at which the overall health of a circuit decays over time; a higher index indicates that the circuit performance deteriorates more rapidly due to aging effects. Based on the integrated circuit's product specifications or user-defined requirements, a target lifespan for the circuit is set (e.g., 10 or 15 years for industrial-grade chips), and a reliability interval including confidence boundaries is constructed accordingly. Using statistical extrapolation, the currently calculated performance erosion index is projected onto the time axis of this reliability interval for probabilistic evaluation. The time required for the critical path delay to reach the timing constraint boundary, assuming a yield requirement (e.g., 99.9%), is calculated, thereby determining the theoretical failure time under current process conditions and workload.

[0072] Based on this, a reverse sensitivity analysis is performed. If the calculated theoretical failure time is greater than the target lifespan, it indicates that the current design has redundancy; otherwise, there is a risk. The difference between the theoretical failure time and the target lifespan (i.e., lifespan margin or deficit) is converted into an adjustable range of physical design parameters through sensitivity inversion. This involves the extent to which the clock frequency can be increased (frequency protection band compression) or the extent to which the supply voltage can be reduced (voltage design margin compression) to ensure the circuit operates just to the end of the target lifespan. The adjustment values ​​of these two physical quantities are integrated into a vector data, namely the dynamic redundancy reduction vector.

[0073] In a preferred embodiment, under the non-uniform thermal distribution of real-world workloads, the performance erosion index of the circuit path is lower than expected, with its latency increment increasing by only 8% at the end of 10 years, instead of the estimated 15%. Projecting this index, the theoretical failure time of the chip under the current design margin is calculated to be as long as 13.5 years, far exceeding the 10-year target. The dynamic redundancy reduction vector is then calculated: given the additional 3.5-year lifetime margin, combined with the sensitivity model (assuming a 0.8-year reduction in lifetime for every 10mV voltage decrease; or a 0.5-year reduction in lifetime for every 10MHz frequency increase), the current design has compressible space for either a 40mV voltage reduction or a 50MHz frequency increase. The final output dynamic redundancy reduction vector indicates that designers can adjust the operating voltage to 0.86V or set the nominal frequency to 850MHz while still meeting the 10-year reliability requirement.

[0074] This embodiment achieves a leap from qualitative assessment to quantitative optimization by quantifying the performance erosion index and dynamic redundancy reduction vector, thus improving the chip area increase or power consumption waste caused by using a fixed guard band. By calculating the deviation between the theoretical failure time and the target lifetime, the hidden redundancy space in the design is identified, allowing designers to compress design margins while ensuring reliability, thereby significantly improving the chip's performance-to-power ratio and achieving the optimal balance between circuit lifetime and performance.

[0075] Furthermore, the specific implementation process of converging the reliability assessment of integrated circuits within the target design range by utilizing dynamic redundancy reduction vectors and adjusting the guard band reduction magnitude in conjunction with the basic process library includes:

[0076] A multi-dimensional design space coordinate system is established using a dynamic redundant shrinkage vector and process angle deviation data from the basic process library. The target design interval is mapped to a multi-objective constraint hyperplane within the coordinate system, and the Euclidean distance between the projection coordinates of the current performance erosion index in the coordinate system and the constraint hyperplane is calculated. A gradient descent search strategy is adopted to convert the Euclidean distance into the adjustment step size of the guard band parameters, and the clock cycle guard band and voltage design margin are iteratively shrunk and corrected. In each correction iteration, the circuit yield prediction curve is updated synchronously, and the degree of fit between the yield prediction curve and the confidence boundary of the target design interval is monitored. When the overlapping area of ​​the two satisfies the presignificance test, the evaluation is determined to be converged and the guard band configuration parameters at this time are locked.

[0077] Specifically, a multi-dimensional design space coordinate system is established in a multi-dimensional data space by utilizing a dynamic redundancy shrinkage vector and combining it with deviation data from different process angles (fast, slow, and typical) covered in the basic process library. The dimensions of this multi-dimensional design space coordinate system include operating voltage, clock frequency, ambient temperature, aging time, and process deviation parameters. The target design range of the integrated circuit (i.e., the range of performance, power consumption, and lifetime requirements specified in the product datasheet) is mapped to a multi-objective constraint hyperplane defined by a system of inequalities within this coordinate system. The current circuit design state (including the initial guard band setting) is represented as a point in the coordinate system. The Euclidean distance between the projection coordinates of the current performance erosion index in this coordinate system and the multi-objective constraint hyperplane is calculated. This distance directly reflects how much room for reduction the current design has from the ideal boundary of "optimization and safety."

[0078] A gradient descent search strategy is employed to find the optimal guard band configuration, and the calculated Euclidean distance is converted into a step size parameter for each iteration. The convergence speed of the step size is controlled to iteratively shrink and correct the original clock cycle guard band and voltage design margin. In each iteration, a slight decrease in voltage or a slight increase in frequency is attempted to approximate the multi-objective constrained hyperplane. However, simple parameter shrinkage may lead to a decrease in yield. Therefore, during each correction iteration, statistical yield analysis is synchronously invoked, and the current circuit yield prediction curve is updated based on Monte Carlo simulation. The fit between this yield prediction curve and the confidence boundary of the target design range (e.g., the performance boundary corresponding to 99.9% yield) is monitored in real time. A pre-significance test is performed to determine whether the tail of the yield curve has touched or slightly crossed the safety threshold of the target reliability. When the characteristic statistics of the overlapping area (e.g., the P-value) meet the test criteria, the evaluation process is considered to have converged, indicating that the guard band has been reduced to its physical limit; further reduction will lead to unacceptable yield. The current protection strip configuration parameters are then locked and output as the final optimization result.

[0079] In a preferred embodiment, the chip design includes an 18% clock frequency guard band (i.e., timing convergence at 1.41GHz) and a 10% voltage margin (nominal value of 0.8V, actual design approved at 0.72V). A multi-dimensional design space coordinate system is established, and calculations reveal a significant Euclidean distance between the current design point and the multi-objective constraint hyperplane, indicating substantial overdesign. A gradient descent search is initiated using a dynamic redundancy shrinkage vector for iterative optimization. In the first iteration, the frequency guard band is reduced to 15%, while the voltage margin remains unchanged. The updated circuit yield prediction curve shows a yield of 100%, not reaching the boundary. After multiple iterations, when the frequency guard band is reduced to 6.5% and the voltage margin to 3%, the 3-sigma boundary of the yield prediction curve begins to overlap with the confidence boundary of the target design interval, and the pre-significance test is passed (confidence level set at 95%). At this point, convergence was determined, and the configuration of "6.5% clock protection band" and "3% voltage margin" was locked.

[0080] This embodiment automates the trade-off process of guard bands by constructing a multi-dimensional design space coordinate system and gradient descent updates. It guides the optimization direction based on Euclidean distance and uses yield prediction curves as a safety mechanism to ensure that while improving every bit of chip performance potential, mass production yield and long-term reliability are not sacrificed. This achieves optimization of integrated circuit design in terms of performance, power consumption, area and reliability.

[0081] Example 2:

[0082] This embodiment fully deploys the aforementioned method for predicting integrated circuit aging effects and assessing circuit lifetime reliability in a factory's automotive-grade microcontroller chip quality inspection and design optimization system. The aim is to improve the problem of excessive design margins or reliability failures caused by inaccurate aging effect prediction in high-performance automotive electronic chips operating under extreme temperatures and long-term cycles.

[0083] Furthermore, the system obtains the chip's physical design netlist and the corresponding 28nm basic process library through the electronic design automation (EDA) interface. To simulate the chip's operation in a real automotive environment, a 10-second "autopilot cruise mode" data stream is selected as the test load sequence. The system first performs a transient flip-flop density analysis process, extracting the parasitic capacitance and resistance parameters associated with all nodes in the physical netlist. Combined with the standard cell delay characteristics in the process library, a static timing analysis graph of the entire chip is constructed. The test load sequence is deconstructed into discrete time-domain signal vector streams and injected into the graph according to timing constraints for step-by-step logic state propagation deduction. During this process, the voltage level transition behavior of millions of nodes across the entire chip is monitored, and rising and falling edge flip-flops are counted independently. For example, a critical node A in the arithmetic logic unit is detected to have undergone 500 million flips within 10 seconds. Based on the chip's 2GHz operating frequency and clock cycle constraints, the system normalizes the original count value and calculates the instantaneous flip-flop density of node A as 0.25, thus quantifying the node's activity level.

[0084] Furthermore, the system establishes an electrothermal coupling model. The calculated transient flip-flop density is combined with the chip's layout geometry (GDSII data) and transformed into a time-varying instantaneous power sequence for each node using a dynamic power consumption formula. Based on the thermal conductivity and specific heat capacity characteristics of the single-crystal silicon substrate and silicon dioxide dielectric layer, the system performs meshing of the chip's physical structure, establishing a high-precision three-dimensional thermal resistance-capacitance network. The instantaneous power sequence is mapped as a heat source excitation to the corresponding mesh cells, and the transient thermal solver is activated to calculate the heat flow diffusion process. The system simultaneously calculates the device's self-heating effect and the mutual heating effect of adjacent high-power modules on the chip core, generating a local temperature field evolution curve. This temperature curve is time-domain synchronized and aligned with the original voltage logic signal, integrating it into a time-varying excitation flow that includes node power consumption characteristics and thermal field coupling states.

[0085] Furthermore, a dual-track aging differential mechanism is used to partition the entire chip based on its sensitivity. In the first evaluation channel, the system combines the local high-temperature data (105 degrees Celsius) of node A with its duration in the logic low-level state to calculate the accumulation rate of oxide interface state traps, thereby assessing negative bias temperature instability. In the second evaluation channel, the system combines the signal edge transition rate of node A (e.g., a rise time of 20 ps) with the channel peak current density to calculate the hot carrier collisional ionization intensity, thereby assessing the hot carrier injection effect. The system weights and fuses these two sets of data to generate a comprehensive sensitivity distribution matrix, which is then projected onto the circuit topology. A cumulative damage safety threshold of 0.6 is set, and the system identifies a set of critical timing paths, including node A, whose cumulative damage potential exceeds this threshold, and classifies them as aging sensitive regions. This step effectively filters out more than 90% of the non-critical paths across the entire chip, significantly reducing subsequent computational load.

[0086] Furthermore, the system performs high-precision time-domain integration within the aging-sensitive domain. Chip nodes within the sensitive domain are extracted, and the time-varying excitation current is decoupled into voltage stress components and dynamic thermal distribution components. The system accurately tracks the stress phase and recovery phase in the voltage stress component, calculates the interface state trap density modulated by the dynamic thermal distribution component (real-time temperature), and obtains the negative bias temperature instability aging parameters. Simultaneously, it monitors the kinetic energy gain of channel carriers under electric field acceleration, and calculates the oxide layer defect accumulation rate by combining drain current integration, obtaining the hot carrier injection aging parameters. A multiphysics superposition algorithm is used to convert both into a time-increasing damage function. Through sensitivity coefficient matrix quantization, it is predicted that at the end of the 15-year design life of the vehicle, the threshold voltage of the PMOS transistor at node A will drift by 45 mV, and the carrier mobility will decrease by 8%.

[0087] Furthermore, the aforementioned circuit aging parameters are mapped back to the physical design netlist for full-chip timing simulation. The system reads the non-uniform temperature distribution data in the thermal coupling state, constructs spatially relevant environmental process corner constraints, and covers the entire chip. Under these constraints, a static timing analysis engine is launched to perform delay simulations on the aged circuit. Monitoring revealed that due to the drift of the aging parameters of node A, the total delay of the critical path where it is located increased by 120 picoseconds, causing the settling time margin to change from a positive value at the initial design stage to -15 picoseconds, resulting in a timing violation. Based on this, the system generates timing simulation data characterizing the circuit performance degradation.

[0088] Furthermore, the system predicts the performance erosion index and calculates the dynamic redundancy reduction vector based on timing simulation data. The system identifies the aforementioned timing violation nodes, correlates the path delay increment with the failure rate model, and generates a performance erosion index. Projecting this index onto a 15-year reliability range, it calculates that under current process conditions, the theoretical failure time of the chip is only 13.8 years, which fails to meet the 15-year automotive-grade requirement. To correct this deficiency, the system uses sensitivity inversion to calculate that either the operating voltage needs to be increased by 20 millivolts or the maximum clock frequency reduced by 50 MHz to meet the lifespan requirement, thereby calculating the specific dynamic redundancy reduction vector.

[0089] Furthermore, the guard band configuration is optimized using a dynamic redundancy shrinkage vector. The system establishes a multi-dimensional design space coordinate system, mapping the target design interval to a constraint hyperplane, and calculates the Euclidean distance between the current state and the hyperplane. A gradient descent search strategy is employed, converting this distance into an adjustment step size to iteratively correct the clock cycle guard band and voltage design margin. During the correction process, the circuit yield prediction curve is updated synchronously, and its fit with the target interval is monitored. After multiple iterations, the system finally determines an optimized scheme that moderately widens the voltage design margin while shrinking the clock frequency guard band. When the overlap between the yield prediction curve and the target interval meets the pre-significance test, the evaluation is considered converged. Ultimately, the factory adopted this optimized configuration, resulting in a 5% reduction in chip area while meeting a 15-year reliability lifespan, and mitigating the potential failure risk caused by localized overheating.

[0090] This embodiment significantly improves the physical realism and accuracy of aging prediction by constructing a time-varying excitation flow that includes node power consumption characteristics and thermal field coupling states. By capturing thermoelectric coupling behavior, especially by aligning the evolution of the local temperature field with the time domain of the logic signal, it can reproduce the real physical conditions and effectively improve the reliability assessment distortion problem caused by ignoring transient thermal effects.

[0091] By employing a dual-track aging differential mechanism and a sensitivity partitioning strategy, the trade-off between computational efficiency and prediction accuracy in full-chip-level aging simulation is mitigated. By distinguishing between two different physical aging mechanisms and selecting high-risk aging-sensitive domains for focused analysis, the enormous computational power consumption caused by indiscriminate high-precision simulation across the entire chip is avoided, while ensuring zero omissions in capturing aging damage along critical paths, thus achieving a balance between evaluation efficiency and accuracy.

[0092] A dynamic redundancy reduction vector and guard band iterative optimization method is proposed. By quantitatively transforming the performance erosion index into a compressible design space and performing gradient descent search within the multi-dimensional design space, the clock frequency guard band and voltage design margin can be reduced while meeting strict reliability and lifetime requirements. This not only eliminates redundancy waste in the design and reduces chip area and power consumption, but also significantly improves the nominal performance indicators of the integrated circuit.

[0093] It should be clarified that the embodiments described above are merely exemplary and are intended to aid in understanding the present invention, not to limit it. Those skilled in the art can make various changes and modifications after grasping the core ideas of the present invention.

Claims

1. A method for predicting aging effects and assessing circuit lifetime reliability in integrated circuits, characterized in that, include: Obtain the physical design netlist and basic process library of integrated circuits, and parse the test load sequence into the transient flip-flop density of chip nodes; The transient flip density is thermally mapped to the chip layout geometry to generate a time-varying excitation flow that includes node power consumption characteristics and thermal field coupling state; The specific implementation process of using the time-varying excitation flow to perform sensitivity partitioning topology based on the dual-track aging differential mechanism to divide the aging sensitive domain includes: the dual-track aging differential mechanism contains two evaluation channels. In the first evaluation channel, the accumulation rate of oxide interface state traps in the circuit chip is calculated by combining local temperature field data and the duration of static low level. In the second evaluation channel, the hot carrier collision ionization intensity of the circuit chip is calculated by combining signal edge transition rate and channel peak current density. Data fusion of the accumulation rate of oxide interface state traps and the hot carrier collision ionization intensity is performed based on the time-varying excitation flow to generate a comprehensive sensitivity distribution matrix that maps the aging susceptibility of the entire chip device. The comprehensive sensitivity distribution matrix is ​​projected onto the topology of the integrated circuit to screen out the set of circuit paths with accumulated damage potential values ​​higher than the safety threshold and divide them into... The aging sensitive domain; the specific implementation process of performing time-domain integration on the time-varying excitation flow within the aging sensitive domain to quantify circuit aging parameters including negative bias temperature instability and hot carrier injection cumulative damage includes: extracting chip nodes within the aging sensitive domain; decoupling the time-varying excitation flow into voltage stress components and dynamic thermal distribution components; tracking the stress phase and recovery phase in the voltage stress components; calculating the interface state trap density modulated by the dynamic thermal distribution components to obtain the negative bias temperature instability; monitoring the kinetic energy gain of channel carriers under electric field acceleration; calculating the defect accumulation rate in the oxide layer by combining the drain current density integration to obtain the hot carrier injection cumulative damage; and using a multiphysics superposition algorithm to convert the interface state trap density and defect accumulation rate into a damage function that increases with time, which is then quantified into circuit aging parameters through a sensitivity coefficient matrix. The circuit aging parameters are back-mapped to the physical design netlist, and full-chip timing simulation is performed under the boundary conditions of the thermal coupling state to generate timing simulation data. The performance erosion index of the integrated circuit is predicted based on the timing simulation data, and the dynamic redundancy shrinkage vector between the performance erosion index and the circuit lifespan is calculated. The dynamic redundancy shrinkage vector is used in conjunction with the basic process library to adjust the guard band reduction range, and the reliability assessment of the integrated circuit is converged within the target design range.

2. The method for predicting integrated circuit aging effects and assessing circuit lifetime reliability according to claim 1, characterized in that, The specific implementation process of obtaining the physical design netlist and basic process library of integrated circuits and parsing the test load sequence into the transient flip-flop density of chip nodes includes: The physical design netlist of the integrated circuit is obtained, and the capacitance and resistance parameters associated with the chip node locations are extracted. Combined with the cell delay characteristics in the basic process library, a static timing analysis map is constructed. The test load sequence is deconstructed into a discrete time-domain signal vector flow, and the signal vector flow is injected into the static timing analysis map according to the timing constraints to perform step-by-step logic state propagation deduction. The voltage level transition behavior of all chip nodes is monitored, and the rising edge and falling edge switching actions are independently statistically accumulated to form an original switching count matrix characterizing the dynamic behavior of the nodes. The original switching count matrix is ​​normalized according to the circuit operating frequency and clock cycle constraints, and the instantaneous switching density reflecting the node activity level is calculated.

3. The method for predicting integrated circuit aging effects and assessing circuit lifetime reliability according to claim 1, characterized in that, The specific implementation process of mapping the transient flip density to chip layout geometry to generate a time-varying excitation flow containing node power consumption characteristics and thermal field coupling state includes: The transient flip density is combined with the chip layout geometry information to transform it into an instantaneous power sequence that fluctuates over time for each chip node. A three-dimensional thermal resistance-capacitance network is established based on the thermal conductivity and specific heat capacity characteristics of the chip material. The instantaneous power sequence is used as a heat source excitation and mapped to the corresponding thermal analysis grid cell. The heat flow diffusion process is transiently solved within the three-dimensional thermal resistance-capacitance network to calculate the local temperature field evolution curve formed by the superposition of device self-heating effect and mutual heating effect of adjacent regions. The local temperature field evolution curve is time-domain synchronized and data correlated with the original voltage logic signal to integrate it into a time-varying excitation flow.

4. The method for predicting integrated circuit aging effects and assessing circuit lifetime reliability according to claim 1, characterized in that, The specific implementation process of inversely mapping the circuit aging parameters to the physical design netlist, performing full-chip timing simulation under the boundary conditions of the thermal coupling state, and generating timing simulation data includes: Based on the hierarchical topology of the physical design netlist, an index mapping relationship is established between circuit aging parameters and chip nodes. Non-uniform temperature distribution data in the thermal field coupling state is read, and spatially related environmental process corner constraints are constructed and covered to all chip nodes. Under the environmental process corner constraints, a static timing analysis engine is started to perform delay simulation of the circuit path. The changes in the setup time and hold time margin of the circuit path are monitored, and timing violation nodes caused by circuit aging parameters are extracted to generate timing simulation data characterizing circuit performance degradation.

5. The method for predicting integrated circuit aging effects and assessing circuit lifetime reliability according to claim 1, characterized in that, The specific implementation process of predicting the performance erosion index of the integrated circuit based on the timing simulation data and calculating the dynamic redundancy shrinkage vector between the performance erosion index and the circuit lifetime includes: Identify timing violation nodes in the timing simulation data, correlate the delay increment of the corresponding circuit path with the failure rate, and generate a performance erosion index that quantifies the rate of degradation of circuit health. Construct a reliability interval based on the circuit's lifespan, project the performance erosion index onto the reliability interval for probability assessment, and calculate the theoretical failure time under the current process conditions. Convert the theoretical failure time into a compressible space of clock frequency protection band and voltage design margin through sensitivity inversion, and calculate the dynamic redundancy shrinkage vector.

6. The method for predicting integrated circuit aging effects and assessing circuit lifetime reliability according to claim 1, characterized in that, The specific implementation process of converging the reliability assessment of integrated circuits within the target design range by utilizing dynamic redundancy shrinkage vectors and adjusting the guard band reduction magnitude in conjunction with the basic process library includes: A multi-dimensional design space coordinate system is established using a dynamic redundant shrinkage vector and process angle deviation data from the basic process library. The target design interval is mapped to a multi-objective constraint hyperplane within the coordinate system, and the Euclidean distance between the projection coordinates of the current performance erosion index in the coordinate system and the constraint hyperplane is calculated. A gradient descent search strategy is adopted to convert the Euclidean distance into the adjustment step size of the guard band parameters, and the clock cycle guard band and voltage design margin are iteratively shrunk and corrected. In each correction iteration, the circuit yield prediction curve is updated synchronously, and the degree of fit between the yield prediction curve and the confidence boundary of the target design interval is monitored. When the overlapping area of ​​the two satisfies the presignificance test, the evaluation is determined to be converged and the guard band configuration parameters at this time are locked.

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