Circuit aging monitoring device and method based on double-section delay chain and signal overturning detection

Abstract

The invention provides a circuit aging monitoring device and method based on a double-section delay chain and signal upset detection. The circuit aging monitoring device comprises a data upset detection module, a double-section buffer delay chain, a rising edge sampling logic module, a signal comparison module and a falling edge anti-burr judgment output logic module. The data flipping detection module monitors flipping of the input signal and generates an enabling control signal; the double-section buffer delay chain applies two-stage configurable delay to an input signal and outputs signals with different delay degrees; the rising edge sampling logic module is used for sampling and latching each path of signal; the signal comparison module compares the sampling signals and generates a time sequence margin intermediate signal; and the falling edge anti-burr judgment output logic module latches the intermediate signal at the falling edge of the clock and updates the output state only when the enabling is effective.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit reliability design, and more specifically, to a circuit aging monitoring device and method based on a two-segment delay chain and signal flip detection. Background Technology

[0002] As integrated circuit feature sizes continue to shrink and chip performance improves, the industry also faces challenges from aging effects, primarily negative bias temperature instability (NBTI). After prolonged operation, component aging leads to increased threshold voltages and decreased drive currents, resulting in increased gate propagation delays that exceed design timing margins, ultimately causing circuit failure. Traditional conservative designs ensure reliability by reserving large timing margins, but this results in significant power consumption waste and performance degradation. To eliminate redundancy margins, adaptive voltage-frequency regulation (AVFS) technology has emerged, relying on in-situ monitors deployed within the chip to continuously sense the circuit's timing status.

[0003] In-situ monitors are divided into error detection type and timing warning type. Among them, the canary monitor is widely used in low-power chips due to its simple structure and low cost. It introduces shadow registers and delay chains at the end of the critical path to output warning signals before timing violations occur, providing a basis for adjustment of the AVFS system.

[0004] Although canary monitors are widely used, they still have significant shortcomings in practical high-performance SoC dynamic monitoring scenarios. In conventional canary monitors, the warning signal is generated by comparing the original signal and the delayed signal through an XOR gate. Due to the non-ideal characteristics of the device and path mismatch, the arrival times of these two signals at the XOR gate cannot be perfectly synchronized, causing the XOR gate to easily generate transient glitches during the clock high level. Once these glitches are captured, they send erroneous violation warnings to the AVFS controller, causing the system to perform unnecessary voltage and frequency adjustments. In addition, traditional canary monitors have coarse binary logic feedback. In AVFS closed-loop control, due to insufficient feedback information depth, frequent adjustments are made near timing critical points, lacking a stable target operating range. This not only increases the load on the power management unit but also makes it difficult to support more refined graded voltage regulation strategies. Existing in-situ monitors can only complete detection and output a valid state when the signal flips. When the signal is stationary, they output invalid "sufficient margin" information, which may lead to erroneous adjustments by the AVFS controller. At the same time, they continue to update the state when the signal does not change, resulting in redundant power consumption.

[0005] Patent application CN117590838A discloses a method and system for intelligent detection of microprocessor aging. The method includes: acquiring pin signals, a frequency-divided clock signal, and an ideal waveform; acquiring voltage deviation based on the voltage difference of the pin signals; acquiring a first sub-signal; acquiring a delay observation period based on the ideal waveform, and acquiring the significance of the delay phenomenon based on the voltage difference and the length of the delay observation period; acquiring a signal transition interval period, and acquiring the significance of glitches based on the voltage difference and the length of the signal transition interval period; acquiring the significance of the microprocessor aging degree based on this; acquiring a Markov transition probability matrix based on the significance of the microprocessor aging degree, and constructing an aging index disorder; acquiring an aging degree index based on the aging index disorder, thus completing the intelligent detection of microprocessor aging. However, this patent application cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the purpose of this invention is to provide a circuit aging monitoring device and method based on a two-segment delay chain and signal inversion detection.

[0007] The circuit aging monitoring device based on a dual-segment delay chain and signal flip detection provided by the present invention includes a data flip detection module, a dual-segment buffer delay chain, a rising edge sampling logic module, a signal comparison module, and a falling edge anti-glitch determination output logic module.

[0008] The data flip detection module is used to monitor whether the input signal flips within a clock cycle and generate an enable control signal; The dual-segment buffer delay chain is connected to the data flip detection module and the input signal, and is used to apply a configurable delay of two stages in series to the input signal and output at least two delay signals with different delay levels. The input terminal of the rising edge sampling logic module is connected to the input signal and each delay output node of the dual-segment buffer delay chain, respectively, and is used to sample and latch each signal at the rising edge of the clock. The signal comparison module is connected to the output of the rising edge sampling logic module and is used to compare the sampled signals to generate an intermediate comparison signal that represents the timing margin range. The falling edge anti-glitch determination output logic module is connected to the output of the signal comparison module and the enable control signal generated by the data flip detection module. It is used to latch the intermediate comparison signal at the falling edge of the clock and update the output state only when the enable control signal is valid.

[0009] Preferably, the data flip detection module includes a first D flip-flop, a second D flip-flop, and a first XOR gate; The data input terminal of the first D flip-flop receives the input signal, and the clock terminal receives the clock signal; The data input terminal of the second D flip-flop is connected to the output terminal of the first D flip-flop, and the clock terminal receives the clock signal to store the signal value sampled by the first D flip-flop in the previous clock cycle. The two inputs of the first XOR gate are respectively connected to the outputs of the first D flip-flop and the second D flip-flop. Its output outputs the enable control signal. When the output of the first XOR gate is logic 1, it indicates that the input signal has flipped in the previous clock cycle.

[0010] Preferably, the dual-stage buffer delay chain includes a first-stage delay chain and a second-stage delay chain; The input terminal of the first-stage delay chain is connected to the input signal, and its delay amount is used to set a first timing threshold. The input of the second-stage delay chain is connected to the output of the first-stage delay chain, and its delay is used to set the second timing threshold. The first timing threshold corresponds to the timing warning line of the system, and the second timing threshold is used together with the first timing threshold to define the target adjustment range of the adaptive voltage and frequency regulation system.

[0011] Preferably, the rising edge sampling logic module includes a third D flip-flop and a fourth D flip-flop; The data input terminal of the third D flip-flop is connected to the output terminal of the first stage delay chain, and the clock terminal receives the clock signal to sample the signal after the first stage delay. The data input terminal of the fourth D flip-flop is connected to the output terminal of the second-stage delay chain, and the clock terminal receives the clock signal to sample the signal after two stages of delay.

[0012] Preferably, the signal comparison module includes a second XOR gate and a third XOR gate; The two inputs of the second XOR gate are respectively connected to the outputs of the first D flip-flop and the third D flip-flop, and output a first intermediate comparison signal. Its logic state indicates whether the timing margin of the input signal is less than the delay time set by the first-stage delay chain. The two inputs of the third XOR gate are respectively connected to the outputs of the first D flip-flop and the fourth D flip-flop, and output a second intermediate comparison signal. Its logic state indicates whether the timing margin of the input signal is less than the total delay time jointly set by the first-level delay chain and the second-level delay chain.

[0013] Preferably, the falling edge anti-glitch determination output logic module includes a fifth D flip-flop and a sixth D flip-flop; The data input terminal of the fifth D flip-flop is connected to the output terminal of the second XOR gate, the clock terminal receives the inverted signal of the clock signal or adopts the falling edge triggering method, and its enable terminal is connected to the enable control signal output by the data flip detection module. The data input terminal of the sixth D flip-flop is connected to the output terminal of the third XOR gate, the clock terminal receives the inverted signal of the clock signal or adopts the falling edge triggering method, and its enable terminal is connected to the enable control signal output by the data flip detection module. The outputs of the fifth and sixth D flip-flops together constitute the final state output signal of the monitoring device.

[0014] Preferably, the final state output signal is a two-bit code, and its relationship with the first intermediate comparison signal and the second intermediate comparison signal satisfies the following logic: When the signal fails to pass through the first delay, it indicates that the timing margin is lower than the first threshold, and the final output signal is the first code. When the signal passes through the first delay but not the second delay, it indicates that the timing margin is between the first threshold and the second threshold, and the final output signal is the second code. When the signal passes through two delays, it indicates that the timing margin is greater than the second threshold, and the final output signal is the third code.

[0015] Preferably, the first code is 11, the second code is 01, and the third code is 00.

[0016] Preferably, the specific state of the final state output signal is directly defined by the output level of the fifth and sixth D flip-flops, and corresponds to the output results of the second and third XOR gates before latching on the falling edge.

[0017] The circuit aging monitoring method based on a two-segment delay chain and signal inversion detection provided by the present invention includes: Step 1: Use the data flip detection module to determine whether the input signal has flipped relative to the previous cycle in the current clock cycle, and generate a state update enable signal accordingly; Step 2: Delay the input signal via a first-stage delay chain and a second-stage delay chain in series to generate delayed signals with different delay amounts; Step 3: Sample and latch the original input signal and each delayed signal at the rising edge of the clock; Step 4: Perform an XOR comparison between the sampled original input signal and each delayed sampled signal to generate an intermediate result reflecting the timing margin range; Step 5: At the falling edge of the clock, latch the intermediate result according to the state update enable signal, and output a stable, glitch-free timing margin state code.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) In view of the problems of transient glitches and false alarms, voltage regulation oscillation caused by binary logic and invalid output state when the signal is stationary, the present invention designs a dual threshold aging monitoring device with jump detection and glitch elimination function, which realizes efficient glitch filtering, time margin hierarchical characterization, continuous effective output state and low power consumption operation, provides stable and accurate feedback signal for AVFS system, and supports fine voltage frequency adjustment; (2) The present invention adopts a fully digital circuit design scheme. The overall circuit is composed of standard digital units and has no analog circuit modules. It is fully compatible with the existing integrated circuit design process and can be easily integrated into various high-performance SoC chips. (3) The circuit structure is simple and there is no complex timing logic. It can be developed and verified on a common chip design platform. No special power supply or external auxiliary circuit is required during operation. It has low power consumption and strong stability. (4) This design can accurately realize timing margin hierarchical monitoring and stable feedback, effectively support the fine voltage and frequency adjustment of AVFS system, significantly improve the reliability and power management efficiency of integrated circuits, and is of great significance for extending chip life and reducing energy consumption. It is suitable for aging monitoring scenarios of various integrated circuits such as low-power IoT chips and high-performance server CPUs. Attached Figure Description

[0019] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a circuit structure diagram; Figure 2 This is a timing waveform diagram of an aging monitor. Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0021] Example 1 This invention provides a circuit aging monitoring device based on a dual-segment delay chain and signal flip detection, including a data flip detection module, a dual-segment buffer delay chain, a rising edge sampling logic module, a signal comparison module, and a falling edge anti-glitch determination output logic module. The data flip detection module is used to monitor whether the input signal flips within a clock cycle and generate an enable control signal; The dual-segment buffer delay chain is connected to the data flip detection module and the input signal, and is used to apply a configurable delay of two stages in series to the input signal and output at least two delay signals with different delay levels. The input terminal of the rising edge sampling logic module is connected to the input signal and each delay output node of the dual-segment buffer delay chain, respectively, and is used to sample and latch each signal at the rising edge of the clock. The signal comparison module is connected to the output of the rising edge sampling logic module and is used to compare the sampled signals to generate an intermediate comparison signal that represents the timing margin range. The falling edge anti-glitch determination output logic module is connected to the output of the signal comparison module and the enable control signal generated by the data flip detection module. It is used to latch the intermediate comparison signal at the falling edge of the clock and update the output state only when the enable control signal is valid.

[0022] The data flip detection module includes a first D flip-flop, a second D flip-flop, and a first XOR gate; The data input terminal of the first D flip-flop receives the input signal, and the clock terminal receives the clock signal; The data input terminal of the second D flip-flop is connected to the output terminal of the first D flip-flop, and the clock terminal receives the clock signal to store the signal value sampled by the first D flip-flop in the previous clock cycle. The two inputs of the first XOR gate are respectively connected to the outputs of the first D flip-flop and the second D flip-flop. Its output outputs the enable control signal. When the output of the first XOR gate is logic 1, it indicates that the input signal has flipped in the previous clock cycle.

[0023] The dual-segment buffer delay chain includes a first-level delay chain and a second-level delay chain; The input terminal of the first-stage delay chain is connected to the input signal, and its delay amount is used to set a first timing threshold. The input of the second-stage delay chain is connected to the output of the first-stage delay chain, and its delay is used to set the second timing threshold. The first timing threshold corresponds to the timing warning line of the system, and the second timing threshold is used together with the first timing threshold to define the target adjustment range of the adaptive voltage and frequency regulation system.

[0024] The rising edge sampling logic module includes a third D flip-flop and a fourth D flip-flop; The data input terminal of the third D flip-flop is connected to the output terminal of the first stage delay chain, and the clock terminal receives the clock signal to sample the signal after the first stage delay. The data input terminal of the fourth D flip-flop is connected to the output terminal of the second-stage delay chain, and the clock terminal receives the clock signal to sample the signal after two stages of delay.

[0025] The signal comparison module includes a second XOR gate and a third XOR gate; The two inputs of the second XOR gate are respectively connected to the outputs of the first D flip-flop and the third D flip-flop, and output a first intermediate comparison signal. Its logic state indicates whether the timing margin of the input signal is less than the delay time set by the first-stage delay chain. The two inputs of the third XOR gate are respectively connected to the outputs of the first D flip-flop and the fourth D flip-flop, and output a second intermediate comparison signal. Its logic state indicates whether the timing margin of the input signal is less than the total delay time jointly set by the first-level delay chain and the second-level delay chain.

[0026] The falling edge anti-glitch determination output logic module includes a fifth D flip-flop and a sixth D flip-flop; The data input terminal of the fifth D flip-flop is connected to the output terminal of the second XOR gate, the clock terminal receives the inverted signal of the clock signal or adopts the falling edge triggering method, and its enable terminal is connected to the enable control signal output by the data flip detection module. The data input terminal of the sixth D flip-flop is connected to the output terminal of the third XOR gate, the clock terminal receives the inverted signal of the clock signal or adopts the falling edge triggering method, and its enable terminal is connected to the enable control signal output by the data flip detection module. The outputs of the fifth and sixth D flip-flops together constitute the final state output signal of the monitoring device.

[0027] The final state output signal is a two-bit code, and its relationship with the first intermediate comparison signal and the second intermediate comparison signal satisfies the following logic: When the signal fails to pass through the first delay, it indicates that the timing margin is lower than the first threshold, and the final output signal is the first code. When the signal passes through the first delay but not the second delay, it indicates that the timing margin is between the first threshold and the second threshold, and the final output signal is the second code. When the signal passes through two delays, it indicates that the timing margin is greater than the second threshold, and the final output signal is the third code.

[0028] The first code is 11, the second code is 01, and the third code is 00.

[0029] The specific state of the final state output signal is directly defined by the output level of the fifth and sixth D flip-flops, and corresponds to the output results of the second and third XOR gates before latching on the falling edge.

[0030] This invention also provides a circuit aging monitoring method based on a two-segment delay chain and signal inversion detection, comprising: Step 1: Use the data flip detection module to determine whether the input signal has flipped relative to the previous cycle in the current clock cycle, and generate a state update enable signal accordingly; Step 2: Delay the input signal via a first-stage delay chain and a second-stage delay chain in series to generate delayed signals with different delay amounts; Step 3: Sample and latch the original input signal and each delayed signal at the rising edge of the clock; Step 4: Perform an XOR comparison between the sampled original input signal and each delayed sampled signal to generate an intermediate result reflecting the timing margin range; Step 5: At the falling edge of the clock, latch the intermediate result according to the state update enable signal, and output a stable, glitch-free timing margin state code.

[0031] Example 2 Example 2 is a preferred example of Example 1.

[0032] The circuit structure proposed in this invention is as follows: Figure 1 As shown, its overall framework mainly consists of a data flip detection module, a dual-segment buffer delay chain, rising edge sampling logic, and falling edge anti-glitch judgment output logic. In the figure, Enable refers to the enable control signal, and status refers to the final status output signal.

[0033] DFF1, DFF2, and XOR1 constitute a toggle detection module to monitor whether the signal toggles within a clock cycle. DFF1 samples the original signal value, while DFF3 and DFF4 sample the original signal values ​​after the first-stage delay and the second-stage delay, respectively. The Q-output signals of DFF1 and DFF3, and the Q-output signals of DFF1 and DFF4, are compared by XOR2 and XOR3, respectively, and then output as XOR2_OUT and XOR3_OUT, representing the margin range. If XOR2_OUT is 1, it indicates that the signal margin is less than the time set by the first-stage delay chain; if XOR3_OUT is 1, it indicates that the signal margin is less than the time set by the second-stage delay chain. The two D flip-flops controlled by the XOR1 output signal ACT_EN are status update registers (the two D flip-flops at the bottom of the circuit diagram). These two D flip-flops sample the output signals of XOR2_OUT and XOR3_OUT, and use falling edge sampling to avoid glitches caused by combinational logic.

[0034] The specific technical solution is as follows: 1) A drawback of the unified in-situ monitoring system is that detection and output of a valid state can only be performed when the signal flips. This leads to two possibilities for the output "sufficient margin" information: ① There is sufficient remaining timing margin, allowing for voltage / frequency adjustment; ② The signal has not flipped, the circuit aging monitoring sensor has not completed detection, and the margin state is unknown. To ensure that the sensor output is always valid and to avoid incorrect adjustment of the AVFS controller due to an invalid "sufficient margin" state output when the signal is stationary, this invention proposes a data flip detection structure composed of DFF1, DFF2, and XOR1. DFF2 stores the data sampled by D flip-flop DFF1 in the previous cycle. This stored value is XORed with the signal value sampled by DFF1 at the current clock edge. If the XOR output is 1, it indicates that the signal flipped in the previous cycle. If the signal flips, the detection signal ACT_EN outputs 1. This signal controls the enable terminal of the state sampling flip-flop. The sensor state is updated only when the ACT_EN output is 1; otherwise, the previous state is maintained, thus ensuring that the sensor output state is always valid and reliable. Meanwhile, the self-enabling based on data flip detection can reduce the redundant power consumption of the monitoring path when it still performs invalid state updates when the signal does not change.

[0035] 2) This monitoring device contains two-stage delay chains in series, mainly composed of delay units made up of buffers. The first-stage delay chain, Delay line 1, is used to set the critical failure threshold. The threshold is defined as the margin being lower than this value, and the system is prone to timing errors. Its delay amount corresponds to the timing warning line of the system. The second-stage delay chain, Delay line 2, is used to set the target adjustment range of the system, that is, the margin does not need to be adjusted in the voltage range, which is the ideal range. Thus, the adjustment "dead zone" required by the AVFS system is constructed between the two delay nodes. The dual delay chain setting can also further classify the margin. The traditional in-situ monitor only outputs two states, "0" and "1", which is too coarse in representing the margin. It can only know whether the margin is greater than the set threshold. The dual threshold delay chain added in this invention further subdivides the range of the margin. According to the XOR judgment result, Zone_Status outputs three states: Panic (11): The signal did not pass through the first delay, indicating that the margin is extremely low, less than the threshold 1, and the voltage needs to be boosted or the frequency reduced immediately. Target(01): The signal passes through the first segment but not the second segment, indicating that it is within the preset "dead zone" range. The margin is between threshold 1 and threshold 2, and the AVFS system maintains its current state. Waste(00): The signal passes through both delay segments smoothly, indicating that the margin is too large and the system has room for voltage reduction and energy saving.

[0036] 3) Traditional canary monitors directly output the XOR comparison result. However, due to the non-ideal characteristics of the devices, the signals through the endpoint register and the shadow register may not arrive at the XOR gate simultaneously, resulting in glitches. If these glitches are detected by the subsequent AVFS controller, they can lead to incorrect voltage and frequency adjustments. Therefore, this invention adds a falling-edge triggered D flip-flop after the XOR operation, latching the XOR result at the falling edge of each cycle. This mechanism utilizes a half-cycle time window to effectively isolate and filter transient glitches generated during the high-level period of the XOR logic, ensuring the stability of the output Zone_Status code.

[0037] Figure 2 The timing waveform diagram shows the aging monitor. In the diagram, "glitch" refers to the transient spikes generated at the output of the XOR gate. According to the timing diagram, Zone_Status [1:0] is updated only when ACT_EN is 1; otherwise, it remains unchanged. Also, because the two input signals of the XOR gate do not necessarily arrive at the XOR gate synchronously, spikes will occur at the XOR gate output. Therefore, sampling on the falling edge of the status update register avoids combinational logic spikes. Depending on the signal arrival time, i.e., the remaining margin, the sensor outputs different status signals: 11, 01, 00 represent the margin range.

[0038] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0039] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A circuit aging monitoring device based on a two-segment delay chain and signal inversion detection, characterized in that, It includes a data flip detection module, a dual-segment buffer delay chain, a rising edge sampling logic module, a signal comparison module, and a falling edge anti-glitch judgment output logic module; The data flip detection module is used to monitor whether the input signal flips within a clock cycle and generate an enable control signal; The dual-segment buffer delay chain is connected to the data flip detection module and the input signal, and is used to apply a configurable delay of two stages in series to the input signal and output at least two delay signals with different delay levels. The input terminal of the rising edge sampling logic module is connected to the input signal and each delay output node of the dual-segment buffer delay chain, respectively, and is used to sample and latch each signal at the rising edge of the clock. The signal comparison module is connected to the output of the rising edge sampling logic module and is used to compare the sampled signals to generate an intermediate comparison signal that represents the timing margin range. The falling edge anti-glitch determination output logic module is connected to the output of the signal comparison module and the enable control signal generated by the data flip detection module. It is used to latch the intermediate comparison signal at the falling edge of the clock and update the output state only when the enable control signal is valid.

2. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 1, characterized in that, The data flip detection module includes a first D flip-flop, a second D flip-flop, and a first XOR gate; The data input terminal of the first D flip-flop receives the input signal, and the clock terminal receives the clock signal; The data input terminal of the second D flip-flop is connected to the output terminal of the first D flip-flop, and the clock terminal receives the clock signal to store the signal value sampled by the first D flip-flop in the previous clock cycle. The two inputs of the first XOR gate are respectively connected to the outputs of the first D flip-flop and the second D flip-flop. Its output outputs the enable control signal. When the output of the first XOR gate is logic 1, it indicates that the input signal has flipped in the previous clock cycle.

3. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 2, characterized in that, The dual-segment buffer delay chain includes a first-level delay chain and a second-level delay chain; The input terminal of the first-stage delay chain is connected to the input signal, and its delay amount is used to set a first timing threshold. The input of the second-stage delay chain is connected to the output of the first-stage delay chain, and its delay is used to set the second timing threshold. The first timing threshold corresponds to the timing warning line of the system, and the second timing threshold is used together with the first timing threshold to define the target adjustment range of the adaptive voltage and frequency regulation system.

4. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 3, characterized in that, The rising edge sampling logic module includes a third D flip-flop and a fourth D flip-flop; The data input terminal of the third D flip-flop is connected to the output terminal of the first stage delay chain, and the clock terminal receives the clock signal to sample the signal after the first stage delay. The data input terminal of the fourth D flip-flop is connected to the output terminal of the second-stage delay chain, and the clock terminal receives the clock signal to sample the signal after two stages of delay.

5. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 4, characterized in that, The signal comparison module includes a second XOR gate and a third XOR gate; The two inputs of the second XOR gate are respectively connected to the outputs of the first D flip-flop and the third D flip-flop, and output a first intermediate comparison signal. Its logic state indicates whether the timing margin of the input signal is less than the delay time set by the first-stage delay chain. The two inputs of the third XOR gate are respectively connected to the outputs of the first D flip-flop and the fourth D flip-flop, and output a second intermediate comparison signal. Its logic state indicates whether the timing margin of the input signal is less than the total delay time jointly set by the first-level delay chain and the second-level delay chain.

6. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 5, characterized in that, The falling edge anti-glitch determination output logic module includes a fifth D flip-flop and a sixth D flip-flop; The data input terminal of the fifth D flip-flop is connected to the output terminal of the second XOR gate, the clock terminal receives the inverted signal of the clock signal or adopts the falling edge triggering method, and its enable terminal is connected to the enable control signal output by the data flip detection module. The data input terminal of the sixth D flip-flop is connected to the output terminal of the third XOR gate, the clock terminal receives the inverted signal of the clock signal or adopts the falling edge triggering method, and its enable terminal is connected to the enable control signal output by the data flip detection module. The outputs of the fifth and sixth D flip-flops together constitute the final state output signal of the monitoring device.

7. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 6, characterized in that, The final state output signal is a two-bit code, and its relationship with the first intermediate comparison signal and the second intermediate comparison signal satisfies the following logic: When the signal fails to pass through the first delay, it indicates that the timing margin is lower than the first threshold, and the final output signal is the first code. When the signal passes through the first delay but not the second delay, it indicates that the timing margin is between the first threshold and the second threshold, and the final output signal is the second code. When the signal passes through two delays, it indicates that the timing margin is greater than the second threshold, and the final output signal is the third code.

8. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 7, characterized in that, The first code is 11, the second code is 01, and the third code is 00.

9. The circuit aging monitoring device based on a dual-segment delay chain and signal inversion detection according to claim 7, characterized in that, The specific state of the final state output signal is directly defined by the output level of the fifth and sixth D flip-flops, and corresponds to the output results of the second and third XOR gates before latching on the falling edge.

10. A circuit aging monitoring method based on a two-segment delay chain and signal inversion detection, applied to the circuit aging monitoring device based on a two-segment delay chain and signal inversion detection as described in any one of claims 1 to 9, characterized in that, The method includes: Step 1: Use the data flip detection module to determine whether the input signal has flipped relative to the previous cycle in the current clock cycle, and generate a state update enable signal accordingly; Step 2: Delay the input signal via a first-stage delay chain and a second-stage delay chain in series to generate delayed signals with different delay amounts; Step 3: Sample and latch the original input signal and each delayed signal at the rising edge of the clock; Step 4: Perform an XOR comparison between the sampled original input signal and each delayed sampled signal to generate an intermediate result reflecting the timing margin range; Step 5: At the falling edge of the clock, latch the intermediate result according to the state update enable signal, and output a stable, glitch-free timing margin state code.

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