Preparation method of GaN HEMT (High Electron Mobility Transistor) with air dielectric layer and composite passivation layer structure
By introducing an air dielectric layer on both sides of the gate of the GaN HEMT device, the problem of large parasitic capacitance is solved, and the RF performance and output power of the device are improved.
Patent Information
- Application Number
- CN202610103097.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-26
- Publication Date
- 2026-04-28
AI Technical Summary
In existing GaN HEMT devices, the parasitic capacitance between the source-gate and drain-gate is relatively large, which affects high-frequency performance and output power. Traditional composite passivation layer structures have failed to effectively reduce the dielectric constant.
An air dielectric layer is introduced between the composite passivation layers on both sides of the gate. An air dielectric layer is formed between the gate metal and the source and drain electrodes by means of a fabrication method, thereby reducing the equivalent dielectric constant.
This effectively reduces the parasitic capacitance of the device, thereby improving its RF performance and output power.
Smart Images
Figure CN121941071A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for preparing a GaN HEMT with a composite passivation layer structure having an air dielectric layer. Background Technology
[0002] In gallium nitride high electron mobility transistors (GaN HEMTs), the dielectric properties of the surface passivation layer have a crucial impact on the device's high-frequency performance. Currently widely used dielectric materials, such as silicon nitride or aluminum oxide, often have high dielectric constants. While this is beneficial for suppressing surface states and improving breakdown voltage, it also makes it difficult to significantly reduce parasitic capacitances between the source-gate and drain-gate. Even with optimization through composite passivation layer structures, the overall equivalent dielectric constant remains high, and the parasitic capacitance problem remains unresolved.
[0003] During high-frequency switching and signal amplification, large parasitic capacitances cause repeated accumulation and release of charge between electrodes, resulting in a non-ideal capacitive coupling effect. This phenomenon not only slows down signal transmission speed but also reduces the output power of the device, thus limiting its performance in radio frequency and high-efficiency power applications. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating a GaN HEMT with a composite passivation layer structure having an air dielectric layer, which can effectively reduce the equivalent dielectric constant between the gate electrode and the source electrode, and between the gate electrode and the drain electrode, thereby reducing the parasitic capacitance of the device.
[0005] The technical solution of this invention: A method for preparing a GaN HEMT with a composite passivation layer structure having an air dielectric layer is as follows: Step 1: Clean the epitaxial wafer and define the ohmic contact areas of the source and drain electrodes; then perform metal evaporation, metal separation, and annealing on the epitaxial wafer to prepare the source and drain electrodes; Step 2: Deposit the first passivation layer on the epitaxial wafer on which the source and drain electrodes are fabricated and perform device isolation; Step 3: Etch two lower-layer cavities on the first passivation layer after device isolation; Step 4: Fabricate two columnar photoresists on the two lower cavities; Step 5: Deposit a second passivation layer on the first passivation layer of the two prepared columnar photoresists; Step 6: Etch the gate electrode contact area on the second passivation layer between the two columnar photoresists. After etching, remove the two columnar photoresists to form an air dielectric layer. Step 7: After removing the two columnar photoresists, deposit the gate metal; Step 8: Remove all metals except the gate metal and all photoresist.
[0006] Further, step 1 is further specifically defined as follows: cleaning the epitaxial wafer, coating the epitaxial wafer with a first photoresist after cleaning, and defining the ohmic contact areas of the source electrode and the drain electrode after exposure and development. Then, the first metal is deposited on the epitaxial wafer. After the metal evaporation is completed, metal removal is performed to remove the first photoresist and the first metal outside the ohmic contact area of the source electrode and drain electrode. After the metal removal is completed, annealing is performed at a temperature of 860-900℃.
[0007] Furthermore, step 2 is further specifically defined as: depositing a first passivation layer on the epitaxial wafer on which the source electrode and drain electrode are fabricated; and isolating different devices after the deposition of the first passivation layer is completed. Mesa isolation of devices can be achieved through dry etching; or, ion implantation can be used to disrupt the conductive channels between different devices, thereby creating insulation between devices on the same epitaxial structure.
[0008] Further, step 3 is further specified as follows: a second photoresist is coated on the isolated first passivation layer, and after exposure and development, the position to be etched is defined; then the position to be etched is etched by dry etching, and after the etching process is completed, the morphology of the etched position is checked and the second photoresist is removed, thereby defining the positions of the two lower cavities of the first passivation layer.
[0009] Furthermore, step 4 is further specified as follows: after completing the etching of the first passivation layer, a third photoresist is coated; after exposure and development, only the third photoresist at the two lower cavity positions is retained, thus completing the preparation of the two columnar photoresists.
[0010] Further, step 6 is further specified as follows: a fourth photoresist is coated on the second passivation layer having two columnar photoresists. After exposure and development, the position to be etched, i.e., the area between the two columnar photoresists, is defined. Then, the position to be etched is etched by dry etching. After the etching process is completed, the morphology of the etched position is checked and the fourth photoresist is removed. The etched position is the contact area between the gate metal and the epitaxial wafer. At the same time as the fourth photoresist is removed, the two columnar photoresists are removed simultaneously. An air dielectric layer is formed between the first passivation layer and the second passivation layer.
[0011] Further, step 7 is further specified as follows: after removing the two columnar photoresists, a fifth photoresist is applied, and then exposure and development are performed on both sides of the contact area to define the gate metal deposition area; then, a second metal is deposited by an evaporation coating process, and the second metal located in the gate metal deposition area is the gate metal.
[0012] The beneficial effects of this invention are: This invention introduces an air dielectric layer between the composite passivation layers on both sides of the gate. Because air dielectric has a very low dielectric constant, it effectively reduces the parasitic capacitance between the gate and source electrodes, and between the gate and drain electrodes, thereby improving the device's radio frequency performance. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of an epitaxial wafer; Figure 2 This is a schematic diagram of the source electrode and the drain electrode; Figure 3 This is a schematic diagram of the first passivation layer; Figure 4 This is a schematic diagram of the lower cavity; Figure 5 This is a schematic diagram of a columnar photoresist; Figure 6 This is a schematic diagram of the contact area; Figure 7 This is a schematic diagram of the fifth photoresist; Figure 8 This is a schematic diagram of the gate metal.
[0014] In the figure: epitaxial wafer 1, source electrode 2, drain electrode 3, first passivation layer 4, lower cavity 5, columnar photoresist 6, second passivation layer 7, contact area 8, air dielectric layer 9, gate metal 10, fifth photoresist 11, second metal 12. Detailed Implementation
[0015] The invention will now be further described with reference to the accompanying drawings.
[0016] Please see Figures 1-8 This invention provides a method for preparing a GaN HEMT with a composite passivation layer structure having an air dielectric layer, the method being as follows: Step 1: Clean the epitaxial wafer 1 and define the ohmic contact areas of the source electrode 2 and the drain electrode 3; then perform metal evaporation, metal separation, and annealing on the epitaxial wafer 1 to prepare the source electrode 2 and the drain electrode 3. Step 2: Deposit the first passivation layer 4 on the epitaxial wafer 1 on which the source electrode 2 and drain electrode 3 are fabricated and then isolate them; Step 3: Etch two lower cavities 5 on the first passivation layer 4 after isolation; Step 4: Fabricate two columnar photoresists 6 on the two lower cavities 5; Step 5: Deposit a second passivation layer 7 on the first passivation layer 4 of the two prepared columnar photoresists 6; Step 6: Etch the gate electrode contact area 8 on the first passivation layer 4 and the second passivation layer 7 between the two columnar photoresists 6. After etching, remove the two columnar photoresists 6 to form an air dielectric layer 9. Step 7: After removing the two columnar photoresists 6, deposit the gate metal 10; Step 8: Remove all metals except gate metal 10 and all photoresist.
[0017] Step 1 is further specified as follows: cleaning the epitaxial wafer 1, coating the epitaxial wafer 1 with a first photoresist after cleaning, and defining the ohmic contact area of the source electrode 2 and the drain electrode 3 after exposure and development. Then, a first metal is deposited on the epitaxial wafer 1. After the metal evaporation is completed, metal removal is performed to remove the first photoresist and the first metal outside the ohmic contact area of the source electrode 2 and the drain electrode 3. After the metal removal is completed, annealing is performed at a temperature of 860-900℃.
[0018] Step 2 is further specified as follows: depositing a first passivation layer 4 on the epitaxial wafer 1 on which the source electrode 2 and the drain electrode 3 are fabricated; after the deposition of the first passivation layer 4 is completed, isolation is performed between different devices; Mesa isolation of devices can be achieved through dry etching; or, ion implantation can be used to disrupt the conductive channels between different devices, thereby creating insulation between devices on the same epitaxial structure.
[0019] Step 3 is further specified as follows: a second photoresist is coated on the isolated first passivation layer 4, and after exposure and development, the position to be etched is defined; then the position to be etched is etched by dry etching, and after the etching process is completed, the morphology of the etched position is checked and the second photoresist is removed, thereby defining the positions of the two lower cavities 5 of the first passivation layer 4.
[0020] Step 4 is further specified as follows: after etching the first passivation layer 4, the third photoresist is coated; after exposure and development, only the third photoresist at the positions of the two lower cavity 5 is retained, thus completing the preparation of the two columnar photoresists 6.
[0021] Step 6 is further specified as follows: a fourth photoresist is coated on the second passivation layer 7 having two columnar photoresists 6. After exposure and development, the position to be etched, i.e., the area between the two columnar photoresists 6, is defined. Then, the position to be etched is etched by dry etching. After the etching process is completed, the morphology of the etched position is checked and the fourth photoresist is removed. The etched position is the contact area 8 between the gate metal 10 and the epitaxial wafer 1. At the same time as the fourth photoresist is removed, the two columnar photoresists 6 are removed simultaneously. An air dielectric layer 9 is formed between the first passivation layer 4 and the second passivation layer 7.
[0022] Step 7 is further specified as follows: after removing the two columnar photoresists 6, a fifth photoresist 11 is coated, and then exposure and development are performed on both sides of the contact area 8 to define the gate metal deposition area; then the second metal 12 is deposited by evaporation coating process, and the second metal 12 located in the gate metal deposition area is the gate metal 10.
[0023] The present invention will be further described below with reference to a specific embodiment: Taking a depletion-mode gallium nitride high-mobility transistor device as an example, the implementation scheme of this patent is specifically described. The epitaxial wafer includes a substrate and an epitaxial layer. The substrate can be made of materials such as silicon, silicon carbide, sapphire, diamond, or gallium nitride. The epitaxial layer consists of a buffer layer, a channel layer, and a barrier layer grown on the substrate from bottom to top. Its structure is as follows: Figure 1 As shown.
[0024] The differences in device structure between existing and improved technologies are reflected in the following: the passivation layer structures between the source and gate electrodes, and between the drain and gate electrodes, differ. This results in differences in the passivation layer structures between the gate metal and the source and drain electrodes. The improved technology introduces an air dielectric layer between the traditional compound passivation layers.
[0025] A method for preparing a GaN HEMT with a composite passivation layer structure having an air dielectric layer is as follows: (1) Source and drain electrode fabrication: The epitaxial wafer is cleaned, and then photoresist is coated, exposed, and developed to define the ohmic contact areas of the source and drain electrodes. Metal is deposited on the gallium nitride epitaxial wafer using an evaporation deposition process. The metal structure can be a Ti / Al / Ni / Au structure stacked from bottom to top. After the metal evaporation is completed, metal removal is required to remove the photoresist and metal from the non-ohmic contact areas. After the metal removal is completed, annealing is required, and the annealing temperature can be selected from 860-900℃. Figure 2 A schematic diagram of the device structure after the source and drain electrodes are fabricated.
[0026] (2) First passivation layer deposition & device isolation: After the source and drain electrode metals are fabricated, a passivation layer needs to be deposited on the device surface to passivate surface defects of the epitaxial wafer. Simultaneously, the passivation layer also protects the device surface from water and oxygen corrosion. Here, we first deposit the first passivation layer. The passivation layer can be made of materials such as SiN, AlN, or SiO2, and high-quality passivation layers can be deposited using processes such as LPCVD, PECVD, and ALD. After the passivation layer is deposited, isolation between different devices is required. Dry etching can be used for mesa isolation, or ion implantation can be used to disrupt the conductive channels between different devices, thereby creating insulation between devices on the same epitaxial structure. Figure 3 A schematic diagram of the device structure after the passivation layer deposition is completed.
[0027] (3) Etching of the first passivation layer: After the passivation layer has been deposited and isolated from the device, photoresist is coated, exposed, and developed to define the position of the lower half of the cavity of the first passivation layer. Dry etching technology can be used for this etching process. CF4, CHF3, etc. can be used as the reactive gas. After the etching process is completed, the morphology of the etched position is checked and the photoresist is removed. Figure 4 A schematic diagram of the device structure after etching the lower layer of the passivation layer cavity.
[0028] (4) Preparation of sacrificial photoresist in the air dielectric layer: Photoresist is coated, exposed, and developed on the wafer after etching the lower layer of the passivation layer cavity. Two discrete columnar photoresists are prepared above the etched passivation layers on both sides of the gate mesa. Their thickness should be significantly higher than the height of the unetched part of the first passivation layer. Note that sufficient hardening of the photoresist must be ensured here. Figure 5 A schematic diagram of the device structure after the passivation layer cavity sacrificial photoresist has been fabricated.
[0029] (5) Deposition of the second passivation layer: A second passivation layer is deposited on the wafer after the previous step. Similarly, the passivation layer can be made of materials such as SiN, AlN, or SiO2, and the passivation layer can be prepared using methods such as LPCVD, PECVD, or ALD. Figure 6 A schematic diagram of the device structure after the second passivation layer has been deposited.
[0030] (6) Gate electrode contact window etching & sacrificial photoresist removal: Photoresist is coated, exposed, and developed on the wafer after the second passivation layer deposition to define the contact area between the gate electrode and the AlGaN barrier. Dry etching technology can be used for this etching process. CF4, CHF3, etc., can be used as the reactive gas. After the etching process is completed, the morphology of the etched location is inspected and the photoresist is removed. Simultaneously, the sacrificial photoresist is also removed. Figure 7 A schematic diagram of the device structure after etching the gate electrode contact window.
[0031] (7) Gate electrode fabrication: Photoresist is coated, exposed, and developed on the wafer after the previous step to define the gate metal region. Then, the gate metal is deposited on the gallium nitride epitaxial wafer using an evaporation deposition process. The metal structure can be a Ti / Pt / Au or Ni / Au structure stacked from bottom to top. Figure 8 A schematic diagram of the device structure after the gate electrode fabrication is completed.
[0032] (8) Metal removal: A metal removal process is used to remove metal outside the photoresist and gate regions. The photoresist and non-gate region metal are then checked to ensure they have been completely removed. The device fabrication is now complete.
[0033] Definitions of abbreviations and key terms: 1. GaN HEMT: Gallium Nitride High Electron Mobility Transistor 2. SiN: Silicon Nitride 3. SiO2: Silicon dioxide 4. AlN: Aluminum nitride 5. AlGaN Barrier: AlGaN barrier layer; 6. Buffer layer: a layer that provides buffering. 7. Gate cap: The cap region on the upper layer of the gate; 8. PECVD: Plasma-enhanced chemical vapor deposition; 9. ALD: Atomic Layer Deposition Technology; 10. LPCVD: Low-Pressure Chemical Vapor Deposition; 11. GaN Channel: refers to the GaN channel layer in an AlGaN / GaN heterojunction; 12. Substrate: refers to the substrate, which can be made of materials such as silicon substrate, silicon carbide substrate, gallium nitride substrate, sapphire substrate, and diamond substrate.
[0034] The above description is only a preferred embodiment of the present invention and should not be construed as a limitation of this application. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should be covered by the present invention.
Claims
1. A method for preparing a GaN HEMT with a composite passivation layer structure having an air dielectric layer, characterized in that, The method is as follows: Step 1: Clean the epitaxial wafer and define the ohmic contact areas of the source and drain electrodes; then perform metal evaporation, metal separation, and annealing on the epitaxial wafer to prepare the source and drain electrodes; Step 2: Deposit the first passivation layer on the epitaxial wafer on which the source and drain electrodes are fabricated and then isolate them; Step 3: Etch two lower-layer cavities on the first passivation layer after isolation; Step 4: Fabricate two columnar photoresists on the two lower cavities; Step 5: Deposit a second passivation layer on the first passivation layer of the two prepared columnar photoresists; Step 6: Etch the gate electrode contact area on the second passivation layer between the two columnar photoresists. After etching, remove the two columnar photoresists to form an air dielectric layer. Step 7: After removing the two columnar photoresists, deposit the gate metal; Step 8: Remove all metals except the gate metal and all photoresist.
2. The method for preparing a GaN HEMT with an air dielectric layer according to claim 1, characterized in that, Step 1 is further specified as follows: cleaning the epitaxial wafer, coating the epitaxial wafer with a first photoresist after cleaning, and defining the ohmic contact areas of the source electrode and the drain electrode after exposure and development. Then, the first metal is deposited on the epitaxial wafer. After the metal evaporation is completed, metal removal is performed to remove the first photoresist and the first metal outside the ohmic contact area of the source electrode and drain electrode. After the metal removal is completed, annealing is performed at a temperature of 860-900℃.
3. The method for preparing a GaN HEMT with an air dielectric layer according to claim 1, characterized in that, Step 2 is further specified as follows: depositing a first passivation layer on the epitaxial wafer on which the source electrode and drain electrode are fabricated; after the deposition of the first passivation layer is completed, isolation is performed between different devices; Mesa isolation of the device is achieved through dry etching; Alternatively, ion implantation can be used to disrupt the conductive channels between different devices, thereby creating insulation between devices on the same epitaxial structure.
4. The method for preparing a GaN HEMT with an air dielectric layer according to claim 1, characterized in that, Step 3 is further specified as follows: a second photoresist is coated on the isolated first passivation layer, and after exposure and development, the position to be etched is defined; then the position to be etched is etched by dry etching, and after the etching process is completed, the morphology of the etched position is checked and the second photoresist is removed, thereby defining the positions of the two lower cavities of the first passivation layer.
5. The method for preparing a GaN HEMT with an air dielectric layer according to claim 1, characterized in that, Step 4 is further specified as follows: after the first passivation layer is etched, the third photoresist is coated; after exposure and development, only the third photoresist at the two lower cavity positions is retained, thus completing the preparation of the two columnar photoresists.
6. The method for preparing a GaN HEMT with an air dielectric layer according to claim 1, characterized in that, Step 6 is further specified as follows: a fourth photoresist is coated on the second passivation layer with two columnar photoresists, and after exposure and development, the position to be etched is defined, namely the area between the two columnar photoresists. Then, the area to be etched is etched by dry etching. After the etching process is completed, the morphology of the etched area is checked and the fourth photoresist is removed. The etched area is the contact area between the gate metal and the epitaxial wafer. At the same time as the fourth photoresist is removed, the two columnar photoresists are removed simultaneously. An air dielectric layer is formed between the first passivation layer and the second passivation layer.
7. The method for preparing a GaN HEMT with an air dielectric layer according to claim 1, characterized in that, Step 7 is further specified as follows: after removing the two columnar photoresists, a fifth photoresist is applied, and then exposure and development are performed on both sides of the contact area to define the gate metal deposition area; then, a second metal is deposited by an evaporation coating process, and the second metal located in the gate metal deposition area is the gate metal.