Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to the technical field of semiconductor technology, and relates to a semiconductor structure, a forming method thereof and a memory. The semiconductor structure comprises a substrate, a first dielectric layer, a conductive layer and a semiconductor layer. The substrate comprises an active region, and the active region has a word line trench. The first dielectric layer is conformally attached in the word line trench. The conductive layer is located on the surface of the first dielectric layer and fills part of the word line trench. A preset gap is formed between the end of the conductive layer away from the bottom of the word line trench and the first dielectric layer. The semiconductor layer is located on the top of the preset gap and the conductive layer. The semiconductor structure can reduce parasitic capacitance and GIDL.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] With the continuous development of mobile devices, battery-powered mobile devices such as mobile phones, tablets, and wearable devices are increasingly used in our lives. As an indispensable component in mobile devices, memory has generated huge demands for smaller size and integration.

[0003] However, as memory size continues to shrink, the number of word lines per unit area increases, resulting in smaller spacing between word lines and consequently, a greater increase in parasitic capacitance between them.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce parasitic capacitance and lower GIDL.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] A substrate, including an active region having word line trenches therein;

[0008] The first dielectric layer is conformally attached to the groove of the letter line;

[0009] A conductive layer is located on the surface of the first dielectric layer and fills part of the word line trench. The end of the conductive layer away from the bottom of the word line trench has a predetermined gap with the first dielectric layer.

[0010] A semiconductor layer is located on top of the preset gap and the conductive layer.

[0011] In one exemplary embodiment of this disclosure, the size of the top of the conductive layer is smaller than the size of the semiconductor layer in a direction perpendicular to the extension direction of the word line trench.

[0012] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0013] A first gap surrounds the sidewall of the semiconductor layer; and in a direction perpendicular to the extension direction of the word line trench, the size of the first gap is smaller than the size of the preset gap.

[0014] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0015] The second dielectric layer is located within the preset gap, and the semiconductor layer covers the surfaces of the conductive layer and the second dielectric layer.

[0016] In one exemplary embodiment of this disclosure, the dielectric constant of the second dielectric layer is less than that of the first dielectric layer.

[0017] In one exemplary embodiment of this disclosure, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer surrounding the sidewalls and bottom surface of the second semiconductor layer, and the doping concentration of the second semiconductor layer is greater than that of the first semiconductor layer.

[0018] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0019] A substrate is provided, the substrate including an active region having word line trenches within the active region;

[0020] A first conformally attached dielectric layer is formed within the groove of the letter line;

[0021] A conductive layer is formed on the surface of the first dielectric layer, the conductive layer fills part of the word line trench, and a predetermined gap exists between the end of the conductive layer away from the bottom of the word line trench and the first dielectric layer;

[0022] A semiconductor layer is formed on top of the conductive layer.

[0023] In one exemplary embodiment of this disclosure, forming the conductive layer includes:

[0024] A conductive material layer is formed on the surface of the first dielectric layer;

[0025] The conductive material layer is etched back to make the thickness of the conductive material layer located in the word line groove a preset thickness;

[0026] Remove the material from the edge region of the conductive material layer at one end away from the bottom of the word line groove, and the remaining conductive material layer forms the conductive layer.

[0027] In one exemplary embodiment of this disclosure, forming the semiconductor layer includes:

[0028] An insulating layer is formed, which fills the predetermined gap and at least covers the sidewalls of the word line groove and the top of the conductive layer;

[0029] Remove the insulating layer located on top of the conductive layer;

[0030] Deposit semiconductor material, the semiconductor material filling the remaining portion of the word line trench;

[0031] The semiconductor material is etched back to form the semiconductor layer;

[0032] Remove the remaining insulating layer to expose the predetermined gap, while simultaneously forming a first gap around the semiconductor layer.

[0033] In one exemplary embodiment of this disclosure, the forming method further includes:

[0034] A first passivation layer is formed on the surface of the semiconductor layer away from the conductive layer, and the first passivation layer seals the opening of the first gap.

[0035] In one exemplary embodiment of this disclosure, the forming method further includes:

[0036] Before forming the semiconductor layer, a dielectric material is filled in the preset gap to form a second dielectric layer, the semiconductor layer covering the surfaces of the conductive layer and the second dielectric layer.

[0037] In one exemplary embodiment of this disclosure, forming the second dielectric layer includes:

[0038] A dielectric material is deposited on the surface of the structure formed by the substrate, the first dielectric layer, and the conductive layer, and the dielectric material fills the predetermined gap.

[0039] Remove the dielectric material located outside the preset gap to form the second dielectric layer within the preset gap.

[0040] In one exemplary embodiment of this disclosure, forming the semiconductor layer includes:

[0041] A first semiconductor layer is formed conformally attached to the surface of the structure jointly formed by the substrate, the first dielectric layer, the conductive layer and the second dielectric layer;

[0042] A second semiconductor layer is formed on the surface of the first semiconductor layer, and the second semiconductor layer fills the word line trench;

[0043] The first semiconductor layer and the second semiconductor layer are etched back to form the semiconductor layer.

[0044] In one exemplary embodiment of this disclosure, when the first semiconductor layer and the second semiconductor layer are etched back, a portion of the first dielectric layer located on the sidewall of the word trench is removed so that the top of the first dielectric layer located on the sidewall of the word trench is flush with the top of the semiconductor layer.

[0045] In one exemplary embodiment of this disclosure, the forming method further includes:

[0046] A second passivation layer is formed on the surface of the semiconductor layer away from the conductive layer, and the second passivation layer covers the top of the first dielectric layer and the semiconductor layer.

[0047] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0048] The semiconductor structure and its formation method disclosed herein, as well as the memory, have the following advantages: First, the conductive layer and the semiconductor layer can jointly constitute a word line structure. By placing the word line structure within the word line trench, space can be saved, which is beneficial for the miniaturization design of the structure. Second, by setting a semiconductor layer with a low work function on the surface of the conductive layer, the gate-induced drain leakage current (GIDL) can be reduced while ensuring the turn-on voltage of the word line structure. Third, since the dielectric constant of the preset gap at the top edge of the conductive layer is relatively small, the parasitic capacitance between word line structures and between the word line structure and other surrounding structures (e.g., conductive plugs) can be reduced by setting the preset gap, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the memory. In addition, since the first dielectric layer is located on the sidewall of the word line structure, the sidewall of the word line structure can be insulated and protected by the first dielectric layer, thereby reducing the probability of coupling between the word line structure and other structures and further improving the product yield.

[0049] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0051] Figure 1a This is a schematic diagram of the semiconductor structure in the first embodiment of this disclosure;

[0052] Figure 1b This is a schematic diagram of the semiconductor structure in the second embodiment of this disclosure;

[0053] Figure 2 This is a schematic diagram of the semiconductor structure in the third embodiment of this disclosure;

[0054] Figure 3 This is a top view of the semiconductor structure in the embodiments of this disclosure;

[0055] Figure 4 This is a top view of the substrate in the embodiment of this disclosure;

[0056] Figure 5 As described in the embodiments of this disclosure Figure 4 A cross-sectional view cut along the dashed line;

[0057] Figure 6 This is a schematic diagram of the character line groove in the embodiment of this disclosure;

[0058] Figure 7 This is a schematic diagram of the first dielectric layer and conductive layer in the embodiments of this disclosure;

[0059] Figure 8a This is a schematic diagram of the semiconductor layer in the first embodiment of this disclosure;

[0060] Figure 8b This is a schematic diagram of the semiconductor layer in the second embodiment of this disclosure;

[0061] Figure 9 This is a schematic diagram of the semiconductor layer in the third embodiment of this disclosure;

[0062] Figure 10 This is a schematic diagram of the second dielectric layer in an embodiment of this disclosure;

[0063] Figure 11 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0064] Figure 12 This is a schematic diagram of the first dielectric layer in one embodiment of the present disclosure;

[0065] Figure 13 This is a schematic diagram showing the result after step S210 is completed in this embodiment of the present disclosure;

[0066] Figure 14 This is a schematic diagram showing the result after step S310 is completed in this embodiment of the present disclosure;

[0067] Figure 15 This is a schematic diagram showing the result after step S320 is completed in this embodiment of the present disclosure;

[0068] Figure 16 This is a schematic diagram showing the result after step S330 is completed in this embodiment of the present disclosure;

[0069] Figure 17 This is a schematic diagram showing the result after step S340 is completed in this embodiment of the present disclosure;

[0070] Figure 18This is a schematic diagram showing the result after step S410 is completed in this embodiment of the present disclosure;

[0071] Figure 19 This is a schematic diagram of the first semiconductor layer in one embodiment of the present disclosure;

[0072] Figure 20 This is a schematic diagram of the second semiconductor layer in one embodiment of the present disclosure.

[0073] Explanation of reference numerals in the attached figures:

[0074] 100. Word line structure; 1. Substrate; 11. Active region; 12. Shallow trench isolation junction; 101. Word line trench; 2. First dielectric layer; 3. Conductive layer; 301. Preset gap; 310. Conductive material layer; 4. Semiconductor layer; 401. First gap; 41. First semiconductor layer; 42. Second semiconductor layer; 410. Semiconductor material; 420. Air gap; 5. Second dielectric layer; 510. Dielectric material; 6. Insulating layer; 7. First passivation layer; 8. Second passivation layer. Detailed Implementation

[0075] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0076] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0077] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0078] This disclosure provides a semiconductor structure. Figure 1a A schematic diagram of a semiconductor structure according to a first embodiment of this disclosure is shown. Figure 1b A schematic diagram of the semiconductor structure in the second embodiment of this disclosure is shown. Figure 2 A schematic diagram of the semiconductor structure in the third embodiment of this disclosure is shown. Figure 3 A top view of the semiconductor structure in an embodiment of this disclosure is shown; see also Figures 1a-3 As shown, the semiconductor structure disclosed herein may include a substrate 1, a first dielectric layer 2, a conductive layer 3, and a semiconductor layer 4, wherein:

[0079] The substrate 1 may include an active region 11, in which word line trenches are provided;

[0080] The first dielectric layer 2 can be conformally attached to the groove of the letter line;

[0081] The conductive layer 3 may be located on the surface of the first dielectric layer 2 and fill part of the word line trench. The end of the conductive layer 3 away from the bottom of the word line trench has a preset gap with the first dielectric layer 2.

[0082] The semiconductor layer 4 can be located on top of the preset gap 301 and the conductive layer 3.

[0083] In the disclosed semiconductor structure, on the one hand, the conductive layer 3 and the semiconductor layer 4 can jointly form the word line structure 100. By placing the word line structure 100 in the word line trench, space can be saved, which is beneficial to the miniaturization design of the structure. On the other hand, by placing the semiconductor layer 4 with a low work function on the surface of the conductive layer 3, the gate-induced drain leakage current (GIDL) can be reduced by the semiconductor layer 4 while ensuring the turn-on voltage of the word line structure 100. On the other hand, since the dielectric constant of the preset gap 301 at the top edge of the conductive layer 3 is relatively small, the parasitic capacitance between word line structures 100 and other word line structures 100, as well as the parasitic capacitance between word line structures 100 and other surrounding structures (e.g., conductive plugs), can be reduced by setting the preset gap 301, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the memory. In addition, since the first dielectric layer 2 is located on the sidewall of the word line structure 100, the sidewall of the word line structure 100 can be insulated and protected by the first dielectric layer 2, thereby reducing the probability of coupling between the word line structure 100 and other structures and further improving the product yield.

[0084] The specific details of the semiconductor structure in the embodiments of this disclosure are described in detail below:

[0085] Figure 4 A top view of the substrate according to an embodiment of this disclosure is shown. Figure 5The embodiments of this disclosure are shown along Figure 4 Cross-sectional view cut along the dashed line; see also Figure 4 and Figure 5 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0086] In some embodiments of this disclosure, the substrate 1 may be a silicon substrate, with a shallow trench isolation structure 12 formed therein. The shallow trench isolation structure 12 is formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc., and is not specifically limited herein. The cross-sectional shape of the shallow trench isolation structure 12 can be set according to actual needs. The shallow trench isolation structure 12 can separate a plurality of active regions 11 on the substrate 1.

[0087] Figure 6 A schematic diagram of the word line groove 101 in an embodiment of this disclosure is shown. See also Figure 6 As shown, a plurality of word line trenches 101 extending along a first direction A may be provided in the substrate 1, and each word line trench 101 may be distributed at intervals along a second direction B. The word line trenches 101 may be groove-shaped structures formed by indentation from the surface of the substrate 1. In the first direction A, the word line trenches 101 may penetrate multiple active regions 11. In some embodiments, the depth of the word line trenches 101 may be 150nm to 300nm, for example, its depth may be 150nm, 200nm, 250nm or 300nm; and in the second direction B, the width of the word line trenches 101 may be 50nm to 100nm, for example, its width may be 50nm, 60nm, 70nm, 80nm, 90nm or 100nm. Of course, the depth or width of the word line trenches 101 may also be other values, which will not be listed here.

[0088] For example, the active regions 11 and the isolation material between them can be etched to form multiple word line trenches 101 penetrating each active region 11. Each word line trench 101 can extend along a first direction A and be arranged at intervals along a second direction B. In the first direction A, the word line trenches 101 can be continuous at both ends and can be strip-shaped, and the strip-shaped word line trenches 101 can be distributed in parallel.

[0089] In some embodiments, a photoresist layer can be formed on the surface of substrate 1 by spin coating or other methods. The photoresist layer material can be positive photoresist or negative photoresist, and no special limitation is made here.

[0090] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can be matched with the pattern required for the word line trench 101. Subsequently, the exposed photoresist layer can be developed to form multiple development areas. Each development area can expose a portion of the active region 11 and the shallow trench isolation structure 12 of the substrate 1, and the pattern of the development area can be the same as the pattern required for the word line trench 101. The size of each development area can be matched with the size of the required word line trench 101.

[0091] The substrate 1 can be etched in the developing area using a plasma etching process to form word line trenches 101 within the substrate 1. After completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes.

[0092] It should be noted that the first direction A can be any direction in the lateral extension direction of the substrate 1, and no special limitation is made to the first direction A here. The second direction B can intersect with the first direction A; for example, the first direction A can be perpendicular to the second direction B. It should be noted that perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during the manufacturing process. In this disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first direction A and the second direction B. As long as the angular deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction A and the second direction B can be considered perpendicular when the angle between the first direction A and the second direction B is greater than or equal to 80° and less than or equal to 100°.

[0093] Figure 7 A schematic diagram of the first dielectric layer 2 and the conductive layer 3 in an embodiment of this disclosure is shown. See also Figure 7 As shown, the first dielectric layer 2 can be conformally attached to the word line trench 101. The first dielectric layer 2 can be a thin film formed on the sidewalls and bottom of the word line trench 101, or it can be a coating formed on the sidewalls and bottom of the word line trench 101; no special limitation is made here. The first dielectric layer 2 can be made of an insulating material, for example, silicon oxide. The first dielectric layer 2 can be formed on the sidewalls and bottom of the word line trench 101 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. Of course, other methods can also be used to form the first dielectric layer 2 on the sidewalls and bottom of the word line trench 101, which will not be listed here.

[0094] In some embodiments of this disclosure, the thickness of the first dielectric layer 2 can be 2nm to 5nm. For example, its thickness can be 2nm, 3nm, 4nm or 5nm. Of course, the first dielectric layer 2 can also have other thicknesses, which will not be listed here.

[0095] A conductive layer 3 can be formed on the surface of the first dielectric layer 2. During this process, a conductive layer 3 can be formed in each word line trench 101, and the conductive layer 3 can fill a portion of the word line trench 101. For example, a conductive layer 3 is formed in each word line trench 101, and the conductive layer 3 in each word line trench 101 does not completely fill the corresponding word line trench 101; that is, the top of the conductive layer 3 is lower than the top of the word line trench 101.

[0096] In some embodiments of this disclosure, the thickness of the conductive layer 3 in the depth direction of the word line trench 201 can be 70nm to 75nm. For example, the thickness of the conductive layer 3 in the depth direction of the word line trench 201 can be 70nm, 71nm, 72nm, 73nm, 74nm or 75nm. Of course, the conductive layer 3 can also be other thicknesses, which will not be listed here.

[0097] In some embodiments of this disclosure, the conductive layer 3 may be a thin film formed at the bottom of the word line trench 101. Its material may be titanium nitride. The conductive layer 3 can be formed at the bottom of the word line trench 101 by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. One end of the conductive layer 3 near the bottom of the word line trench 101 may be in conformal contact with the first dielectric layer 2 located on the sidewall and bottom of the word line trench 101. A predetermined gap 301 exists between the end of the conductive layer 3 away from the bottom of the word line trench 101 and the first dielectric layer 2. Furthermore, along the length of the word line trench 101, both ends of the predetermined gap 301 may be flush with the ends of the conductive layer 3 away from the bottom of the word line trench 101. The opening of the predetermined gap 301 may be located between the top surface of the conductive layer 3 and the first dielectric layer 2.

[0098] In some embodiments of this disclosure, the height of the preset gap 301 in the depth direction of the word line groove 101 can be 10nm to 20nm, for example, its height can be 10nm, 15nm or 20nm; in the width direction of the word line groove 101 (i.e., in the second direction B), the width of the preset gap 301 can be 5nm to 10nm, for example, its width can be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm; of course, the preset gap 301 can also be other heights or other widths, which will not be listed here.

[0099] Figure 8a A schematic diagram of the semiconductor layer in a first embodiment of this disclosure is shown; Figure 8b A schematic diagram of the semiconductor layer in a second embodiment of this disclosure is shown; Figure 9 A schematic diagram of the semiconductor layer in a third embodiment of this disclosure is shown; see also Figures 8a-9As shown, the semiconductor layer 4 can be located on top of the preset gap 301 and the conductive layer 3. In a direction perpendicular to the extension direction of the word line trench 101 (the width direction of the word line trench 101 or the second direction B), the size of the top of the conductive layer 3 can be smaller than the size of the semiconductor layer 4. For example, the semiconductor layer 4 can cover the entire top surface of the conductive layer 3 and can extend from the surface of the conductive layer 3 to the top of the preset gap 301.

[0100] The layout details of semiconductor layer 4 are described in detail below through three implementation methods:

[0101] See also the first and second embodiments of this disclosure. Figure 8a and Figure 8b As shown, in the width direction of the word line trench 101 (i.e., in the second direction B), the semiconductor layer 4 is not in contact with the first dielectric layer 2, and a first gap 401 exists between the sidewall of the semiconductor layer 4 and the first dielectric layer 2. In the length direction of the word line trench 101, the first gap 401 can surround the sidewall of the semiconductor layer 4; that is, in the length direction of the word line trench 101, the two ends of the first gap 401 can be flush with the two ends of the semiconductor layer 4.

[0102] The semiconductor layer 4 can be a thin film formed on top of the conductive layer 3. Its material can be polycrystalline silicon. The semiconductor layer 4 can be formed on top of the conductive layer 3 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation. Of course, the semiconductor layer 4 can also be formed by other methods. No special limitation is made on the formation method of the semiconductor layer 4 here.

[0103] In some embodiments of this disclosure, the semiconductor layer 4 may be n-type doped to reduce the work function of the semiconductor layer 4, thereby improving the gate control capability of the word line structure 100.

[0104] In some embodiments of this disclosure, the thickness of the semiconductor layer 4 can be 40nm to 55nm. For example, the thickness of the semiconductor layer 4 can be 40nm, 45nm, 50nm or 55nm. Of course, the semiconductor layer 4 can also be of other thicknesses, which will not be listed here.

[0105] In some embodiments of this disclosure, the size of the first gap 401 may be smaller than the size of the preset gap 301 in the direction perpendicular to the extension direction of the word line groove 101 (i.e., in the width direction of the word line groove 101 or in the second direction B). For example, in the width direction of the word line groove 101 (i.e., in the second direction B), the width of the first gap 401 may be smaller than the width of the preset gap 301. For example, the width of the first gap 401 may be 3nm to 5nm, such as 3nm, 4nm, or 5nm. Of course, the first gap 401 may also have other widths, which will not be listed here. Meanwhile, in the depth direction of the word line trench 101, the height of the first gap 401 is equal to the thickness of the semiconductor layer 4 (that is, in the thickness direction of the semiconductor layer 4, the two ends of the first gap 401 are flush with the two ends of the semiconductor layer 4). For example, the height of the first gap 401 can be 40nm to 55nm, for example, its height can be 40nm, 45nm, 50nm or 55nm; of course, the first gap 401 can also be other heights, which will not be listed here.

[0106] In one exemplary embodiment of this disclosure, the bottom of the first gap 401 can be connected to the opening of the preset gap 301, thereby enabling the first gap 401 to communicate with the preset gap 301. The structure formed by the first gap 401 and the preset gap 301 can be defined as an air gap 420.

[0107] The difference between the semiconductor layer 4 in the second embodiment and the first embodiment of this disclosure is that:

[0108] In the first embodiment, the semiconductor layer 4 is a single-layer film. This single-layer film can be made of polycrystalline silicon, and the single-crystalline silicon can be n-type doped to improve the gate control capability of the word line structure 100. For example, the doping concentration of this single-layer film can be 8.6*e 20 .

[0109] In the second embodiment, the semiconductor layer 4 is a multilayer film layer. For example, it may include a first semiconductor layer 41 and a second semiconductor layer 42. The second semiconductor layer 42 may be located on top of the conductive layer 3. The first semiconductor layer 41 may be conformally attached to the bottom and sidewall of the second semiconductor layer 42. The first gap 401 may be located between the first semiconductor layer 41 and the first dielectric layer 2 located on the sidewall of the word line trench 101.

[0110] In some embodiments of this disclosure, the height of the first semiconductor layer 41 in the depth direction of the word line trench 101 can be 40nm to 55nm, for example, its height can be 40nm, 45nm, 50nm or 55nm; of course, the first semiconductor layer 41 can also have other heights, which will not be listed here.

[0111] In some embodiments of this disclosure, the thickness of the first semiconductor layer 41 can be 2nm to 10nm. For example, the thickness of the first semiconductor layer 41 can be 2nm, 4nm, 6nm, 8nm or 10nm. Of course, the first semiconductor layer 41 can also have other thicknesses, which will not be listed here.

[0112] The material of the first semiconductor layer 41 can be a material with a relatively low dielectric constant, which helps to reduce parasitic capacitance. At the same time, the first semiconductor layer 41 can reduce gate-induced drain leakage current (GIDL) while ensuring the turn-on voltage of the word line structure 100. For example, the material of the first semiconductor layer 41 can be polysilicon.

[0113] The material of the second semiconductor layer 42 can be the same as that of the first semiconductor layer 41. For example, both the second semiconductor layer 42 and the first semiconductor layer 41 can be made of polysilicon. The difference is that the doping concentration of the second semiconductor layer 42 can be greater than that of the first semiconductor layer 41, thereby making the second semiconductor layer 42 have a lower work function, so as to further improve the gate control capability of the word line structure 100. In this way, while ensuring the turn-on voltage of the word line structure 100, the gate-induced drain leakage current (GIDL) can be further reduced by the second semiconductor layer 42.

[0114] For example, the second semiconductor layer 42 can be n-type doped. The n-type doping material can be an element located in Group V of the periodic table. For example, it can be phosphorus. Of course, it can also be other elements, which will not be listed here.

[0115] In some embodiments of this disclosure, phosphorus ions can be implanted into the second semiconductor layer 42 by ion implantation. Of course, other methods can also be used to perform n-type doping on the second semiconductor layer 42, and no special limitation is made here.

[0116] In some embodiments of this disclosure, see also Figure 1a and Figure 1b As shown, the semiconductor structure disclosed herein may further include a first passivation layer 7. The first passivation layer 7 may be a thin film formed on the surface of the semiconductor layer 4, or it may be a coating formed on the surface of the semiconductor layer 4. No specific limitation is made here on the specific form of the first passivation layer 7. The material of the first passivation layer 7 may be an insulating material. The first passivation layer 7 can provide insulation protection for the surface of the word line structure 100, which can not only avoid damage to the surface of the word line structure 100 by subsequent processes, but also reduce the possibility of coupling or short circuit between the word line structure 100 and other surrounding structures, thereby improving product yield.

[0117] The material of the first passivation layer 7 can be silicon oxide or silicon nitride, and the first passivation layer 7 can be formed on the surface of the semiconductor layer 4 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation.

[0118] In the third embodiment of this disclosure, see also Figure 9 As shown, semiconductor layer 4 may include a first semiconductor layer 41 and a second semiconductor layer 42, wherein:

[0119] The first semiconductor layer 41 can contact the top surface of the conductive layer 3 and extend laterally along the top surface of the conductive layer 3, thereby contacting and connecting with the first dielectric layer 2 located on the sidewall of the word line trench 101. Simultaneously, the first semiconductor layer 41 can also be attached to a portion of the surface of the first dielectric layer 2. For example, the first semiconductor layer 41 can be attached to the surface of the first dielectric layer 2 on the side of the preset gap 301 away from the bottom of the word line trench 101. The first semiconductor layer 41 can be formed on the top of the conductive layer 3 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. Of course, other methods can also be used to form the first semiconductor layer 41; no specific limitation is made here regarding the formation method of the first semiconductor layer 41.

[0120] See also Figure 9 As shown, the second semiconductor layer 42 may be located on the surface of the first semiconductor layer 41, the first semiconductor layer 41 may surround the sidewalls and bottom surface of the second semiconductor layer 42, and the surface of the second semiconductor layer 42 may be flush with the top of the first semiconductor layer 41.

[0121] It should be noted that other details of the first semiconductor layer 41 and the second semiconductor layer 42 in the third embodiment of this disclosure can be found in the first semiconductor layer 41 and the second semiconductor layer 42 in the second embodiment of this disclosure, and will not be repeated here.

[0122] In a third embodiment of this disclosure, the semiconductor structure may further include a second dielectric layer 5. Figure 10 A schematic diagram of the second dielectric layer 5 in an embodiment of this disclosure is shown. See also Figure 10 As shown, the second dielectric layer 5 can be located within the preset gap 301, for example, the second dielectric layer 5 can fill the preset gap 301. The thickness of the dielectric layer in the sidewall of the word line trench 101 can be increased by setting the second dielectric layer 5, which helps to increase the distance between the overlapping area of ​​the drain and the word line structure 100, thereby reducing the electric field strength in the overlapping area and thus reducing GIDL; at the same time, as the thickness of the dielectric layer on the sidewall of the word line trench 101 increases, the physical distance between adjacent word line structures 100 can be increased, and the parasitic capacitance between adjacent word line structures 100 can be reduced.

[0123] The material of the second dielectric layer 5 can be an insulating material, and the material of the second dielectric layer 5 can be the same as that of the first dielectric layer 2. For example, both the second dielectric layer 5 and the first dielectric layer 2 can be silicon oxide. Of course, the materials of the second dielectric layer 5 and the first dielectric layer 2 can also be different. For example, the dielectric constant of the second dielectric layer 5 can be lower than that of the first dielectric layer 2. For example, the material of the second dielectric layer 5 can be a material with a low dielectric constant, which can better reduce the parasitic capacitance between adjacent word line structures 100. For example, the material of the second dielectric layer 5 can be a material with a dielectric constant lower than that of silicon oxide (3.9), such as: low dielectric constant materials based on silicon-based polymers (hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ)), fluorinated silicon dioxide, fluorinated amorphous carbon, or aerogel, etc.

[0124] In some embodiments of this disclosure, see also Figure 9 As shown, the semiconductor layer 4 can cover the surfaces of the conductive layer 3 and the second dielectric layer 5. For example, the first semiconductor layer 41 can simultaneously cover the surfaces of the conductive layer 3 and the second dielectric layer 5, and contact the first dielectric layer 2 exposed on the sidewall of the word line trench 101.

[0125] In the third embodiment of this disclosure, see also Figure 2 As shown, the semiconductor structure disclosed herein may further include a second passivation layer 8. The second passivation layer 8 may be a thin film formed on the surface of the semiconductor layer 4, or it may be a coating formed on the surface of the semiconductor layer 4. No specific limitation is made here regarding the specific form of the second passivation layer 8. The material of the second passivation layer 8 may be an insulating material. The second passivation layer 8 can provide insulation protection for the surface of the word line structure 100, which can prevent subsequent processes from damaging the surface of the word line structure 100 and reduce the possibility of coupling or short circuits between the word line structure 100 and other surrounding structures, thereby improving product yield.

[0126] The material of the second passivation layer 8 can be the same as or different from the material of the first passivation layer 7, and no special limitation is made here. For example, the material of the second passivation layer 8 can be silicon oxide or silicon nitride, and the second passivation layer 8 can be formed on the surface of the semiconductor layer 4 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation.

[0127] In one exemplary embodiment of this disclosure, a method for forming a semiconductor structure is also provided. Figure 11 A flowchart illustrating the method for forming the semiconductor structure of this disclosure is shown; see [link to flowchart]. Figure 11 As shown, the forming method may include steps S110-S140, wherein:

[0128] Step S110: Provide a substrate, the substrate including an active region having word line trenches within the active region;

[0129] Step S120: A first conformal dielectric layer is formed within the groove of the letter line;

[0130] Step S130: A conductive layer is formed on the surface of the first dielectric layer. The conductive layer fills part of the word line trench. A predetermined gap exists between the end of the conductive layer away from the bottom of the word line trench and the first dielectric layer.

[0131] Step S140: A semiconductor layer is formed on top of the conductive layer.

[0132] The steps and specific details of the method for forming the semiconductor structure in the embodiments of this disclosure are described in detail below:

[0133] like Figure 11 As shown, in step S110, a substrate 1 is provided, the substrate 1 including an active region 11, the active region 11 having a word line trench 101.

[0134] The substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1.

[0135] In some embodiments of this disclosure, such as Figure 4 and Figure 5 As shown, substrate 1 can be a silicon substrate, with a shallow trench isolation structure 12 formed inside it. The shallow trench isolation structure 12 is formed by forming trenches in substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structure 12 can include silicon nitride or silicon oxide, etc., without special limitation. The cross-sectional shape of the shallow trench isolation structure 12 can be set according to actual needs. The shallow trench isolation structure 12 can separate several active regions 11 on substrate 1.

[0136] See also Figure 6As shown, a plurality of word line trenches 101 extending along a first direction A may be provided in the substrate 1, and each word line trench 101 may be distributed at intervals along a second direction B. The word line trenches 101 may be groove-shaped structures formed by indentation from the surface of the substrate 1. In the first direction A, the word line trenches 101 may penetrate multiple active regions 11. In some embodiments, the depth of the word line trenches 101 may be 150nm to 300nm, for example, its depth may be 150nm, 200nm, 250nm or 300nm; and in the second direction B, the width of the word line trenches 101 may be 50nm to 100nm, for example, its width may be 50nm, 60nm, 70nm, 80nm, 90nm or 100nm. Of course, the depth or width of the word line trenches 101 may also be other values, which will not be listed here.

[0137] For example, the active regions 11 and the isolation material between them can be etched to form multiple word line trenches 101 penetrating each active region 11. Each word line trench 101 can extend along a first direction A and be arranged at intervals along a second direction B. In the first direction A, the word line trenches 101 can be continuous at both ends and can be strip-shaped, and the strip-shaped word line trenches 101 can be distributed in parallel.

[0138] In some embodiments, a photoresist layer can be formed on the surface of substrate 1 by spin coating or other methods. The photoresist layer material can be positive photoresist or negative photoresist, and no special limitation is made here.

[0139] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can be matched with the pattern required for the word line trench 101. Subsequently, the exposed photoresist layer can be developed to form multiple development areas. Each development area can expose a portion of the active region 11 and the shallow trench isolation structure 12 of the substrate 1, and the pattern of the development area can be the same as the pattern required for the word line trench 101. The size of each development area can be matched with the size of the required word line trench 101.

[0140] The substrate 1 can be etched in the developing area using a plasma etching process to form word line trenches 101 within the substrate 1. After completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes.

[0141] It should be noted that the first direction A can be any direction in the lateral extension direction of the substrate 1, and no special limitation is made to the first direction A here. The second direction B can intersect with the first direction A; for example, the first direction A can be perpendicular to the second direction B. It should be noted that perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during the manufacturing process. In this disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first direction A and the second direction B. As long as the angular deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction A and the second direction B can be considered perpendicular when the angle between the first direction A and the second direction B is greater than or equal to 80° and less than or equal to 100°.

[0142] like Figure 11 As shown, in step S120, a first conformally attached dielectric layer 2 is formed in the word line groove 101.

[0143] See also Figure 7 As shown, the first dielectric layer 2 can be conformally attached to the word line trench 101. The first dielectric layer 2 can be a thin film formed on the sidewalls and bottom of the word line trench 101, or it can be a coating formed on the sidewalls and bottom of the word line trench 101; no special limitation is made here. The first dielectric layer 2 can be made of an insulating material, for example, silicon oxide. The first dielectric layer 2 can be formed on the sidewalls and bottom of the word line trench 101 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. Of course, other methods can also be used to form the first dielectric layer 2 on the sidewalls and bottom of the word line trench 101, which will not be listed here.

[0144] It should be noted that, for ease of fabrication, during the formation of the first dielectric layer 2, the first dielectric layer 2 can be formed simultaneously on top of the substrate 1 (e.g., ...). Figure 12 (As shown), the first dielectric layer 2 located on top of the substrate 1 can then be removed, leaving only the first dielectric layer 2 located within the word line trench 101.

[0145] In some embodiments of this disclosure, the thickness of the first dielectric layer 2 can be 2nm to 5nm. For example, its thickness can be 2nm, 3nm, 4nm or 5nm. Of course, the first dielectric layer 2 can also have other thicknesses, which will not be listed here.

[0146] like Figure 11 As shown, in step S130, a conductive layer 3 is formed on the surface of the first dielectric layer 2. The conductive layer 3 fills part of the word line groove 101. A predetermined gap 301 is formed between the end of the conductive layer 3 away from the bottom of the word line groove 101 and the first dielectric layer 2.

[0147] A conductive layer 3 can be formed on the surface of the first dielectric layer 2. During this process, a conductive layer 3 can be formed in each word line trench 101, and the conductive layer 3 can fill a portion of the word line trench 101. For example, a conductive layer 3 is formed in each word line trench 101, and the conductive layer 3 in each word line trench 101 does not completely fill the corresponding word line trench 101; that is, the top of the conductive layer 3 is lower than the top of the word line trench 101.

[0148] In some embodiments of this disclosure, the thickness of the conductive layer 3 in the depth direction of the word line trench 201 can be 70nm to 75nm. For example, the thickness of the conductive layer 3 in the depth direction of the word line trench 201 can be 70nm, 71nm, 72nm, 73nm, 74nm or 75nm. Of course, the conductive layer 3 can also be other thicknesses, which will not be listed here.

[0149] In some embodiments of this disclosure, the conductive layer 3 may be a thin film formed at the bottom of the word line trench 101. Its material may be titanium nitride. The conductive layer 3 can be formed at the bottom of the word line trench 101 by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. One end of the conductive layer 3 near the bottom of the word line trench 101 may be in conformal contact with the first dielectric layer 2 located on the sidewall and bottom of the word line trench 101. A predetermined gap 301 exists between the end of the conductive layer 3 away from the bottom of the word line trench 101 and the first dielectric layer 2. Furthermore, along the length of the word line trench 101, both ends of the predetermined gap 301 may be flush with the ends of the conductive layer 3 away from the bottom of the word line trench 101. The opening of the predetermined gap 301 may be located between the top surface of the conductive layer 3 and the first dielectric layer 2.

[0150] In some embodiments of this disclosure, the height of the preset gap 301 in the depth direction of the word line groove 101 can be 10nm to 20nm, for example, its height can be 10nm, 15nm or 20nm; in the width direction of the word line groove 101 (i.e., in the second direction B), the width of the preset gap 301 can be 5nm to 10nm, for example, its width can be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm; of course, the preset gap 301 can also be other heights or other widths, which will not be listed here.

[0151] In one exemplary embodiment of this disclosure, forming the semiconductor layer 4 may include steps S210-S230, wherein:

[0152] Step S210: A conductive material layer 310 is formed on the surface of the first dielectric layer 2.

[0153] like Figure 13As shown, the conductive material layer 310 can be a thin film formed on the surface of the first dielectric layer 2. Its material can be titanium nitride. The conductive material layer 310 can be formed on the surface of the first dielectric layer 2 by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. Of course, other methods can also be used to form the conductive material layer 310. No specific limitations are placed on the formation method of the conductive material layer 310 here. It should be noted that, in order to accurately control the thickness of the conductive layer 3, the conductive material layer 310 can at least fill the word line trench 101 of the first dielectric layer 2. During this process, for ease of fabrication, the conductive material layer 310 can also cover the top of the substrate 1.

[0154] Step S220: The conductive material layer 310 is etched back so that the thickness of the conductive material layer 310 located in the word line groove 101 is a preset thickness.

[0155] A dry etching process can be used to etch back the conductive material layer 310, thereby removing the conductive material layer 310 located on top of the substrate 1, while retaining the predetermined conductive material layer 310 within the word line trench 101. For example, carbon tetrafluoride can be used as the etching gas to etch back the conductive material layer 310. Of course, other gases can also be used to etch back the conductive material layer 310, as long as the conductive material layer 310 can be etched away without damaging other structures. No special limitation is made to the etching gas here.

[0156] In some embodiments of this disclosure, the preset thickness can be 70nm to 75nm. For example, the preset thickness can be 70nm, 71nm, 72nm, 73nm, 74nm or 75nm. Of course, the preset thickness can also be other thicknesses, which will not be listed here.

[0157] Step S230: Remove the material from the edge region of the conductive material layer 310 at the end away from the bottom of the word line groove 101, and the remaining conductive material layer 310 forms the conductive layer 3.

[0158] After etching back to retain the conductive material layer 310 of a predetermined thickness, the material at the edge region of the conductive material layer 310 away from the bottom of the word line trench 101 can be removed by adjusting the etching gas, so as to form the conductive layer 3. For example, when removing the material at the edge region of the conductive material layer 310 away from the bottom of the word line trench 101, the etching gas can be replaced with chlorine gas, that is: chlorine gas can be used as the etching gas to etch the material at the edge region of the conductive material layer 310 away from the bottom of the word line trench 101, thereby forming a predetermined gap 301 between the end of the conductive layer 3 away from the bottom of the word line trench 101 and the first dielectric layer 2. The structure after completing step S230 is as follows. Figure 7As shown.

[0159] In some embodiments of this disclosure, the height of the preset gap 301 in the depth direction of the word line groove 101 can be 10nm to 20nm, for example, its height can be 10nm, 15nm or 20nm; in the width direction of the word line groove 101 (i.e., in the second direction B), the width of the preset gap 301 can be 5nm to 10nm, for example, its width can be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm; of course, the preset gap 301 can also be other heights or other widths, which will not be listed here.

[0160] like Figure 11 As shown, in step S140, a semiconductor layer 4 is formed on top of the conductive layer 3.

[0161] The semiconductor layer 4 may be located on top of the preset gap 301 and the conductive layer 3. In a direction perpendicular to the extension direction of the word line trench 101 (the width direction of the word line trench 101 or the second direction B), the size of the top of the conductive layer 3 may be smaller than the size of the semiconductor layer 4. For example, the semiconductor layer 4 may cover the entire top surface of the conductive layer 3 and may extend from the surface of the conductive layer 3 to the top of the preset gap 301.

[0162] See also the first and second embodiments of this disclosure. Figure 8a and Figure 8b As shown, in the width direction of the word line trench 101 (i.e., in the second direction B), the semiconductor layer 4 is not in contact with the first dielectric layer 2, and a first gap 401 exists between the sidewall of the semiconductor layer 4 and the first dielectric layer 2. In the length direction of the word line trench 101, the first gap 401 can surround the sidewall of the semiconductor layer 4; that is, in the length direction of the word line trench 101, the two ends of the first gap 401 can be flush with the two ends of the semiconductor layer 4.

[0163] The semiconductor layer 4 can be a thin film formed on top of the conductive layer 3. Its material can be polycrystalline silicon. The semiconductor layer 4 can be formed on top of the conductive layer 3 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation. Of course, the semiconductor layer 4 can also be formed by other methods. No special limitation is made on the formation method of the semiconductor layer 4 here.

[0164] In some embodiments of this disclosure, the thickness of the semiconductor layer 4 can be 40nm to 55nm. For example, the thickness of the semiconductor layer 4 can be 40nm, 45nm, 50nm or 55nm. Of course, the semiconductor layer 4 can also be of other thicknesses, which will not be listed here.

[0165] In some embodiments of this disclosure, the size of the first gap 401 may be smaller than the size of the preset gap 301 in the direction perpendicular to the extension direction of the word line groove 101 (i.e., in the width direction of the word line groove 101 or in the second direction B). For example, in the width direction of the word line groove 101 (i.e., in the second direction B), the width of the first gap 401 may be smaller than the width of the preset gap 301. For example, the width of the first gap 401 may be 3nm to 5nm, such as 3nm, 4nm, or 5nm. Of course, the first gap 401 may also have other widths, which will not be listed here. Meanwhile, in the depth direction of the word line trench 101, the height of the first gap 401 is equal to the thickness of the semiconductor layer 4 (that is, in the thickness direction of the semiconductor layer 4, the two ends of the first gap 401 are flush with the two ends of the semiconductor layer 4). For example, the height of the first gap 401 can be 40nm to 55nm, for example, its height can be 40nm, 45nm, 50nm or 55nm; of course, the first gap 401 can also be other heights, which will not be listed here.

[0166] In one exemplary embodiment of this disclosure, the bottom of the first gap 401 can be connected to the opening of the preset gap 301, thereby enabling the first gap 401 to communicate with the preset gap 301. The structure formed by the first gap 401 and the preset gap 301 can be defined as an air gap 420.

[0167] The formation process of the semiconductor layer 4 of this disclosure will be described below using the first embodiment as an example:

[0168] In the first embodiment of this disclosure, forming the semiconductor layer 4 may include steps S310-S350, wherein:

[0169] Step S310: An insulating layer 6 is formed, which fills the preset gap 301 and at least covers the sidewall of the word line groove 101 and the top of the conductive layer 3.

[0170] The insulating layer 6 can at least fill the opening of the preset gap 301 and cover the surface of the first dielectric layer 2 located on the sidewall of the word line trench 101. During the formation of the insulating layer 6, for the convenience of the process, the insulating layer 6 can be formed simultaneously on the surface of the structure jointly formed by the substrate 1, the first dielectric layer 2 and the conductive layer 3; that is, the insulating layer 6 can fill the preset gap 301 and simultaneously cover the top of the conductive layer 3 and the surface of the first dielectric layer 2 located on the sidewall of the word line trench 101.

[0171] The insulating layer 6 can be made of an insulating material, such as silicon nitride. The insulating layer 6 can be formed on the surface of the structure consisting of the substrate 1, the first dielectric layer 2, and the conductive layer 3 by methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the insulating layer 6; no specific limitation is made here. In this embodiment, the structure after step S310 is as follows: Figure 14 As shown.

[0172] Step S320: Remove the insulating layer 6 located on top of the conductive layer 3.

[0173] The insulating layer 6 can be etched back to expose the surface of the conductive layer 3. For example, the conductive layer 3 can be used as the etch stop layer, and a dry etching process can be used to etch back the insulating layer 6 until the top surface of the conductive layer 3 is exposed.

[0174] It should be noted that during the etch-back process of the insulating layer 6, the insulating layer 6 attached to the surface of the first dielectric layer 2 can be retained. After the etch-back process, the thickness of the remaining insulating layer 6 in the width direction (i.e., the second direction B) of the word line trench 101 can be 3nm to 5nm, for example, its thickness can be 3nm, 4nm, or 5nm. In this embodiment, the structure after completing step S320 is as follows: Figure 15 As shown.

[0175] Step S330: Deposit semiconductor material 410, which fills the remaining portion of the word line trench 101.

[0176] Semiconductor material 410 can be polycrystalline silicon. It can be deposited on the surfaces of conductive layer 3 and insulating layer 6 using methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. Of course, other methods can also be used to deposit semiconductor material 410; no specific limitation is made here. It should be noted that, in order to accurately control the thickness of semiconductor layer 4, semiconductor material 410 can fill the word line trench 101. During this process, for ease of fabrication, semiconductor material 410 can simultaneously cover the top of substrate 1. In this embodiment, the structure after step S330 is as follows: Figure 16 As shown.

[0177] Step S340: The semiconductor material 410 is etched back to form the semiconductor layer 4.

[0178] The semiconductor material 410 can be etched using a dry etching process to retain a certain thickness of semiconductor material 410. In some embodiments, the thickness of the remaining semiconductor material 410 can be 40nm to 55nm. For example, the thickness of the remaining semiconductor material 410 can be 40nm, 45nm, 50nm or 55nm. Of course, the remaining semiconductor material 410 can also be of other thicknesses, which will not be listed here.

[0179] It should be noted that during the etch-back process of the semiconductor material 410, the insulating layer 6 located on the surface of the first dielectric layer 2 can be etched simultaneously, and the etching of the insulating layer 6 can be stopped after the semiconductor layer 4 is formed. In this embodiment, the structure after completing step S340 is as follows: Figure 17 As shown.

[0180] In step S350, the remaining insulating layer 6 is removed to expose the preset gap 301, while a first gap 401 is formed around the semiconductor layer 4.

[0181] The remaining insulating layer 6 can be removed by an etching process. For example, the insulating layer 6 can be removed by a wet etching process, such as by using hot phosphoric acid to clean the sidewalls of the word line trench 101, thereby removing the insulating layer 6. It should be noted that other solutions can also be used to remove the insulating layer 6, as long as the insulating layer 6 can be removed without damaging other structures.

[0182] After removing the insulating layer 6, the preset gap 301 is exposed, and a first gap 401 is formed between the semiconductor layer 4 and the first dielectric layer 2. In this embodiment, the structure after completing step S350 is shown in Figure 8.

[0183] In the first and second embodiments of this disclosure, the method for forming the semiconductor structure may further include:

[0184] In step S150, a first passivation layer 7 is formed on the surface of the semiconductor layer 4 away from the conductive layer 3, and the first passivation layer 7 seals the opening of the first gap 401.

[0185] Referring again to Figure 1, the first passivation layer 7 can be a thin film formed on the surface of the semiconductor layer 4, or it can be a coating formed on the surface of the semiconductor layer 4. No specific limitations are made on the specific form of the first passivation layer 7. The material of the first passivation layer 7 can be an insulating material. The first passivation layer 7 can provide insulation protection for the surface of the word line structure 100, which can prevent damage to the surface of the word line structure 100 caused by subsequent processes, and reduce the possibility of coupling or short circuits between the word line structure 100 and other surrounding structures, thereby improving product yield.

[0186] For example, the material of the first passivation layer 7 can be silicon oxide or silicon nitride, and the first passivation layer 7 can be formed on the surface of the semiconductor layer 4 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation.

[0187] In a third embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0188] In step S160, before forming the semiconductor layer 4, a dielectric material is filled in the preset gap 301 to form a second dielectric layer 5, wherein the semiconductor layer 4 covers the surface of the conductive layer 3 and the second dielectric layer 5.

[0189] See also Figure 10 As shown, the second dielectric layer 5 can fill the preset gap 301. The thickness of the dielectric layer in the sidewall of the word line trench 101 can be increased by setting the second dielectric layer 5, which helps to increase the distance between the overlapping area of ​​the drain and the word line structure 100, and can reduce the electric field strength in the overlapping area, thereby reducing GIDL. At the same time, as the thickness of the dielectric layer on the sidewall of the word line trench 101 increases, the physical distance between adjacent word line structures 100 can be increased, and the parasitic capacitance between adjacent word line structures 100 can be reduced.

[0190] The material of the second dielectric layer 5 can be an insulating material, and the material of the second dielectric layer 5 can be the same as that of the first dielectric layer 2. For example, both the second dielectric layer 5 and the first dielectric layer 2 can be silicon oxide. Of course, the materials of the second dielectric layer 5 and the first dielectric layer 2 can also be different. For example, the dielectric constant of the second dielectric layer 5 can be lower than that of the first dielectric layer 2. For example, the material of the second dielectric layer 5 can be a material with a low dielectric constant, which can better reduce the parasitic capacitance between adjacent word line structures 100. For example, the material of the second dielectric layer 5 can be a material with a dielectric constant lower than that of silicon oxide (3.9), such as: low dielectric constant materials based on silicon-based polymers (hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ)), fluorinated silicon dioxide, fluorinated amorphous carbon, or aerogel, etc.

[0191] In one exemplary embodiment of this disclosure, forming the second dielectric layer 5 may include steps S410 and S420, wherein:

[0192] In step S410, a dielectric material 510 is deposited on the surface of the structure formed by the substrate 1, the first dielectric layer 2, and the conductive layer 3, and the dielectric material 510 fills the preset gap 301.

[0193] The dielectric material 510 can at least fill the preset gap 301. During the deposition of the dielectric material 510, for ease of processing, the dielectric material 510 can be deposited simultaneously on the surface of the structure formed by the substrate 1, the first dielectric layer 2, and the conductive layer 3; that is, the dielectric material 510 can fill the preset gap 301 and simultaneously cover the top of the conductive layer 3 and the surface of the first dielectric layer 2 located on the sidewall of the word line trench 101. In this embodiment, the structure after step S410 is as follows... Figure 18 As shown.

[0194] The dielectric material 510 can be an insulating material, for example, silicon oxide. The dielectric material 510 can be deposited on the surface of the structure formed by the substrate 1, the first dielectric layer 2 and the conductive layer 3 by means of chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the dielectric material 510 can also be deposited by other means. No special limitation is made here on the deposition method of the dielectric material 510.

[0195] Step S420: Remove the dielectric material 510 located outside the preset gap 301 to form the second dielectric layer 5 within the preset gap 301.

[0196] The dielectric material 510 can be etched back to expose the surface of the conductive layer 3. For example, the conductive layer 3 can be used as an etch stop layer, and a dry etching process can be used to etch back the dielectric material 510 until the top surface of the conductive layer 3 is exposed. That is, after etching, the remaining dielectric material 510 fills the preset gap 301, and the top of the remaining dielectric material 510 is flush with the top of the conductive layer 3. The remaining dielectric material 510 can then be considered the second dielectric layer 5. Figure 10 As shown. In the depth direction of the word line trench 101, the height of the second dielectric layer 5 can be 10nm to 20nm, for example, its height can be 10nm, 15nm or 20nm; in the width direction of the word line trench 101 (i.e., in the second direction B), the width of the second dielectric layer 5 can be 5nm to 10nm, for example, its width can be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm; of course, the second dielectric layer 5 can also have other heights or other widths, which will not be listed here.

[0197] In the third embodiment of this disclosure, see also Figure 9 As shown, semiconductor layer 4 may include a first semiconductor layer 41 and a second semiconductor layer 42, wherein:

[0198] The first semiconductor layer 41 can contact the top surface of the conductive layer 3 and extend laterally along the top surface of the conductive layer 3, thereby contacting and connecting with the first dielectric layer 2 located on the sidewall of the word line trench 101. Simultaneously, the first semiconductor layer 41 can also be attached to a portion of the surface of the first dielectric layer 2. For example, the first semiconductor layer 41 can be attached to the surface of the first dielectric layer 2 on the side of the preset gap 301 away from the bottom of the word line trench 101. The first semiconductor layer 41 can be formed on the top of the conductive layer 3 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. Of course, other methods can also be used to form the first semiconductor layer 41; no specific limitation is made here regarding the formation method of the first semiconductor layer 41.

[0199] In some embodiments of this disclosure, the height of the first semiconductor layer 41 in the depth direction of the word line trench 101 can be 40nm to 55nm, for example, its height can be 40nm, 45nm, 50nm or 55nm; of course, the first semiconductor layer 41 can also have other heights, which will not be listed here.

[0200] In some embodiments of this disclosure, the thickness of the first semiconductor layer 41 can be 2nm to 10nm. For example, the thickness of the first semiconductor layer 41 can be 2nm, 4nm, 6nm, 8nm or 10nm. Of course, the first semiconductor layer 41 can also have other thicknesses, which will not be listed here.

[0201] See also Figure 9 As shown, the material of the first semiconductor layer 41 can be a material with a relatively low dielectric constant, which helps to reduce parasitic capacitance. At the same time, while ensuring the turn-on voltage of the word line structure 100, the first semiconductor layer 41 can reduce the gate-induced drain leakage current (GIDL). For example, the material of the first semiconductor layer 41 can be polysilicon.

[0202] The second semiconductor layer 42 may be located on the surface of the first semiconductor layer 41. The first semiconductor layer 41 may surround the sidewalls and bottom surface of the second semiconductor layer 42, and the surface of the second semiconductor layer 42 may be flush with the top end of the first semiconductor layer 41. The material of the second semiconductor layer 42 may be the same as that of the first semiconductor layer 41. For example, both the second semiconductor layer 42 and the first semiconductor layer 41 may be made of polysilicon. The difference is that the doping concentration of the second semiconductor layer 42 may be greater than that of the first semiconductor layer 41, thereby giving the second semiconductor layer 42 a lower work function. This further improves the gate control capability of the word line structure 100, and further reduces the gate-induced drain leakage current (GIDL) by means of the second semiconductor layer 42 while ensuring the turn-on voltage of the word line structure 100.

[0203] For example, the second semiconductor layer 42 can be n-type doped. The n-type doping material can be an element located in Group V of the periodic table. For example, it can be phosphorus. Of course, it can also be other elements, which will not be listed here.

[0204] In some embodiments of this disclosure, phosphorus ions can be implanted into the second semiconductor layer 42 by ion implantation. Of course, other methods can also be used to perform n-type doping on the second semiconductor layer 42, and no special limitation is made here.

[0205] In some embodiments of this disclosure, forming the semiconductor layer 4 may include steps S510-S530, wherein:

[0206] Step S510: A conformally attached first semiconductor layer 41 is formed on the surface of the structure jointly formed by the substrate 1, the first dielectric layer 2, the conductive layer 3 and the second dielectric layer 5.

[0207] like Figure 19 As shown, for ease of manufacturing, the first semiconductor layer 41 can be formed simultaneously on the surface of the structure composed of the substrate 1, the first dielectric layer 2, the conductive layer 3, and the second dielectric layer 5. For example, the first semiconductor layer 41 can be formed in the word line trench 101 in which the conductive layer 3 and the first dielectric layer 2 are formed by electroplating, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or thermal evaporation. The first semiconductor layer 41 can be conformally attached to the sidewalls and bottom of the word line trench 101 in which the conductive layer 3 and the first dielectric layer 2 are formed.

[0208] In step S520, a second semiconductor layer 42 is formed on the surface of the first semiconductor layer 41, and the second semiconductor layer 42 fills the word line trench 101.

[0209] The second semiconductor layer 42 can be a thin film formed on the surface of the first semiconductor layer 41. It can be formed on the surface of the first semiconductor layer 41 by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. Of course, other methods can also be used to form the second semiconductor layer 42; no specific limitation is made here. It should be noted that, in order to accurately control the thickness of the semiconductor layer 4, the second semiconductor layer 42 can at least fill the word line trench 101 containing the first semiconductor layer 41. During this process, for ease of fabrication, the second semiconductor layer 42 can simultaneously cover the surface of the first semiconductor layer 41 located on top of the substrate 1, such as... Figure 20 As shown.

[0210] Step S530: The first semiconductor layer 41 and the second semiconductor layer 42 are etched back to form the semiconductor layer 4.

[0211] For example, a dry etching process can be used to etch back the first semiconductor layer 41 and the second semiconductor layer 42, thereby removing the first semiconductor layer 41 and the second semiconductor layer 42 located on top of the substrate 1. At the same time, a certain thickness of the first semiconductor layer 41 and the second semiconductor layer 42 can be retained in the word line trench 101. The remaining first semiconductor layer 41 and the second semiconductor layer 42 can be defined as semiconductor layer 4. In some embodiments, the thickness (or height) of the remaining first semiconductor layer 41 and the second semiconductor layer 42 in the depth direction of the word line trench 101 can be 40nm to 55nm. For example, the thickness of the remaining first semiconductor layer 41 and the second semiconductor layer 42 can be 40nm, 45nm, 50nm or 55nm. Of course, the remaining semiconductor material can also be of other thicknesses, which will not be listed here.

[0212] In some embodiments of this disclosure, during the etch-back process of the first semiconductor layer 41 and the second semiconductor layer 42, a portion of the first dielectric layer 2 located on the sidewall of the word line trench 101 can be removed. For example, during the etch-back process of the first semiconductor layer 41 and the second semiconductor layer 42, the first dielectric layer 2 located on the side of the semiconductor layer 4 away from the bottom of the word line trench 101 can be removed simultaneously, thereby making the top of the remaining first dielectric layer 2 flush with the top of the semiconductor layer 4.

[0213] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0214] Step S170: A second passivation layer 8 is formed on the surface of the semiconductor layer 4 away from the conductive layer 3. The second passivation layer 8 covers the top of the first dielectric layer 2 and the semiconductor layer 4.

[0215] See also Figure 2 As shown, the second passivation layer 8 can be a thin film or a coating formed on the surface of the semiconductor layer 4. No specific limitation is made on the specific form of the second passivation layer 8. The material of the second passivation layer 8 can be an insulating material. The second passivation layer 8 can provide insulation protection for the surface of the word line structure 100, which can prevent damage to the surface of the word line structure 100 caused by subsequent processes and reduce the possibility of coupling or short circuits between the word line structure 100 and other surrounding structures, thereby improving product yield.

[0216] The material of the second passivation layer 8 can be the same as or different from the material of the first passivation layer 7, and no special limitation is made here. For example, the material of the second passivation layer 8 can be silicon oxide or silicon nitride, and the second passivation layer 8 can be formed on the surface of the semiconductor layer 4 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation.

[0217] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0218] This disclosure also provides a memory, which may include the semiconductor structure in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and semiconductor structure formation method, and will not be repeated here.

[0219] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0220] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, including an active region having word line trenches therein; The first dielectric layer is conformally attached to the groove of the letter line; A conductive layer is located on the surface of the first dielectric layer and fills part of the word line trench. The end of the conductive layer away from the bottom of the word line trench has a predetermined gap with the first dielectric layer. A semiconductor layer is located on top of the preset gap and the conductive layer; A first gap surrounds the sidewall of the semiconductor layer; Furthermore, in the direction perpendicular to the extension direction of the character line groove, the size of the first gap is smaller than the size of the preset gap.

2. The semiconductor structure according to claim 1, characterized in that, In a direction perpendicular to the extension direction of the word line trench, the size of the top of the conductive layer is smaller than the size of the semiconductor layer.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The second dielectric layer is located within the preset gap, and the semiconductor layer covers the surfaces of the conductive layer and the second dielectric layer.

4. The semiconductor structure according to claim 3, characterized in that, The dielectric constant of the second dielectric layer is less than that of the first dielectric layer.

5. The semiconductor structure according to claim 3, characterized in that, The semiconductor layer includes a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer surrounds the sidewalls and bottom surface of the second semiconductor layer, and the doping concentration of the second semiconductor layer is greater than that of the first semiconductor layer.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an active region having word line trenches within the active region; A first conformally attached dielectric layer is formed within the groove of the letter line; A conductive layer is formed on the surface of the first dielectric layer, the conductive layer fills part of the word line trench, and a predetermined gap exists between the end of the conductive layer away from the bottom of the word line trench and the first dielectric layer; A semiconductor layer is formed on top of the conductive layer; The semiconductor layer is formed by: An insulating layer is formed, which fills the predetermined gap and at least covers the sidewalls of the word line groove and the top of the conductive layer; Remove the insulating layer located on top of the conductive layer; Deposit semiconductor material, the semiconductor material filling the remaining portion of the word line trench; The semiconductor material is etched back to form the semiconductor layer; Remove the remaining insulating layer to expose the predetermined gap, while simultaneously forming a first gap around the semiconductor layer.

7. The forming method according to claim 6, characterized in that, Forming the conductive layer includes: A conductive material layer is formed on the surface of the first dielectric layer; The conductive material layer is etched back to make the thickness of the conductive material layer located in the word line groove a preset thickness; Remove the material from the edge region of the conductive material layer at one end away from the bottom of the word line groove, and the remaining conductive material layer forms the conductive layer.

8. The forming method according to claim 6, characterized in that, The forming method further includes: A first passivation layer is formed on the surface of the semiconductor layer away from the conductive layer, and the first passivation layer seals the opening of the first gap.

9. The forming method according to claim 6 or 7, characterized in that, The forming method further includes: Before forming the semiconductor layer, a dielectric material is filled in the preset gap to form a second dielectric layer, the semiconductor layer covering the surfaces of the conductive layer and the second dielectric layer.

10. The forming method according to claim 9, characterized in that, Forming the second dielectric layer includes: A dielectric material is deposited on the surface of the structure formed by the substrate, the first dielectric layer, and the conductive layer, and the dielectric material fills the predetermined gap. Remove the dielectric material located outside the preset gap to form the second dielectric layer within the preset gap.

11. The forming method according to claim 10, characterized in that, Forming the semiconductor layer includes: A first semiconductor layer is formed conformally attached to the surface of the structure jointly formed by the substrate, the first dielectric layer, the conductive layer and the second dielectric layer; A second semiconductor layer is formed on the surface of the first semiconductor layer, and the second semiconductor layer fills the word line trench; The first semiconductor layer and the second semiconductor layer are etched back to form the semiconductor layer.

12. The forming method according to claim 11, characterized in that, When etching back the first semiconductor layer and the second semiconductor layer, a portion of the first dielectric layer located on the sidewall of the word trench is removed so that the top of the first dielectric layer located on the sidewall of the word trench is flush with the top of the semiconductor layer.

13. The forming method according to claim 12, characterized in that, The forming method further includes: A second passivation layer is formed on the surface of the semiconductor layer away from the conductive layer, and the second passivation layer covers the top of the first dielectric layer and the semiconductor layer.

14. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 1-5.

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