Suspended inductor structure and preparation method and application thereof

Abstract

The invention belongs to the field of semiconductor device manufacturing, and particularly discloses a suspended inductor structure and a preparation method and application thereof. The suspension inductor structure comprises two bases and an arc-shaped part, and the two bases are arranged in the horizontal direction; the two ends of the arc-shaped part are fixedly connected with the upper surfaces of the two bases correspondingly. An insulating layer is arranged on the upper surface of the chip substrate, and a mounting space is arranged in the insulating layer; the end parts of the base and the arc-shaped part are positioned in the mounting space; the base and the arc-shaped part are made of metal materials. When the formed suspension structure is applied to the intersection of two inductance metal wires, an insulating layer does not need to be plated between the two inductance metal wires, and the Q value of the chip inductor can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing, and relates to the fabrication of an integrated circuit on a chip, specifically to a suspended inductor structure, its fabrication method, and its application. Background Technology

[0002] In chip manufacturing, inductors are typically not fabricated separately. Instead, they are integrated into the circuit, manufactured simultaneously using the same materials and processes as the interconnects. Specifically, the interconnects in integrated circuits are inductive metal lines used to connect various components, formed during manufacturing through processes such as deposition and photolithography. Inductors, on the other hand, can be made into planar spiral or other coil structures. During manufacturing, the process design allows some interconnects to take on circular, square, or other coil shapes, thus creating the inductor.

[0003] When fabricating inductor wires, if two inductor wires cross, an insulating layer is typically deposited on the lower inductor wire, and then the second inductor wire is deposited on top of the insulating layer. This prevents the two inductor wires from contacting and short-circuiting. Insulating dielectrics (such as silicon dioxide and silicon nitride) generate dielectric polarization losses at high frequencies. Simultaneously, parasitic capacitances are formed between the coil and the substrate (silicon substrate), between the coil and adjacent metal layers, and between coil turns. These parasitic capacitances introduce capacitive losses and reduce the inductor's self-resonant frequency, increasing the proportion of capacitive components in the inductor's equivalent impedance within the target operating frequency band. This not only weakens the inductor's inductive characteristics but also increases energy loss due to capacitor charging and discharging, leading to a decrease in the inductor's Q value. Summary of the Invention

[0004] In view of the defects and deficiencies of the existing technology, the present invention provides, firstly, a suspended inductor structure; secondly, a method for preparing the suspended inductor structure; and thirdly, a chip.

[0005] In a first aspect, the present invention provides a suspended inductor structure, including a base and an arc-shaped portion, wherein two bases are provided and the two bases are arranged in a horizontal direction; the two ends of the arc-shaped portion are respectively fixedly connected to the upper surfaces of the two bases. An insulating layer is provided on the upper surface of the chip substrate, and an installation space is provided in the insulating layer; the ends of the base and the arc-shaped portion are both located in the installation space; Both the base and the arc-shaped portion are made of metal.

[0006] Preferably, the installation space includes a first hole and a second hole, the first hole and the second hole are connected, and the first hole is located below the second hole; The base is located in the first hole and is adapted to the first hole; the end of the arc-shaped portion is located in the second hole and is adapted to the second hole; The radial dimension of the second hole is smaller than that of the first hole.

[0007] More preferably, the first hole and the second hole are coaxially arranged.

[0008] Preferably, the metallic material is any one or more of Au, Ti, Pt, TiW alloy, Cu, Ni, Ge, Al, and Ag.

[0009] Secondly, the present invention provides a method for preparing a suspended inductor structure, comprising the following steps: Step 1: Deposit an insulating layer on the chip substrate, then coat the insulating layer with negative photoresist, and sequentially dry, expose, and develop to obtain negative photolithographic holes. Etch the insulating layer along the negative photolithographic holes to obtain two first holes. Step 2: Evaporate the metal layer, then remove the negative photoresist. The metal layer deposited in the first hole is the base. Step 3: Deposit an insulating layer again on the upper surface of the chip; coat the upper surface of the insulating layer with positive photoresist, then dry, expose, and develop to obtain a positive photolithography hole, and etch the insulating layer along the positive photolithography hole until the upper surface of the base below the insulating layer is exposed to obtain a second hole, and the photoresist supports the base. Step 4: Apply another layer of negative photoresist to the upper surface of the positive photoresist from Step 3, then dry, expose, and develop until the photoresist support base is exposed. Step 5: Evaporate the metal layer, then remove the negative photoresist, immerse the chip substrate in the photoresist remover solution, and remove the photoresist support base to obtain the suspended inductor structure.

[0010] Preferably, the material used to prepare the metal layer by vapor deposition in steps 2 and 6 is any one or more of Au, Ti, Pt, TiW alloy, Cu, Ni, Ge, Al, and Ag.

[0011] Preferably, mask one is used in the exposure process of step 1, mask two is used in the exposure process of step 3, and mask three is used in the exposure process of step 5; the light-transmitting area of ​​mask one overlaps with the light-transmitting area of ​​mask two; and the light-transmitting area of ​​mask three overlaps with the light-blocking area of ​​mask two.

[0012] Preferably, the center points of the light-transmitting areas of mask one and mask two overlap, and the size of the light-transmitting area of ​​mask one is larger than that of the light-transmitting area of ​​mask two.

[0013] Preferably, in step 5, the adhesive remover is any one or more of acetone, NMP, and IPA.

[0014] Thirdly, the present invention provides a chip comprising the above-described floating inductor structure or the floating inductor structure prepared by the above-described preparation method.

[0015] Compared with the prior art, one or more technical solutions provided by the present invention have one of the following beneficial effects: (1) The inductor structure provided by the present invention consists of a base and an arc-shaped part. When two inductor metal lines intersect in the chip, the floating structure provided by the present invention is applied to the intersection. The floating structure is formed on the upper inductor metal line to avoid short circuit. There is no need to set an insulating layer between the two inductor metal lines for separation. This can greatly reduce the interlayer parasitic capacitance and reduce capacitive loss, thereby improving the Q value of the chip inductor.

[0016] (2) The suspension structure provided by the present invention can be applied not only to the intersection of two inductive metal lines, but also to other parts, reducing the contact area between the inductive metal and the insulating layer of the chip, and further improving the Q value of the chip inductance.

[0017] (3) The inductor structure provided by the present invention can be applied to existing inductor design schemes without the need to design new inductor design schemes, thus avoiding additional chip fabrication costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an inductor metal structure in the prior art; Figure 2 This is a schematic diagram of the suspended inductor metal structure provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the inductor structure of the test chip of the present invention; Figure 4 Return loss test diagrams of the inductor structures provided in Example 2 and Comparative Example 1; Figure 5 Z-parameter test diagrams of the inductor structures provided in Example 2 and Comparative Example 1; Figure 6 An inductance sensing view of the inductor structure provided in Example 2 and Comparative Example 1; Figure 7 Q-value test diagrams for the inductor structures provided in Example 2 and Comparative Example 1.

[0019] Labeling explanation: 1. Metal layer; 2. Insulating layer; 3. Chip; 4. Base; 5. Curved part; 6. Mounting space; 601. First hole; 602. Second hole. Detailed Implementation

[0020] The present invention provides the following specific technical solutions.

[0021] In a first aspect, the present invention provides a suspended inductor structure, including a base and an arc-shaped portion, wherein two bases are provided and the two bases are arranged in a horizontal direction; the two ends of the arc-shaped portion are respectively fixedly connected to the upper surfaces of the two bases. An insulating layer is provided on the upper surface of the chip substrate, and an installation space is provided in the insulating layer; the ends of the base and the arc-shaped portion are both located in the installation space; Both the base and the arc-shaped portion are made of metal.

[0022] The inventors discovered through research that, in the existing technology for fabricating inductive metal wires, if two inductive metal wires intersect, see [reference needed]. Figure 1 Typically, an insulating layer is deposited on the lower inductor metal line (metal layer), and then a second inductor metal line (metal layer) is deposited on top of the insulating layer. This avoids short circuits caused by contact between the two inductor metal lines. The inductor structure built with metal layers, insulating layers, and metal layers not only weakens the inductive characteristics of the inductor, but also increases energy loss due to capacitor charging and discharging, resulting in a decrease in the Q value of the inductor.

[0023] Further research by the inventors revealed that the suspended inductor structure, through the interlocking and fixing of the base and the insulating layer mounting space, allows the arc-shaped portion to cross the two inductor metal lines in a suspended form, completely eliminating the insulating layer used in traditional solutions to separate the two metal lines. On the one hand, the removal of the insulating layer weakens the dielectric loss caused by dielectric polarization under high-frequency operating conditions to a certain extent, significantly reduces interlayer parasitic capacitance, avoids the interference of capacitive components on the inductor's equivalent impedance, and effectively improves the inductor's self-resonant frequency and energy storage efficiency. On the other hand, the integrated molding of the arc-shaped portion and the base ensures the continuity of the conductive path and reduces interface contact loss due to the absence of an insulating layer, thus lowering the overall equivalent resistance. In addition, the suspended configuration reduces the contact area between the inductor and the silicon substrate, weakens substrate eddy current losses, and the symmetrical design of the base enhances the structural mechanical stability, adapting to the space constraints of high-density chip integration, achieving a dual breakthrough in inductor performance and chip process compatibility.

[0024] Preferably, the installation space includes a first hole and a second hole, the first hole and the second hole are connected, and the first hole is located below the second hole; The base is located in the first hole and is adapted to the first hole; the end of the arc-shaped portion is located in the second hole and is adapted to the second hole; The radial dimension of the second hole is smaller than that of the first hole.

[0025] Through research, the inventors discovered that the projected area of ​​the second hole is smaller than that of the first hole, which can help to position the inductor structure, reduce the possibility of the base falling off, and improve the stability of the inductor structure.

[0026] More preferably, the first hole and the second hole are coaxially arranged.

[0027] Through research, the inventors discovered that the vertical cross-section of the first and second holes is shaped like a "⊥", which can limit the base from multiple angles and further improve the stability of the inductor structure.

[0028] Preferably, the metallic material is any one or more of Au, Ti, Pt, TiW alloy, Cu, Ni, Ge, Al, and Ag.

[0029] Secondly, the present invention provides a method for preparing a suspended inductor structure, comprising the following steps: Step 1: Deposit an insulating layer on the chip substrate, then coat the insulating layer with negative photoresist, and sequentially dry, expose, and develop to obtain negative photolithographic holes. Etch the insulating layer along the negative photolithographic holes to obtain two first holes. Step 2: Evaporate the metal layer, then remove the negative photoresist. The metal layer deposited in the first hole is the base. Step 3: Deposit an insulating layer again on the upper surface of the chip; coat the upper surface of the insulating layer with positive photoresist, then dry, expose, and develop to obtain a positive photolithography hole, and etch the insulating layer along the positive photolithography hole until the upper surface of the base below the insulating layer is exposed to obtain a second hole, and the photoresist supports the base. Step 4: Apply another layer of negative photoresist to the upper surface of the positive photoresist from Step 3, then dry, expose, and develop until the photoresist support base is exposed. Step 5: Evaporate the metal layer, then remove the negative photoresist, immerse the chip substrate in the photoresist remover solution, and remove the photoresist support base to obtain the suspended inductor structure.

[0030] Through research, the inventors discovered that the fabrication method for this suspended inductor structure possesses significant advantages in process adaptability and performance optimization. The overall solution is highly compatible with traditional chip manufacturing processes, relying entirely on mature standard processes such as coating, exposure, development, and evaporation. No additional specialized equipment is required, allowing seamless integration into chip mass production processes, effectively controlling production line modification costs and ensuring production yield. Its core lies in achieving precise molding through differentiated, step-by-step application of positive and negative photoresists: first, a negative photoresist is used in conjunction with an etching process to create the first hole, in which a base is deposited. Then, positive photoresist is used to construct a photoresist support base, and in conjunction with an etching process, a second hole is obtained. Afterward, negative photoresist is coated to cover areas where deposition is unnecessary, and the photoresist is removed after the arc-shaped portion is deposited. This process precisely ensures the molding accuracy and structural mechanical stability of the base and arc-shaped portion, while eliminating the need for an insulating layer at the traditional intersection, reducing dielectric loss and interlayer parasitic capacitance caused by the insulating layer. Simultaneously, it significantly reduces substrate eddy current loss and interface contact loss, ultimately achieving a dual improvement in inductor Q-value and integration adaptability.

[0031] In step 1, the resulting negative photoresist aperture is trapezoidal, narrower at the top and wider at the bottom. The metal layer deposited in step 2 is deposited on the chip surface through the narrower entrance at the top of the photoresist aperture, forming the base of the floating inductor structure. In step 3, the positive photoresist coated is dried, exposed, and developed to form an inverted trapezoid. The insulating layer is etched along the positive photoresist aperture, exposing part or all of the upper surface of the base. Then, a photoresist support base for the deposition of the arc-shaped portion is built on the surface of the insulating layer. The photoresist support base is located between the two second apertures. After step 4, a layer of negative photoresist is coated, dried, exposed, and developed. The resulting negative photoresist aperture exposes the photoresist support base, and the negative photoresist covers the areas where no metal layer needs to be deposited. Then, in step 5, metal is vapor-deposited. The metal is deposited on the surface of the photoresist support base and in the second aperture, forming the arc-shaped portion. The arc-shaped portion deposited in step 6 and the base deposited in step 2 together form the floating inductor structure. Finally, the chip is placed in the resist stripping solution to peel off the residual photoresist on the surface of the insulating layer.

[0032] In actual production, the process parameters for drying, exposing, developing, depositing metal layers, and depositing insulating layers of the photoresist can be adjusted according to actual production conditions. Different chips have different inductor designs. When using the floating inductor structure provided by this invention, the distance between the two first holes in step 1, and the length, width, and thickness of the photoresist support base obtained in step 6 are all designed according to actual requirements.

[0033] Preferably, the material used to prepare the metal layer by vapor deposition in steps 2 and 7 is any one or more of Au, Ti, Pt, TiW alloy, Cu, Ni, Ge, Al, and Ag.

[0034] Preferably, mask one is used in the exposure process of step 1, mask two is used in the exposure process of step 3, mask three is used in the exposure process of step 4, and mask four is used in the exposure process of step 5; the light-transmitting area of ​​mask one overlaps with the light-transmitting area of ​​mask two; the light-transmitting area of ​​mask three overlaps with the light-blocking area of ​​mask two; and the light-transmitting area of ​​mask four overlaps with the light-blocking area of ​​mask three.

[0035] Preferably, the center points of the light-transmitting areas of mask one and mask two overlap, and the size of the light-transmitting area of ​​mask one is larger than that of the light-transmitting area of ​​mask two.

[0036] In actual production, depending on the application of the chip, the structure of the inductor is different. When preparing a floating inductor, the shape of the light-transmitting area of ​​the mask can be designed according to the requirements.

[0037] Preferably, in step 6, the adhesive remover is any one or more of acetone, NMP, and IPA.

[0038] Thirdly, the present invention provides a chip comprising the above-described floating inductor structure or the floating inductor structure prepared by the above-described preparation method.

[0039] To make the technical problems, technical solutions and technical advantages of the present invention clearer, a detailed description will be given below with reference to specific examples. However, the scope of protection of the present invention is not limited to the following specific embodiments.

[0040] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the invention.

[0041] Unless otherwise specified, all raw materials, reagents, instruments and equipment used in this invention can be purchased from the market or prepared by existing methods.

[0042] Example 1: A suspended inductor structure, reference Figure 2 The floating inductor structure includes a base 4 and an arc-shaped part 5. There are two bases 4, and the two bases 4 are arranged in a horizontal direction. The two ends of the arc-shaped part 5 are fixedly connected to the upper surfaces of the two bases 4 respectively, and the concave surface of the arc-shaped part 5 faces the base 4.

[0043] An insulating layer 2 is provided on the upper surface of the chip 3 substrate, and an installation space 6 is provided in the insulating layer 2. The installation space 6 includes a first hole 601 and a second hole 602, which are connected. The base 4 is located in the first hole 601 and is adapted to the first hole 601. The connecting part is located in the second hole 602 and is adapted to the second hole 602. The radial dimension of the second hole 602 is smaller than the orthographic projection area of ​​the first hole 601. The first hole 601 and the second hole 602 are coaxially arranged, and the vertical cross-section of the first hole 601 and the second hole 602 are generally "⊥" shaped, which can limit the inductor structure, reduce the possibility of the base 4 falling off, and improve the stability of the inductor structure.

[0044] Both the base 4 and the arc-shaped part 5 are made of metal.

[0045] Example 2: A method for preparing a suspended inductor structure includes the following steps: Step 1: Deposit an insulating layer on the chip substrate, then coat it with negative photoresist, followed by drying, exposure, and development to obtain negative photolithographic holes. The negative photolithographic holes have a trapezoidal structure that is narrower at the top and wider at the bottom. Etch the insulating layer along the negative photolithographic holes to obtain two first holes. There are two first holes, located on both sides of the inductor metal line that needs to be crossed.

[0046] Step 2: Evaporate a metal layer using Au as the evaporation material. The metal layer is deposited in the first hole through a narrow entrance at the top of the photolithography hole to form the base of the suspended inductor structure; then remove the negative photoresist.

[0047] Step 3: Deposit another insulating layer on the surface of the insulating layer deposited in Step 1, then coat with a layer of positive photoresist, followed by drying, exposure, and development to obtain a positive photolithographic hole. The positive photolithographic hole has an inverted trapezoidal structure that is wider at the top and narrower at the bottom. Etch the insulating layer along the positive photolithographic hole to expose the upper surface of the base, obtaining a second hole. The second hole is coaxial with the first hole, and the radius of the second hole is smaller than that of the first hole. The positive photoresist between the two second holes, located on the upper surface of the insulating layer, forms a support base. The centerline of the photoresist support base in the longitudinal direction overlaps with the line connecting the two first holes. The photoresist support base provides support for the subsequent deposition and fabrication of the arc-shaped portion. Step 4: Apply another layer of negative photoresist to the upper surface of the positive photoresist from Step 3, then dry, expose, and develop to expose the photoresist support base obtained in Step 4. The undissolved negative photoresist after development will cover areas where no metal layer needs to be deposited.

[0048] Step 5: Au metal material is deposited again. The metal layer is deposited on the upper surface of the second hole and the photoresist support base, that is, the arc-shaped part is deposited. The arc-shaped part and the base together form a floating inductor structure.

[0049] Step 6: Remove the negative photoresist by peeling off the photoresist, then immerse the chip substrate in the photoresist remover solution to peel off the remaining photoresist, thus obtaining the suspended inductor structure.

[0050] Comparative Example 1: A method for fabricating an inductor structure includes the following steps: Step 1: Coat a negative photoresist onto the chip substrate, then dry, expose, and develop to obtain photolithographic holes.

[0051] Step 2: Evaporate a metal layer using Au as the evaporation material. The metal layer is deposited on the chip surface through the entrance of the photolithography hole, and then the negative photoresist is removed. The metal layer forms an inductor structure.

[0052] Step 3: When two inductor metal lines intersect in the inductor structure, first coat the upper surface of the inductor structure with negative photoresist, then dry, expose, and develop to create photolithographic holes at the intersection. Then deposit an insulating layer, followed by a metal layer, and finally strip away the negative photoresist to obtain the final product.

[0053] Provide a test chip, the structure of which is as follows: Figure 3 As shown, the inductor wires in the chip are arranged in a spiral shape, with 4 turns, a linewidth of 11 μm, a spacing of 5 μm between adjacent turns, and an outer diameter of 125 μm for the outermost inductor wire. The white-framed portion represents the overlapping area of ​​two inductor wires. A floating inductor structure was fabricated at the intersection of two inductor wires using the method provided in Example 2, allowing the floating inductor to simultaneously span four inductor wires, resulting in Sample 1. An inductor structure was also fabricated at the intersection of two inductor wires using the method provided in Comparative Example 1, depositing an insulating layer on the four inductor wires, followed by the deposition of a second layer of inductor wires, resulting in Sample 2. Performance tests were then performed on Sample 1 and Sample 2.

[0054] Figure 4 The return loss test diagrams for Sample 1 and Sample 2 are provided by... Figure 4 It can be seen that within the test frequency band of 0~18GHz, the return loss curves of Sample 1 and Sample 2 show a high degree of consistency, especially in the low-frequency range (<2GHz), where their values ​​are completely identical (both -2.0dB). Entering the mid-to-high frequency range, although the curves show slight fluctuations, the trends in return loss are highly synchronized, and the numerical differences remain extremely small, with no performance differentiation. Overall, the impedance matching performance of Sample 1 and Sample 2 in this frequency band is basically consistent.

[0055] Figure 5 The Z-parameter test plots for sample 1 and sample 2 are provided by... Figure 5It can be seen that in the 0~10GHz frequency band, the Z-parameter curves of the two are closely matched, and the impedance characteristic change trend is basically the same; in the 4~11GHz frequency band, the impedance characteristic of sample two is better; in the high-frequency band of 11~17GHz, the impedance characteristic of sample one is better.

[0056] Figure 6 For the inductance attempts of Sample 1 and Sample 2, by Figure 6 It can be seen that within the 0~14GHz frequency band, the inductance value of Sample 1 remains basically stable (close to 0H), while the inductance value of Sample 2 shows slight fluctuations. Entering the 14~16GHz high-frequency band, the inductance value of Sample 1 changes drastically, reaching 109.915H at 15.95GHz (m1), dropping to 5.507H at 16.02GHz (m2), and then becoming -118.264H at 16.12GHz (m3), exhibiting dramatic fluctuations. This indicates that Sample 1 can achieve significant changes in inductance at high frequencies, demonstrating good dynamic inductance adjustment capabilities in this range.

[0057] Figure 7 The Q-value test plots for Sample 1 and Sample 2 are provided by... Figure 7 It can be seen that in the 100MHz low-frequency band, the Q values ​​of Sample 1 and Sample 2 are both low and similar; in the 6GHz mid-frequency band, the Q value of Sample 1 rises to 14.186, significantly higher than that of Sample 2; entering the 15GHz high-frequency band (m7), the Q value of Sample 1 remains at 7.876, still better than Sample 2, while the Q value of Sample 2 drops sharply. Sample 1 has a better Q value performance across the entire frequency band, and is significantly better than Sample 2 in the mid-to-high frequency bands, indicating that the floating inductor structure provided by this invention has lower energy loss, better energy storage and frequency selection performance, and better overall performance in inductor structures.

[0058] The above-described embodiments are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope of the present invention, based on the technical solution and concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A suspended inductor structure, characterized in that, The floating inductor structure includes a base (4) and an arc-shaped part (5). There are two bases (4), and the two bases (4) are arranged in a horizontal direction. The two ends of the arc-shaped part (5) are fixedly connected to the upper surfaces of the two bases (4) respectively. An insulating layer (2) is provided on the upper surface of the chip (3) substrate, and an installation space (6) is provided in the insulating layer (2); the base (4) is located in the installation space (6), and the end of the arc-shaped part (5) is also located in the installation space (6); Both the base (4) and the arc-shaped part (5) are made of metal.

2. The suspended inductor structure as described in claim 1, characterized in that, The installation space (6) includes a first hole (601) and a second hole (602), the first hole (601) and the second hole (602) are connected, and the first hole (601) is located below the second hole (602); The base (4) is located in the first hole (601) and is adapted to the first hole (601); the end of the arc-shaped part (5) is located in the second hole (602) and is adapted to the second hole (602); The radial dimension of the second hole (602) is smaller than that of the first hole (601).

3. The suspended inductor structure as described in claim 2, characterized in that, The first hole (601) and the second hole (602) are coaxially arranged.

4. The suspended inductor structure as described in claim 1, characterized in that, The metallic material is any one or more of Au, Ti, Pt, TiW alloy, Cu, Ni, Ge, Al, and Ag.

5. A method for preparing a suspended inductor structure, characterized in that, Includes the following steps: Step 1: Deposit an insulating layer on the chip substrate, then coat the insulating layer with negative photoresist, and sequentially dry, expose, and develop to obtain negative photolithographic holes. Etch the insulating layer along the negative photolithographic holes to obtain two first holes. Step 2: Evaporate the metal layer, then remove the negative photoresist. The metal layer deposited in the first hole is the base. Step 3: Deposit an insulating layer again on the upper surface of the chip; coat the upper surface of the insulating layer with positive photoresist, then dry, expose, and develop to obtain a positive photolithography hole, and etch the insulating layer along the positive photolithography hole until the upper surface of the base below the insulating layer is exposed to obtain a second hole, and the photoresist supports the base. Step 4: Apply another layer of negative photoresist to the upper surface of the positive photoresist from Step 3, then dry, expose, and develop until the photoresist support base is exposed. Step 5: Evaporate the metal layer, then remove the negative photoresist, immerse the chip substrate in the photoresist remover solution, and remove the photoresist support base to obtain the suspended inductor structure.

6. The method for preparing the suspended inductor structure as described in claim 5, characterized in that, The materials used to prepare the metal layer by vapor deposition in steps 2 and 5 are any one or more of Au, Ti, Pt, TiW alloy, Cu, Ni, Ge, Al, and Ag.

7. The method for preparing the suspended inductor structure as described in claim 5, characterized in that, Mask 1 is used in the exposure process of step 1, mask 2 is used in the exposure process of step 3, and mask 3 is used in the exposure process of step 5. The light-transmitting area of ​​mask 1 overlaps with the light-transmitting area of ​​mask 2; the light-transmitting area of ​​mask 3 overlaps with the light-blocking area of ​​mask 2.

8. The method for preparing the suspended inductor structure as described in claim 7, characterized in that, The center points of the light-transmitting areas of mask one and mask two overlap, and the size of the light-transmitting area of ​​mask one is larger than that of the light-transmitting area of ​​mask two.

9. The method for preparing the suspended inductor structure as described in claim 5, characterized in that, In step 5, the adhesive remover is any one or more of acetone, NMP, and IPA.

10. A chip, characterized in that, Includes the suspended inductor structure according to any one of claims 1 to 4 or the suspended inductor structure prepared by the preparation method according to any one of claims 5 to 9.

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