Ceramic substrate structure and integrated package structure thereof

Abstract

The application provides a ceramic substrate structure and an integrated packaging structure thereof, and belongs to the technical field of packaging. The ceramic substrate structure comprises a substrate plate body, a large chip and a small chip. The upper surface of the substrate plate body is provided with a first groove and a plurality of pads, and the lower surface is provided with a second groove. The first groove is communicated with the groove bottom surface of the second groove. A plurality of metal wires are arranged in the second groove. The metal wires are electrically connected with the pads through a via technology. The large chip is fixedly connected to the top surface of the substrate plate body, and the small chip is fixedly connected in the second groove. The large chip, the small chip and the metal wires are electrically connected through wire bonding. Through the double-sided groove structure and the multi-level electrical connection scheme, the double-sided packaging of the chip is realized, the signal transmission path is effectively shortened, the packaging size is reduced, the heat dissipation efficiency and the electrical performance are significantly improved, and the application is particularly suitable for high-performance chip packaging applications such as back incidence detectors and other double-sided electrical connection applications.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and in particular to a ceramic substrate structure and its integrated packaging structure. Background Technology

[0002] Chip packaging technology is a crucial step in the semiconductor manufacturing process. Its core function is to provide stable electrical connections, reliable physical protection, effective heat dissipation paths, and standardized external interfaces for fragile bare chips. The packaging structure not only ensures signal and power transmission between the chip and external circuit systems, but also determines the mechanical strength, environmental adaptability, and overall size of the final electronic components. It is the foundation for the miniaturization, high-density integration, and high performance of modern electronic products.

[0003] Among current mainstream packaging technologies, single-sided wire bonding (also known as wire bonding) is one of the most widely used interconnection solutions. This process typically uses gold or copper wires and employs thermo-pressing, ultrasonic, or thermo-ultrasonic energy to connect the chip's front-side pads to corresponding solder points on the carrier substrate (such as leadframes, ceramic substrates, or organic substrates) point by point. Subsequently, the wires on the substrate guide electrical signals to the pins or solder balls of the package, thereby achieving system integration with the printed circuit board. This process is widely used for packaging various low-to-medium pin count chips due to its mature technology, low cost, and high adaptability.

[0004] However, traditional single-sided wire bonding packaging structures have significant inherent drawbacks, becoming a bottleneck restricting further miniaturization and high performance of products. Firstly, in terms of spatial layout, all interconnects must be led out from a single chip surface and undergo an "upward-outward" arc wiring process. This inevitably occupies the three-dimensional space on the sides and top of the chip, resulting in an overall package size much larger than the bare chip itself, making it difficult to meet the increasingly urgent demands for ultra-compact packaging in consumer electronics, portable devices, and other fields. Secondly, in terms of thermal management, this structure suffers from low heat dissipation efficiency. The heat generated during chip operation mainly relies on its back side or through a limited number of wire bonding points to be transferred to the substrate, resulting in relatively narrow heat dissipation channels and high thermal resistance. If heat cannot be dissipated in time, the chip junction temperature will rise rapidly, leading to a series of problems such as performance degradation, shortened lifespan, and decreased reliability. The thermal stress caused by high temperatures may also damage the internal structure of the chip and the integrity of the bonding points, especially in applications with high heat generation such as power devices or photodetectors, where this contradiction is more pronounced. Summary of the Invention

[0005] This invention provides a ceramic substrate structure and its integrated packaging structure. It solves the technical problems of low space utilization and poor heat dissipation caused by defects in existing chip packaging structures and processes. The technical solution is as follows:

[0006] In a first aspect, embodiments of the present invention provide a ceramic substrate structure, including a substrate body, a large chip, and a small chip.

[0007] The upper surface of the substrate is provided with a first groove and a plurality of pads, which are arranged around the edge of the substrate. The lower surface of the substrate is provided with a second groove, which is connected to the bottom surface of the second groove. A plurality of metal wires are provided in the second groove corresponding to the plurality of pads. The metal wires are electrically connected to the corresponding pads through through-hole technology. The large chip is fixedly connected to the top surface of the substrate, and the small chip is fixedly connected to the second groove. The large chip, the small chip, and the metal wires are electrically connected by wire bonding.

[0008] Optionally, the substrate is provided with a plurality of metal conduit matrices. The metal conduit matrix includes matrix protrusions that protrude from the upper and lower surfaces of the substrate. Multiple conduits are provided through the matrix protrusions in a direction perpendicular to the substrate. The large chip is attached to the top surface of the matrix protrusions by thermally conductive adhesive.

[0009] Optionally, the metal conduit matrix is ​​provided in four parts, and arranged in a rectangular array around the first groove.

[0010] Optionally, the diameter of the catheter ranges from 0.1 to 1 mm.

[0011] Optionally, the depth of the first groove ranges from 0.2 to 100 mm, and the depth of the second groove ranges from 0.5 to 100 mm.

[0012] Optionally, the substrate is in the shape of a regular polygon or a circle, and the substrate is made of aluminum oxide or aluminum nitride.

[0013] Secondly, embodiments of the present invention provide an integrated packaging structure, including the ceramic substrate structure described in the first aspect, and further including a lead base and a semiconductor cooler. The semiconductor cooler is located below the substrate, the cold end of the semiconductor cooler is connected to the lower surface of the substrate, the hot end of the semiconductor cooler is connected to the lead base, a plurality of lead posts matching the pads are disposed through the lead base, and a heat-conducting post is disposed at the bottom of the lead base.

[0014] Optionally, a plurality of the lead posts are arranged circumferentially around the thermoelectric cooler.

[0015] Optionally, a ceramic tube is provided on the lead base, and the lead post passes through the ceramic tube.

[0016] Optionally, it also includes a cylindrical shell with a cap on the top. The large chip is a back-illuminated APD device. The cap has a light-transmitting area corresponding to the large chip. The shell is placed on the lead base and the cap covers the substrate and the lead post.

[0017] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0018] In terms of electrical performance, this invention achieves double-sided electrical connection between a large chip and a small chip by setting a first groove and a second groove that are interconnected on the upper and lower surfaces of the substrate. The large chip is fixed to the upper surface of the substrate, and the small chip is fixed in the second groove on the lower surface. The two are connected by wire bonding through the interconnected groove structure, which significantly shortens the signal transmission path. Compared with the traditional single-sided wire bonding process, the signal no longer needs to go around the edge of the substrate, but can be directly connected through the shortest path. This effectively reduces the parasitic inductance and parasitic capacitance of the interconnect wires, reduces signal delay and distortion, and improves signal transmission speed and signal integrity.

[0019] In terms of space utilization, this invention breaks through the planar layout limitations of traditional single-sided packaging, making full use of the upper and lower surface space of the substrate. By distributing chips with different functions on both sides of the substrate and using a recessed structure for a three-dimensional layout, the overall package area is significantly reduced while ensuring electrical connectivity. The second recess provides dedicated mounting space for smaller chips, preventing them from competing with larger chips for wiring resources on the same plane, thereby improving chip integration density.

[0020] Regarding heat dissipation performance, this invention incorporates a matrix of metal conduits on the substrate. Each metal conduit matrix includes matrix protrusions extending from the upper and lower surfaces of the substrate, with multiple conduits running through each protrusion. The large chip is directly attached to the top surface of the matrix protrusions using thermally conductive adhesive. Heat generated during operation is rapidly transferred to the matrix protrusions via the thermally conductive adhesive, and then reaches the lower surface of the substrate via the shortest path through the through-hole metal conduits. Due to the excellent thermal conductivity of the metal conduits and their matrix distribution forming multiple parallel heat dissipation channels, thermal resistance is significantly reduced, and heat dissipation efficiency is greatly improved. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1This is a schematic diagram of the structure of the upper surface of the substrate provided in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of the lower surface of the substrate provided in an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the lower surface of the ceramic substrate structure provided in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the integrated packaging structure provided in an embodiment of the present invention;

[0026] Figure 5 This is an exploded view of the integrated packaging structure provided in the embodiments of the present invention;

[0027] Figure 6 This is a schematic diagram of the integrated packaging structure provided in this embodiment of the invention after the casing is applied.

[0028] In the diagram: 1-Substrate; 2-Large chip; 3-Small chip; 4-Lead base; 5-Cooler; 6-Shell; 11-First groove; 12-Pad; 13-Second groove; 14-Metal wire; 15-Metal conduit matrix; 41-Lead post; 42-Heat conduction post; 43-Ceramic tube; 61-Cap; 62-Light-transmitting area; 151-Matrix protrusion; 152-Conduit. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the structure of the upper surface of the substrate provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the lower surface of the substrate provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the lower surface of the ceramic substrate structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the integrated packaging structure provided in an embodiment of the present invention; Figure 5 This is an exploded view of the integrated packaging structure provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of the integrated packaging structure provided in an embodiment of the present invention after the casing is applied. Figures 1 to 3 As shown, an embodiment of the present invention provides a ceramic substrate structure, including a substrate body 1, a large chip 2, and a small chip 3.

[0031] The substrate 1 has a first groove 11 and multiple pads 12 on its upper surface. The pads 12 are arranged around the edge of the substrate 1. The substrate 1 has a second groove 13 on its lower surface. The first groove 11 is connected to the bottom surface of the second groove 13. Multiple metal wires 14 are arranged in the second groove 13 corresponding to the pads 12. The metal wires 14 are electrically connected to the corresponding pads 12 through through-hole technology. The large chip 2 is fixedly connected to the top surface of the substrate 1. The small chip 3 is fixedly connected to the second groove 13. The large chip 2, the small chip 3 and the metal wires 14 are electrically connected by wire bonding.

[0032] In this embodiment of the invention, the first groove 11 is located in the central region of the upper surface of the substrate 1 and is circular in shape. A second groove 13 is provided on the lower surface of the substrate 1, corresponding to the position of the first groove 11 on the upper surface, but in a square shape. The square second groove 13 on the lower surface is more suitable for arranging multiple small rectangular or square chips 3 and related circuit structures, facilitating the regular arrangement of metal wires 14 and wire bonding operations. In the thickness direction of the substrate 1, the first groove 11 extends downwards to a certain depth and then meets and connects with the second groove 13 extending upwards from the lower surface, forming a vertically connected cavity structure. This allows for extremely short-distance wire bonding connections between the large chip 2 located on the upper surface of the substrate and the small chip 3 located in the second groove 13 on the lower surface through this connecting area.

[0033] Multiple metal wires 14 are disposed within the second groove 13 corresponding to multiple pads 12. One end of each metal wire 14 is located at the bottom or sidewall of the second groove 13, and the other end is electrically connected to the corresponding pad 12 on the upper surface through a metallized via inside the substrate 1. The metal wires 14 are electrically connected to the corresponding pads 12 via a via technology, which is specifically implemented using a metallized via process: first, through holes are formed on the ceramic substrate by laser drilling or mechanical drilling, and then a conductive metal layer such as copper or gold is deposited on the hole wall to form a reliable electrical path. The metal wires 14 are made of highly conductive materials such as gold, copper, or aluminum, and their wiring paths are optimized to ensure electrical performance while reserving sufficient space for the installation and bonding of the small chip 3 within the second groove 13.

[0034] The large chip 2 is fixedly connected to the top surface of the substrate 1. Specifically, the large chip 2 is attached to the top surface of the substrate 1 using adhesive materials such as thermally conductive adhesive or eutectic solder and covers the first groove 11. The large chip 2 is typically a back-incident avalanche photodiode (APD), charge-coupled device (CCD), or other photodetector. One of its main electrodes, such as the anode, is located on the side facing the opening of the first groove 11, preparing for subsequent wire bonding connection with the small chip 3 or the metal wire 14.

[0035] Small chips 3 are fixedly connected within the second recess 13, and there can be one or more. Small chips 3 may include auxiliary functional modules such as temperature sensors, electronic amplifiers, analog-to-digital converters, and signal processing chips. These small chips 3 are mounted on the surface of the metal wires 14 within the second recess 13 or on the metallization layer at the bottom of the recess using processes such as conductive adhesive, eutectic bonding, or silver paste, achieving both mechanical fixation and partial electrical connection. The placement of small chips 3 enables the entire package structure to have more complete functions. For example, the temperature sensor can monitor the operating temperature of the large chip 2 in real time, and the amplifier chip can amplify the weak signal output by the large chip 2. The integration of these functions avoids signal attenuation and interference problems caused by long-distance external wiring.

[0036] Electrical connections between the large chip 2, the small chip 3, and the metal wire 14 are achieved via wire bonding, a crucial process step for realizing the electrical interconnection of the entire package structure. Wire bonding typically uses gold or aluminum wires, utilizing ultrasonic energy and pressure to form reliable intermetallic compound bonding points on the bonding pads of the large chip 2, the bonding pads of the small chip 3, and the surface of the metal wire 14. The specific bonding path includes: the signal output terminal of the large chip 2 is connected to the signal input terminal of the small chip 3 via gold wire bonding. Utilizing the interconnection structure between the first groove 11 and the second groove 13, the gold wire can complete the connection between the upper and lower layers in a very short distance, with the wire length controlled to within 2mm, far shorter than the 10mm or even longer connections required in traditional packaging that need to wrap around the substrate edge; the output terminal or power pin of the small chip 3 is connected to the metal wire 14 within the second groove 13 via gold wire bonding; the metal wire 14 is then connected to the pad 12 on the upper surface of the substrate 1 through vias; the pad 12 is finally connected to the external circuitry of the package via external lead posts. This multi-layered, short-path interconnection scheme significantly reduces electrical parasitic parameters and improves the electrical performance and signal integrity of the system.

[0037] When this ceramic substrate structure is in operation, if the large chip 2, such as a back-illuminated APD device, receives an optical signal, photons enter through the light-transmitting area 62 of the cover 61, penetrate the back of the large chip 2, and enter the photosensitive area, generating a photocurrent. This current signal is output from the front electrode of the large chip 2 and directly transmitted to the small chip 3, such as an electronic amplifier, located in the second groove 13 through extremely short wire bonding for signal amplification and processing. The processed signal is then bonded to the metal wire 14 through the small chip 3, reaches the pad 12 on the upper surface through the through-hole, and is finally output to the external circuit through the lead post 41. The entire signal link is compact and efficient, with extremely low signal delay and minimal noise interference. At the same time, the heat generated by the large chip 2 during operation can be quickly conducted downwards through the thermally conductive adhesive and the substrate 1, and actively dissipated through the cooler structure, keeping the chip operating within its optimal operating temperature range.

[0038] This embodiment achieves, for the first time, ultra-short-distance double-sided electrical interconnection between large chip 2 and small chip 3 through an innovative structural design in which the first groove 11 on the substrate 1 and the second groove 13 on the lower surface are interconnected, breaking through the space limitations and electrical performance bottlenecks of traditional single-sided wire bonding process.

[0039] Optionally, a plurality of metal conduit matrices 15 are disposed on the substrate 1. Each metal conduit matrix 15 includes matrix protrusions 151 protruding from the upper and lower surfaces of the substrate 1. Multiple conduits 152 are disposed through the matrix protrusions 151 in a direction perpendicular to the substrate 1. The large chip 2 is attached to the top surface of the matrix protrusions 151 using thermally conductive adhesive. Exemplarily, in this embodiment of the invention, each metal conduit matrix 15 includes matrix protrusions 151 protruding from the upper and lower surfaces of the substrate 1. The matrix protrusions 151 are boss-shaped, with their upper end protruding from the upper surface of the substrate 1 and their lower end protruding from the lower surface of the substrate 1. The matrix protrusions 151 are made of a high thermal conductivity metal material, such as copper, aluminum, or their alloys, or a metal-ceramic composite material can be used to balance thermal conductivity and thermal expansion coefficient matching. Multiple conduits 152 are arranged through the matrix bump 151 along a direction perpendicular to the substrate 1. These conduits 152 are arranged in a regular array, and each conduit 152 is a cylindrical through-hole with a diameter between 0.1 mm and 1 mm. The through-hole design of the conduits 152 allows heat to penetrate the substrate 1 directly along the shortest path. Compared with the traditional method where heat needs to diffuse laterally inside the ceramic substrate and then be transferred downwards, the thermal conductivity is significantly improved. The large chip 2 is attached to the top surface of the matrix bump 151 with thermally conductive adhesive. The thermally conductive adhesive not only provides reliable mechanical fixation, but more importantly, it establishes a low thermal resistance thermal conduction channel between the large chip 2 and the matrix bump 151. The heat generated by the large chip 2 during operation is first transferred to the thermally conductive adhesive, then quickly enters the metal body of the matrix bump 151, and then is conducted at high speed along the multiple conduits 152 in parallel to the lower surface of the substrate 1. The protruding design of the matrix bump 151 maintains a certain distance between the large chip 2 and the main body of the substrate 1, avoiding the local stress concentration problem that may occur when the chip is directly mounted on the planar substrate. Meanwhile, the array distribution of multiple heat pipes 152 forms a uniform heat dissipation network, allowing heat to be transferred downwards from various areas of the large chip 2 simultaneously, avoiding the problems of heat accumulation and excessive temperature gradient that may occur with a single heat dissipation channel.

[0040] Optionally, four metal conduit matrices 15 are provided and arranged in a rectangular array around the first groove 11. Exemplarily, in this embodiment of the invention, four metal conduit matrices 15 are provided and arranged in a rectangular array around the first groove 11. Specifically, these four metal conduit matrices 15 are located at the four corner regions of the substrate 1, and with the center of the first groove 11 as a reference point, the four metal conduit matrices 15 are centrally symmetrically distributed about this center point. The lines connecting two adjacent metal conduit matrices 15 are parallel or perpendicular to the edge of the substrate 1, forming a regular rectangular array. Four metal conduit matrices 15 are evenly distributed around the large chip 2, allowing heat to be conducted downwards simultaneously from all directions of the chip, avoiding uneven heat dissipation and excessive temperature gradients that may result from single-sided or double-sided layouts. The arrangement structure makes full use of the space in the corner areas of the substrate 1 without affecting the layout of the first groove 11 in the central area and the surrounding pads 12. Furthermore, it facilitates the precise positioning and fixing of the large chip 2, as the large chip 2 can be aligned and fitted with the top surfaces of the four matrix protrusions 151 through its four corners or edges, achieving high-precision self-alignment mounting.

[0041] Optionally, the depth of the first groove 11 ranges from 0.2 to 100 mm, and the depth of the second groove 13 ranges from 0.5 to 100 mm. For example, in this embodiment of the invention, the depth of the second groove 13 ranges from 0.5 mm to 100 mm, and its depth is typically greater than that of the first groove 11. The specific reasons and design considerations are as follows: 1. To accommodate the small chip 3 and bonding wires: The second groove 13 not only needs to house one or more small chips 3, but also needs to reserve sufficient space for wire bonding between the small chip 3 and the metal wire 14. The bonded gold wires will form a certain arc height, typically 0.3mm to 0.8mm. Therefore, the second groove 13 must be deep enough to accommodate these three-dimensional structures and prevent the bonded wires from contacting and short-circuiting with the lower surface of the substrate 1 or the cooler 5. 2. Lower depth limit 0.5mm: This is the minimum depth to meet basic functional requirements, which can accommodate small chips 3 with a thickness of 0.2mm and bonded wire arc height of about 0.3mm. 3. Upper depth limit 100mm: Similar to the first groove 11, this upper limit is reserved space for extreme applications, such as when multi-layer stacked chips or complex three-dimensional circuit structures need to be installed in the second groove 13.

[0042] Optionally, the substrate 1 is in the shape of a regular polygon or a circle, and the material of the substrate 1 is aluminum oxide or aluminum nitride. For example, in this embodiment of the invention, the substrate 1 adopts a regular geometric shape of a regular polygon or a circle, which has the following advantages: 1. Uniform stress distribution: Regular polygons and circles are highly symmetrical geometric shapes. When subjected to external force or thermal stress, the stress can be uniformly distributed along the axis of symmetry, avoiding the stress concentration problem that is easily caused by irregular shapes, and improving the crack resistance and long-term reliability of the substrate; 2. Facilitates standardized packaging: Regular polygons such as squares, regular hexagons, regular octagons and circles are standard shapes widely used in the field of electronic packaging. They have good geometric matching with existing packaging components such as tube shells 6 and lead bases 4, and can directly adopt standard packaging processes and equipment, reducing customization costs; 3. Optimizes space utilization: Circular substrates have the shortest perimeter under the same area, which can minimize the edge area and increase the proportion of effective chip mounting area; Square substrates are convenient for centered mounting in square tube shells, and the distance between the four sides and the inner wall of the tube shell is equal, which facilitates the symmetrical layout of pads 12 and lead posts 41; 4. Convenience of processing: Regular shapes can be efficiently mass-produced through standardized processes such as laser cutting and ceramic molding, with a low defect rate.

[0043] By employing regular polygonal or circular shapes and combining them with high-performance ceramic materials such as alumina or aluminum nitride, the substrate 1 achieves an optimal balance between mechanical strength, thermal properties, electrical properties, and processing feasibility.

[0044] like Figures 4 to 6 As shown, embodiments of the present invention also provide an integrated packaging structure, including as follows: Figures 1 to 2 The ceramic substrate structure shown also includes a lead base 4 and a semiconductor cooler 5. The semiconductor cooler 5 is located below the substrate 1. The cold end of the semiconductor cooler 5 is connected to the lower surface of the substrate 1, and the hot end of the semiconductor cooler 5 is connected to the lead base 4. Multiple lead posts 41 that match the pads 12 are provided through the lead base 4. A heat-conducting post 42 is provided at the bottom of the lead base 4, forming a fully functional packaging system.

[0045] The thermoelectric cooler 5 is located below the substrate 1. The cold end of the thermoelectric cooler 5 is reliably connected to the lower surface of the substrate 1 through a high thermal conductivity interface material. The hot end of the thermoelectric cooler 5 is connected to the lead base 4, which is also achieved using thermally conductive adhesive, thermally conductive silicone grease, or eutectic bonding. The lead base 4 is typically made of a high thermal conductivity metal material, such as copper, aluminum, or copper-tungsten alloy. Its function is not only to provide mechanical support and electrical insulation for the lead posts 41, but more importantly, it serves as the final heat dissipation platform for the package structure. The thermoelectric cooler 5 pumps heat from the cold end to the hot end through the Peltier effect, and the heat from the hot end is then dissipated to the external environment through the lead base 4. To improve heat dissipation efficiency, the bottom of the lead base 4 is usually provided with thermally conductive pillars 42. The thermally conductive pillars 42 can be a protruding array of metal heat sink pillars, or a heat pipe or vapor chamber connected to an external heat sink, ensuring that heat can be quickly and effectively dissipated outside the package.

[0046] Multiple lead posts 41, matching the pads 12, are disposed through the lead base 4. The number, position, and arrangement of the lead posts 41 correspond one-to-one with the pads 12 on the upper surface of the substrate 1. The lead posts 41 are typically made of materials such as Kovar alloy, copper, or nickel-iron alloy. These materials have good conductivity and solderability, and their coefficient of thermal expansion is similar to that of ceramic materials, which can effectively reduce thermal stress. The lead posts 41 penetrate the lead base 4 vertically, with their lower ends extending out of the bottom surface of the lead base 4 to form external leads that can be soldered to the printed circuit board (PCB). Their upper ends extend out of the upper surface of the lead base 4 to the vicinity of the substrate 1, where they are electrically connected to the pads 12 on the upper surface of the substrate 1 via lead bond alloy wires or aluminum wires.

[0047] Specifically, the lead post 41 must not touch the thermoelectric cooler 5. That is, when the lead post 41 passes through the lead base 4, its position should avoid the projection range of the thermoelectric cooler 5. Typically, the lead posts 41 are arranged circumferentially around the thermoelectric cooler 5 at intervals, forming a ring or rectangular array surrounding the thermoelectric cooler 5. This layout ensures electrical isolation between the lead post 41 and the thermoelectric cooler 5 to prevent short circuits, while not affecting the heat dissipation performance of the cooler.

[0048] This embodiment constructs a highly efficient thermal management system that combines active and passive heat dissipation by introducing a semiconductor cooler 5 and a scientifically designed lead base 4. This active cooling capability is particularly suitable for devices that are extremely sensitive to temperature, such as infrared detectors and avalanche photodiodes (APDs), and can significantly reduce dark current, improve detection sensitivity and dynamic range, and bring the device performance to its optimal state.

[0049] Optionally, multiple lead posts 41 are arranged circumferentially around the thermoelectric cooler 5. Exemplarily, in this embodiment, the circumferential spacing of the lead posts 41 means that, with the geometric center of the thermoelectric cooler 5 as a reference point, the multiple lead posts 41 are uniformly or quasi-uniformly distributed on a closed curve such as a circle, ellipse, or rectangle around this center point. All lead posts 41 are located on the periphery of the thermoelectric cooler 5, maintaining a safe distance from the edge of the thermoelectric cooler 5, typically ≥2mm, ensuring that there is no electrical contact between the lead posts 41 (usually metal conductors) and the external electrodes or metallization layer of the thermoelectric cooler 5, thus avoiding the risk of short circuits. The circumferentially uniformly arranged lead posts 41 provide symmetrical mechanical support for the lead base 4 and the entire package structure, avoiding structural imbalance or stress concentration caused by uneven lead post arrangement. This layout fully utilizes the annular space around the thermoelectric cooler 5, maximizing the number of pins within a limited package size without affecting the installation and operation of the cooler.

[0050] Optionally, a ceramic tube 43 is provided on the lead base 4, and the lead post 41 passes through the ceramic tube 43. Exemplarily, in this embodiment of the invention, the ceramic tube 43 provides a double insulation barrier between the lead post 41 and the lead base 4. The interface between the ceramic tube 43 itself and the outer wall of the ceramic tube and the lead base material significantly improves insulation reliability. Through the glass glaze sintering process, the glass layer formed between the ceramic tube 43 and the lead post 41 has excellent airtightness, effectively preventing external moisture, corrosive gases, and contaminants from entering the package, protecting sensitive components such as the large chip 2, small chip 3, and bonding wires from environmental corrosion, and extending the device's lifespan. The ceramic tube 43 provides mechanical protection for the lead post 41, enhancing its resistance to bending and pulling. During the assembly, transportation, and use of the package, the lead post 41 may be subjected to lateral or tensile forces. The wrapping of the ceramic tube 43 can disperse these stresses, preventing the lead post 41 from breaking or loosening at the lead base 4. Finally, both the ceramic material and the glass glaze can withstand temperatures above 300°C without failure, which allows the encapsulation structure using ceramic tube 43 to withstand harsh processes and operating environments such as high-temperature welding and high-temperature aging, making it suitable for high-temperature applications.

[0051] Optionally, it also includes a cylindrical shell 6, with a cover 61 on the top of the shell 6. The large chip 2 is a back-illuminated APD device. The cover 61 has a light-transmitting area 62 corresponding to the large chip 2. The shell 6 is placed on the lead base 4 and the cover 61 covers the substrate 1 and the lead post 41. For example, in this embodiment of the invention, the complete packaging solution provided in this embodiment has been fully optimized for the special requirements of back-incident APD devices: by setting the cover 61, the high-precision alignment and high transmittance design of the light-transmitting area 62, the incident light energy loss is very small, the light power received by the photosensitive area is maximized, and the detection sensitivity is improved; the double-sided interconnect structure realizes the ultra-short connection between the APD output end and the amplifier input end, the parasitic capacitance is <0.5pF, the bandwidth can reach GHz level, and it supports high-speed optical communication and lidar applications; the active cooling of the semiconductor cooler 5, combined with the efficient heat conduction of the metal conduit matrix 15, can stabilize the APD operating temperature within the preset range, and the detection sensitivity and signal-to-noise ratio are significantly improved; the hermetically sealed packaging, combined with the sealed pins of the ceramic tube 43, ensures long-term reliability and improves the overall service life.

[0052] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A ceramic substrate structure, characterized in that, It includes a substrate (1), a large chip (2), and a small chip (3). The upper surface of the substrate (1) is provided with a first groove (11) and a plurality of pads (12). The plurality of pads (12) are arranged around the edge of the substrate (1). The lower surface of the substrate (1) is provided with a second groove (13). The first groove (11) is connected to the bottom surface of the second groove (13). A plurality of metal wires (14) are provided in the second groove (13) corresponding to the plurality of pads (12). The metal wires (14) are electrically connected to the corresponding pads (12) through through-hole technology. The large chip (2) is fixedly connected to the top surface of the substrate (1). The small chip (3) is fixedly connected to the second groove (13). The large chip (2), the small chip (3) and the metal wires (14) are electrically connected by wire bonding. The substrate (1) is provided with a plurality of metal conduit matrices (15). The metal conduit matrices (15) include matrix protrusions (151) protruding from the upper and lower surfaces of the substrate (1). Multiple conduits (152) are provided on the matrix protrusions (151) in a direction perpendicular to the substrate (1). The large chip (2) is attached to the top surface of the matrix protrusions (151) by thermally conductive adhesive.

2. The ceramic substrate structure according to claim 1, characterized in that, The metal conduit matrix (15) consists of four parts, arranged in a rectangular array around the first groove (11).

3. The ceramic substrate structure according to claim 1, characterized in that, The diameter of the catheter (152) ranges from 0.1 to 1 mm.

4. The ceramic substrate structure according to claim 1, characterized in that, The depth of the first groove (11) ranges from 0.2 to 100 mm, and the depth of the second groove (13) ranges from 0.5 to 100 mm.

5. The ceramic substrate structure according to claim 1, characterized in that, The substrate (1) is in the shape of a regular polygon or a circle, and the substrate (1) is made of aluminum oxide or aluminum nitride.

6. An integrated packaging structure comprising the ceramic substrate structure as described in any one of claims 1 to 5, characterized in that, It also includes a lead base (4) and a semiconductor cooler (5). The semiconductor cooler (5) is located below the substrate (1). The cold end of the semiconductor cooler (5) is connected to the lower surface of the substrate (1). The hot end of the semiconductor cooler (5) is connected to the lead base (4). A plurality of lead posts (41) matching the pads (12) are provided through the lead base (4). A heat-conducting post (42) is provided at the bottom of the lead base (4).

7. The integrated packaging structure according to claim 6, characterized in that, Multiple lead posts (41) are arranged circumferentially around the semiconductor cooler (5).

8. The integrated packaging structure according to claim 6, characterized in that, A ceramic tube (43) is provided on the lead base (4), and the lead post (41) passes through the ceramic tube (43).

9. The integrated packaging structure according to claim 6, characterized in that, It also includes a cylindrical shell (6), the top of which is provided with a cap (61). The large chip (2) is a back-illuminated APD device. The cap (61) is provided with a light-transmitting area (62) corresponding to the large chip (2). The shell (6) is placed on the lead base (4) and the cap (61) covers the substrate (1) and the lead post (41).

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