Cold backup control method, cold backup controller and integrated circuit of processing core

Abstract

The application discloses a cold backup control method and controller of a processing core and an integrated circuit, relates to the technical field of processors, and comprises the following steps: in a current evaluation period, the cold backup controller can collect running state information of a target processing core corresponding to the cold backup controller, and adopts a preset scoring rule to evaluate the running state information, so that a target score of the target processing core in the current evaluation period is obtained. In a continuous preset number of periods, when the scores of the target processing core are all within a preset score threshold range, an interruption flag of the target processing core is read from an interruption controller, a task allocation flag of the target processing core is read from a task scheduler, and then whether the target processing core meets a cold backup condition is determined according to the interruption flag and the task allocation flag; if yes, a cold backup switching operation is performed on the target processing core. In this way, the response is timely, and the cold backup controller is only responsible for the processing core corresponding to the cold backup controller, so that the control granularity is relatively fine.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a cold standby control method, a cold standby controller, and an integrated circuit for processing cores. Background Technology

[0002] As the number of processing cores in servers continues to increase, and the dynamic nature of multi-threaded tasks in high-concurrency computing scenarios becomes more pronounced, processors often have a large number of processing cores that are under low load, intermittently active, and idle for extended periods. If these processing cores remain active continuously, it will not only lead to an increase in the overall power consumption of the integrated circuits, but may also cause localized heat buildup, making it difficult to meet high energy efficiency requirements and limiting the performance release of the server.

[0003] Current mainstream power control technologies mostly rely on operating system-level scheduling strategies. For example, the operating system binds tasks to active processing cores and pulls other cores into a low-power state. However, such methods are overly dependent on the operating system, resulting in high response latency and coarse control granularity. In summary, these technologies have low control efficiency and flexibility. Summary of the Invention

[0004] This application provides a cold standby control method for processing cores, a cold standby controller, an integrated circuit, a storage medium, and a program product to solve the problems of low control efficiency and flexibility in related technologies.

[0005] This application provides a cold standby control method for processing cores, the method being executed by a cold standby controller, the method comprising:

[0006] During the current evaluation cycle, the operating status information of the target processing core corresponding to the cold standby controller is collected;

[0007] The operating status information is evaluated using preset scoring rules to obtain the target score of the target processing core in the current evaluation cycle;

[0008] If the scores corresponding to the target processing core for a consecutive preset number of cycles all fall within the preset score threshold range, the interrupt flag of the target processing core is read from the interrupt controller.

[0009] Read the task allocation flags of the target processing core from the task scheduler;

[0010] Based on the interruption flag and task allocation flag, determine whether the target processing core meets the cold standby conditions;

[0011] If the target processing core meets the cold standby conditions, perform a cold standby switchover operation on the target processing core.

[0012] This application also provides a cold standby controller, including:

[0013] The operation status collector is used to collect the operation status information of the target processing core corresponding to the cold standby controller during the current evaluation cycle; and transmit the operation status information to the scoring calculator.

[0014] The scoring calculator is used to evaluate the operating status information using preset scoring rules, obtain the target score of the target processing core in the current evaluation cycle, and transmit the target score to the status criterion.

[0015] The status criterion is used to trigger a cold standby request when the scores corresponding to the target processing core for a consecutive preset number of cycles all fall within the preset score threshold range; and to send the cold standby request to the status controller.

[0016] The status controller, upon receiving a cold standby request, reads the interrupt flag of the target processing core from the interrupt controller; reads the task allocation flag of the target processing core from the task scheduler; determines whether the target processing core meets the cold standby conditions based on the interrupt flag and the task allocation flag; and performs a cold standby switchover operation on the target processing core if the cold standby conditions are met.

[0017] This application also provides an integrated circuit, comprising:

[0018] At least one cold standby controller is used to perform cold standby switching operations on the processing core corresponding to itself;

[0019] At least one processing core;

[0020] One of the cold standby controllers is connected to its corresponding processing core.

[0021] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the cold standby control method of any of the above-described processing cores.

[0022] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described cold standby control methods for processing cores.

[0023] Through this application, during the current evaluation cycle, the cold standby controller can collect the operating status information of the target processing core corresponding to itself, and evaluate the operating status information using preset scoring rules to obtain the target score of the target processing core in the current evaluation cycle. If, within a consecutive preset number of cycles, the target processing core's score falls within a preset scoring threshold range, the interrupt flag of the target processing core can be read from the interrupt controller and the task allocation flag of the target processing core can be read from the task scheduler. Based on the interrupt flag and task allocation flag, it can be determined whether the target processing core meets the cold standby conditions. If so, a cold standby switchover operation can be performed on the target processing core. In this process, this solution can directly read relevant flags from the interrupt controller and task scheduler, without relying on operating system-level scheduling. Instead, the cold standby controller directly determines whether to perform a cold standby switchover operation at the hardware level, resulting in timely response and high efficiency. Furthermore, each cold standby controller only needs to be responsible for the cold standby switchover operation of its corresponding processing core, enabling fine-grained power consumption control, i.e., finer control granularity, which improves the flexibility of cold standby control. Attached Figure Description

[0024] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating a cold standby control method for processing cores provided in an embodiment of this application;

[0026] Figure 2 A schematic diagram of the architecture of a cold standby controller provided in an embodiment of this application;

[0027] Figure 3 A flowchart illustrating another cold standby control method for processing cores provided in this application embodiment;

[0028] Figure 4 A schematic diagram of another cold standby controller architecture provided in an embodiment of this application;

[0029] Figure 5 This application provides a schematic diagram of a wake-up process for a processing core.

[0030] Figure 6 A schematic diagram of an integrated circuit architecture provided for an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of another integrated circuit architecture provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0033] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0034] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Embodiments of this application provide a cold standby control method for a processing core, which can be executed by a cold standby controller. The cold standby controller can be located in an electronic device with a System of Chips (SOC), such as a server, a terminal device (e.g., a computer, a mobile phone), etc. The processing core is any one of one or more processing cores included in the processor on the System of Chips. Figure 1 As shown, the specific processing steps of the cold standby control method for processing cores may include:

[0036] Step 101: During the current evaluation cycle, collect the operating status information of the target processing core corresponding to the cold standby controller.

[0037] Specifically, a cold standby controller can be dedicated to performing cold standby switching operations on a single processing core. The evaluation cycle length can be pre-written into the integrated circuit's configuration register. The cold standby controller can read the evaluation cycle length from the configuration register in advance and periodically score the target processing core according to this cycle length. Correspondingly, in any evaluation cycle, the cold standby controller can collect the operating status information from the target processing core corresponding to itself. This operating status information can be written into the configuration register by the processing core based on its real-time operating status and updated in real time.

[0038] Step 102: Using preset scoring rules, evaluate the operating status information to obtain the target score of the target processing core in the current evaluation cycle.

[0039] Specifically, the preset scoring rules can specify the specific processing method for evaluating the operating status information. Accordingly, after collecting the operating status information of the target processing core in the current evaluation cycle, the cold standby controller can use the preset scoring rules to evaluate the operating status information and obtain the target score.

[0040] Step 103: If the scores corresponding to the target processing core for a consecutive preset number of cycles all fall within the preset score threshold range, read the interrupt flag of the target processing core from the interrupt controller.

[0041] The preset number can range from 4 to 8, and can be adjusted based on task activity and / or load fluctuation characteristics. Two examples illustrate this: Example 1: For high-activity tasks (processing user requests, performing intensive calculations, database queries, etc.), the load fluctuates significantly, and sudden traffic spikes may occur. A small preset number might cause the target processing core to switch frequently within a short period. In this case, the preset number can be set to 6. Example 2: For periodically stable, batch-processing tasks (such as video transcoding), the load characteristic is a long period of full-load operation followed by a long, predictable idle period. In this case, the preset number can be set to 7 or 8. This is because once a processing core is idle, it is likely to remain idle for a considerable time. Increasing the preset number ensures that the target processing core only triggers a cold standby state after entering a stable, long-term idle period, avoiding unnecessary state switching operations.

[0042] The evaluation method for scores falling within the preset scoring threshold range is related to the scoring method of the preset scoring rules. For example, it could be greater than the preset scoring threshold, or it could be less than the preset scoring threshold. The preset scoring threshold can be adjusted in real time based on one or more factors such as processing core type, load mode, or power consumption strategy.

[0043] Taking falling within the preset scoring threshold range as an example, the processing core type can be a performance core or an energy efficiency core. For performance cores, which have higher power consumption, the preset scoring threshold can be lowered to the first preset value to save energy. For energy efficiency cores, which have lower power consumption, the preset scoring threshold can be raised to the second preset value (the first preset value is less than the second preset value) to avoid the additional losses caused by frequent state switching.

[0044] The load mode can be either batch computing applications (rendering, compilation) or interactive applications (interface interaction, games). For batch computing tasks, which are not sensitive to latency, the preset scoring threshold can be lowered to the first preset value, making it easier for the target processing core to enter a cold standby state, reducing power consumption and heat generation. For interactive applications, which usually require instantaneous response, in order to avoid large latency caused by the target processing core being in a cold standby state when users operate frequently, the preset scoring threshold can be raised to the second preset value.

[0045] The power consumption strategy can be performance mode, energy consumption mode, or balanced mode. For performance mode, the preset score threshold is increased to the second preset value. For energy consumption mode, the preset score threshold is decreased to the first preset value. For balanced mode, no adjustment is made, and the value is kept at the third preset value. The third preset value is greater than the first preset value and less than the second preset value.

[0046] Both the preset quantity and the preset scoring threshold can be pre-written into the aforementioned configuration register by the processing core. The cold standby controller monitors the configuration register, and upon detecting a change in the preset quantity, it reads the latest preset quantity from the configuration register; similarly, upon detecting a change in the preset scoring threshold, it reads the latest preset scoring threshold from the configuration register. The adjustment operations for the preset quantity and preset scoring threshold can be controlled by the operating system and written into the configuration register by the processing core.

[0047] The above-mentioned methods, which adjust preset quantities and preset scoring thresholds by handling influencing factors such as core type and load type, can improve the accuracy of cold standby switching operations in different scenarios.

[0048] Specifically, to prevent frequent fluctuations in scores around a preset score threshold, which could lead to repeated cold standby switching operations, a pre-set number of periods (i.e., a preset number) can be set. The cold standby switching operation is only performed when the target processing core's score falls within the preset score threshold for a consecutive preset number of periods. Furthermore, the interrupt controller is primarily responsible for allocating interrupt requests to the corresponding processing cores. The processing cores execute interrupt operations based on the received interrupt requests. Therefore, to ensure that the target processing core can handle interrupt operations promptly and avoid impacting related tasks, it can be determined whether the target processing core meets the cold standby conditions before performing the cold standby switching operation. Thus, the cold standby controller can also read the interrupt flag of the target processing core from the interrupt controller.

[0049] Step 104: Read the task allocation flag of the target processing core from the task scheduler.

[0050] Specifically, the task scheduler can be responsible for allocating and scheduling tasks to each processing core. Similarly, in order to ensure that the target processing core can execute tasks in a timely manner, the cold standby controller can also read the task allocation flag of the target processing core from the task scheduler.

[0051] Step 105: Determine whether the target processing core meets the cold standby conditions based on the interruption flag and the task allocation flag.

[0052] Specifically, since the interrupt flag can be used to indicate whether there is an interrupt request that is about to arrive at the target processing core, and the task allocation flag can be used to indicate whether there is a scheduled task that is about to arrive at the target processing core, if the cold standby switch operation is performed directly, these tasks will not be completed in time. Therefore, the cold standby controller can combine the interrupt flag and the task allocation flag to determine whether the target processing core needs to process the upcoming task, that is, to determine whether the target processing core meets the cold standby conditions.

[0053] Step 106: If the target processing core meets the cold standby conditions, perform a cold standby switch operation on the target processing core.

[0054] Specifically, if the target processing core meets the cold standby conditions, the cold standby controller can directly perform a cold standby switch operation on the target processing core to put it into a cold standby state. The cold standby state is a low-power operating state, which reduces power consumption. If the target processing core does not meet the cold standby conditions, the cold standby controller can choose not to perform a cold standby switch operation on the target processing core, maintaining its normal operating state so that the target processing core can complete relevant tasks in a timely manner, such as executing interrupt operations or tasks assigned by the task scheduler.

[0055] After the cold standby controller completes the cold standby switchover operation for the target processing core, the cold standby controller no longer needs to perform evaluation operations on the target processing core, thereby reducing its own power consumption.

[0056] The cold standby control method for processing cores in this application involves the cold standby controller collecting the operating status information of the target processing core corresponding to itself during the current evaluation cycle. It then evaluates the operating status information using preset scoring rules to obtain the target score of the target processing core in the current evaluation cycle. If, within a preset number of consecutive cycles, the target processing core's score falls within a preset scoring threshold range, the cold standby controller reads the interrupt flag of the target processing core from the interrupt controller and the task allocation flag from the task scheduler. Based on the interrupt flag and task allocation flag, it determines whether the target processing core meets the cold standby conditions. If so, a cold standby switching operation can be performed on the target processing core. In this process, this solution can directly read relevant flags from the interrupt controller and task scheduler, without relying on operating system-level scheduling. Instead, the cold standby controller directly determines whether to perform a cold standby switching operation at the hardware level, resulting in timely response and high efficiency. Furthermore, each cold standby controller only needs to be responsible for the cold standby switching operation of its corresponding processing core, enabling fine-grained power consumption control and improving the flexibility of cold standby control.

[0057] In some optional implementations, the running status information may include the idle clock cycle percentage and instruction activity of the target processing core. The idle clock cycle percentage is the ratio of the number of idle clock cycles to the number of clock cycles included in the first time window, and the instruction activity is the ratio of the number of valid instructions submitted by the target processing core to the number of clock cycles included in the second time window. Valid instructions are those actually received and processed by the processing core, excluding cancelled instructions, no-operation instructions, and instructions stalled due to blocking. Accordingly, in step 102 above, a preset scoring rule is used to evaluate the running status information to obtain the target score of the target processing core in the current evaluation period, which may specifically include:

[0058] Step 1: Determine the first sub-score based on the proportion of idle clock cycles and the first weighting coefficient.

[0059] Step two: Determine the second sub-score based on the instruction activity level and the second weighting coefficient.

[0060] Step 3: Determine the target score of the target processing kernel in the current evaluation period based on the first sub-score and the second sub-score.

[0061] Specifically, in any given clock cycle, the target processing core may not execute any instructions, may execute one instruction, or may execute multiple instructions. The clock cycle in which no instructions are executed can be called an idle clock cycle.

[0062] The task scheduler can set a running status flag for the target processing core. In any clock cycle within the first time window, if it is determined that the target processing core has not executed any instructions, the running status flag corresponding to the target processing core can be set to the first flag. When the running status flag is detected as the first flag (which can be 1) in any clock cycle, a first counter is incremented. The task scheduler can determine whether the target processing core is executing instructions in any clock cycle in the following ways: First, it checks whether any instructions have been successfully sent to the target processing core in that clock cycle. If yes, it determines that the target processing core is executing instructions in that clock cycle; otherwise, it determines that the target processing core is not executing instructions in that clock cycle. Second, it checks whether the target processing core's task queue is empty in that clock cycle. If yes, it determines that the target processing core is executing instructions in that clock cycle; otherwise, it determines that the target processing core is not executing instructions in that clock cycle.

[0063] After the first time window ends, the cold standby controller can determine the idle clock cycle percentage by the ratio between the value of the first counter recorded in the first time window and the number of clock cycles included in the first time window.

[0064] Furthermore, each time the target processing core successfully completes the commit operation of an instruction, it generates a commit flag signal. After the task scheduler can detect the commit flag signal, it increments the second counter. After the second time window ends, the cold standby controller can determine the instruction activity level by the ratio between the value of the second counter recorded in the second time window and the number of clock cycles included in the second time window.

[0065] During the current evaluation cycle, the cold standby controller determines the first sub-score by multiplying the idle clock cycle percentage by a first weighting coefficient, and then determines the second sub-score based on the instruction activity and a second weighting coefficient. Finally, the sum of the first and second sub-scores is determined as the target score.

[0066] Thus, high instruction activity indicates that the target processing core is executing instructions efficiently and is very busy, making it unsuitable for entering a deep low-power state. Low instruction activity indicates that the target processing core is mostly idle or paused, with very low activity, making it suitable for entering a deep low-power state. A high percentage of idle periods indicates that the target processing core is not fully utilized most of the time, with a light load or in a waiting state, making it suitable for entering a low-power operating state. Conversely, a high percentage of idle periods indicates that the target processing core is continuously busy and under saturated load, requiring high-performance operation to meet computational demands. Therefore, by calculating a score using these two metrics, it is possible to accurately determine whether the target processing core can enter a cold standby state.

[0067] For example, step one can be expressed as follows:

[0068] (1)

[0069] Step two can be expressed as follows:

[0070] (2)

[0071] Step three can be expressed as follows:

[0072] (3)

[0073] in, Rate the target. As the first weighting coefficient, This is the second weighting coefficient. The percentage of idle clock cycles. The number of idle clock cycles. The number of clock cycles included in the first time window. The first sub-score, For command activity, The number of valid instructions submitted. The number of clock cycles included in the second time window. This is the second sub-rating value. Generally, it can be set to... , .

[0074] In some optional implementations, the operating system or power management firmware can also adjust the values ​​of the first and second weighting coefficients based on the load type or core type of the processing core. For example, considering the core type as an influencing factor, the second weighting coefficient can be increased by a preset value for performance cores, and the first weighting coefficient can be increased by a preset value for energy-efficient cores. The preset value can be 0.1, 0.2, etc. Considering the load type as an influencing factor, the second weighting coefficient can be increased by a preset value for compute-intensive load types, and the first weighting coefficient can be increased by a preset value for input / output (IO) request-intensive load types. The above method of adjusting the weighting coefficients based on factors such as core type and load type can improve the accuracy of cold standby switching operations in different scenarios.

[0075] In some optional implementations, the number of clock cycles included in the current evaluation period may be greater than the number of clock cycles included in the first time window, and the number of clock cycles included in the first time window may be greater than the number of clock cycles included in the second time window, where the second time window is a sliding time window. The first time window may include 64 clock cycles.

[0076] For example, in Table 1, column 1 represents the clock cycle number, column 2 represents the second time window, column 3 represents whether to update instruction activity, and column 4 represents whether to perform scoring. The evaluation cycle has a cycle length of 256, meaning the evaluation cycle includes 256 clock cycles, and the second time window includes 32 clock cycles.

[0077] Table 1

[0078]

[0079] During operation, after completing a short task, processing core 1 enters a low-load state. In the 1023rd clock cycle, the idle cycle count is 0.92 and the instruction activity is 0.1. According to formula (3), the score can be calculated as 0.912, and the score has been higher than the preset score threshold for three consecutive scoring cycles. At this time, it can be determined that the score of processing core 1 stably meets the conditions for generating a cold standby, and thus a cold standby switchover operation can be performed. In Table 1, when the second time window is not full, the instruction activity can also be calculated based on the count value and clock cycle number of each existing clock cycle.

[0080] In some optional implementations, in step 105 above, the cold standby controller may use the following specific steps to determine whether the target processing core meets the cold standby conditions based on the interrupt flag and the task allocation flag:

[0081] In scenario one, if the interrupt flag indicates that there is no interrupt request corresponding to the target processing core in the interrupt controller, and the task allocation flag indicates that there is no pending task corresponding to the target processing core in the task scheduler, then the target processing core is determined to meet the cold standby condition.

[0082] Alternatively, in scenario two, if the interrupt flag is used to indicate that there is an interrupt request in the interrupt controller corresponding to the target processing core, or the task allocation flag is used to indicate that there is a task to be processed in the task scheduler corresponding to the target processing core, then the target processing core does not meet the cold standby condition.

[0083] Specifically, the interrupt controller can be configured with interrupt flags corresponding to each processing core. When an interrupt flag is 1, it indicates that there is an interrupt request corresponding to a processing core; when an interrupt flag is 0, it indicates that there is no interrupt request corresponding to a processing core. Similarly, the task scheduler can be configured with task allocation flags corresponding to each processing core. When a task allocation flag is 1, it indicates that there is a task to be processed corresponding to a processing core; when a task allocation flag is 0, it indicates that there is no task to be processed corresponding to a processing core.

[0084] Therefore, the cold standby controller can determine that the target processing core meets the cold standby conditions when the interrupt flag corresponding to the target processing core is 0 and the task allocation flag is 0. Conversely, it can determine that the target processing core does not meet the cold standby conditions when the interrupt flag corresponding to the target processing core is 1 and the task allocation flag is 0, or when the interrupt flag corresponding to the target processing core is 0 and the task allocation flag is 1, or when the interrupt flag corresponding to the target processing core is 1 and the task allocation flag is 1.

[0085] In some alternative implementations, in step 106 above, the cold standby controller may perform a cold standby switchover operation on the target processing core using the following specific steps:

[0086] Step 1: Send a cold standby preparation notification to the target processing core.

[0087] Step 2: After receiving the cold standby completion notification from the target processing core, shut down the main clock signal and main power domain corresponding to the target processing core.

[0088] The cold backup preparation notification can be used to instruct the target processing core to perform a cold backup preparation operation. This operation includes saving the context information corresponding to the target processing core to the target memory, performing a dirty data write-back operation on the target cache corresponding to the target processing core, and invalidating the cache. The target cache is a level-one data cache. The cold backup completion notification can be used to indicate that the target processing core has completed the cold backup preparation operation.

[0089] Context information can include data recorded in registers such as the general-purpose register set, program counter, and status register. The general-purpose register set is a set of the fastest basic storage units inside the processor that are directly exposed to programmers or compilers by the instruction set architecture. It is usually used to temporarily store operands, intermediate results, and address information required during instruction execution. The program counter can be used to store the memory address of the next instruction to be executed. The status register can be used to store various status and flag information after the processing core has completed related operations.

[0090] The target memory can be random access memory (RAM).

[0091] Specifically, in order to ensure that the target processing core can continue to execute tasks correctly after being woken up, the cold standby controller can send a cold standby preparation notification to the target processing core. After receiving the cold standby preparation notification, the target processing core can first read the data recorded in the general-purpose register group, program counter, and status register, use the read data as its own context information, and save it to the target memory.

[0092] Furthermore, to ensure cache consistency in multi-core systems, processing cores in cold standby mode no longer participate in cache consistency maintenance during the cold standby period. Therefore, upon receiving a cold standby preparation notification, the target processing core can also perform dirty data write-back and cache invalidation operations on the primary data cache. Specifically, dirty data write-back and cache invalidation operations can include:

[0093] The target processing core can iterate through the cache lines in its Level 1 Data Cache (L1D Cache). Upon encountering a cache line and determining that it is marked as dirty (a dirty cache line indicates that the cached data has been modified by the current processing core and not written back to the next level cache), the target processing core can initiate a write-back transaction to write the data in the dirty cache line back to the shared cache or main memory (i.e., main memory). After completing the write-back of all dirty data, the target processing core can mark all cache lines in its Level 1 Data Cache as invalid. In this way, the Level 1 Data Cache of the target data is logically cleared, no longer holding any valid data copies, thus exiting data consistency maintenance.

[0094] For the Level 1 Instruction Cache (L1I Cache), since it is read-only and does not involve data consistency issues, maintenance can be skipped. This means the target processing core does not need to perform dirty data write-back and invalidation operations on the L1I Cache. This improves the efficiency of instruction fetching and reduces wake-up overhead after the target processing core is woken up. For the truly globally shared cache portion, since other active cores still need to access it, invalidation is not performed; the cold standby core simply no longer participates in its consistency maintenance. After completing the above cold standby preparation operations, the target processing core can send the corresponding cold standby completion notification to the cold standby controller.

[0095] Upon receiving a cold standby completion notification from the target processing core, the cold standby controller can determine that the target processing core has completed the cold standby preparation operation and can safely switch it to the cold standby state. Furthermore, to reduce the power consumption of the target processing core, the cold standby controller can disable the target processing core's main power domain and main clock signal, thereby reducing the resources occupied by the transmitted clock signal and lowering overall resource consumption.

[0096] In this way, cache consistency is ensured through cache consistency operations before cold backup, thus ensuring stable system operation during the cold backup process.

[0097] In some alternative implementations, in step two above, the operation of shutting down the master clock signal can be performed by the cold standby controller notifying the clock controller. Accordingly, the cold standby controller can send a cold standby switchover notification corresponding to the target processing core to the clock controller.

[0098] The cold standby switch notification can be used to instruct the clock controller to turn off the main clock signal corresponding to the target processing core.

[0099] Specifically, the clock controller can be used to transmit the corresponding master clock signal to each processing core. When the cold standby controller determines that the target processing core meets the cold standby conditions, it can send the corresponding cold standby switching notification to the clock controller (for example, by pulling up the control signal between the clock controller and the target processing core). Then, the clock controller can stop transmitting the master clock signal to the target processing core.

[0100] In some alternative implementations, in step two above, the operation of shutting down the main power domain can be performed by the cold standby controller notifying the power domain controller. Accordingly, the cold standby controller can send a cold standby switchover notification corresponding to the target processing core to the power domain controller.

[0101] The cold standby switch notification can be used to instruct the power domain controller to shut down the main power domain corresponding to the target processing core.

[0102] Specifically, the power domain controller can be used to manage the power domain of each processing core. When the cold standby controller determines that the target processing core meets the cold standby conditions, it can send a corresponding cold standby switching notification to the power domain controller (e.g., pull up the control signal between the power domain controller and the cold standby controller). Then, the power domain controller can shut down the main power domain of the target processing core to reduce energy consumption.

[0103] In some alternative implementations, after step 106, the cold standby controller may further perform the following specific steps:

[0104] After determining that a wake-up event has occurred corresponding to the target processing core, a wake-up operation is performed on the target processing core.

[0105] The wake-up event can include one or more of the following events:

[0106] First, an interrupt flag is detected to indicate that there is an interrupt request in the interrupt controller corresponding to the target processing core; second, a task allocation flag is detected to indicate that there is a task to be processed corresponding to the target processing core in the task scheduler; third, a bus access request corresponding to the target processing core is detected; fourth, an input / output transaction request corresponding to the target processing core is detected; fifth, a memory transfer request corresponding to the target processing core is detected, which is generally also called a direct memory access (DMA) request.

[0107] For example, continuing with the example in Table 1 above, in the 1760th clock cycle, the interrupt controller receives an interrupt signal targeting processing core 1. The cold standby controller detects the interrupt signal going high and immediately executes the wake-up procedure.

[0108] In this way, after a wake-up event is detected at the hardware level, the target processing core can quickly resume its working state, enabling faster perception and response to external events. This ensures that even in a cold standby state, the processing core can operate with low power and respond quickly without interrupting system services.

[0109] In some alternative implementations, the wake-up operation of the target processing core can take the following specific steps:

[0110] Start the main clock signal and main power domain corresponding to the target processing core.

[0111] The target processing core loads context information from the target memory and performs operations corresponding to the wake-up event after the main clock signal and main power domain are ready.

[0112] Specifically, upon detecting a wake-up event, the cold standby controller can send a corresponding job switching notification to the clock controller (e.g., pulling the control signal between itself and the clock controller low), thereby enabling the clock controller to begin transmitting the master clock signal to the target processing core. It also sends a corresponding job switching notification to the power domain controller (e.g., pulling the control signal between itself and the power domain controller low), thereby enabling the power domain controller to activate the main power domain of the target processing core. Once the target processing core's master clock signal and main power domain are ready, it can load context information from the target memory, restore the data in the general purpose register set, program register, and status register using the loaded context information, and execute the operation corresponding to the wake-up event.

[0113] In some optional implementations, during the cold standby switching operation in step 106 above, the cold standby controller may also mark the state corresponding to the target processing core as a cold standby state.

[0114] Specifically, the cold standby controller can, upon determining that the target processing core meets the cold standby conditions, first set the ready flag of the target processing core to 0 to instruct the target processing core to stop working and enter a low-power cold standby state. After receiving a cold standby completion notification from the target processing core, it then sets the status flag of the target processing core to 1 to indicate that the target processing core no longer participates in task scheduling and cache consistency maintenance.

[0115] Accordingly, the wake-up operation of the target processing core may also include setting the state corresponding to the target processing core to the working state.

[0116] Specifically, after determining that a wake-up event corresponding to the target processing core has occurred, the cold standby controller can set the ready flag of the target processing core to 1 and the status flag of the target processing core to 0 after completing the startup operations of the main clock signal and the main power domain.

[0117] Embodiments of this application also provide a cold standby controller, such as Figure 2 As shown, the cold standby controller may include an operating status acquisition unit, a scoring calculator, a status criterion unit, and a status controller, which are connected in this order.

[0118] The operational status collector is used to collect operational status information of the target processing core corresponding to the cold standby controller during the current evaluation cycle. This operational status information is then transmitted to the scoring calculator.

[0119] The scoring calculator is used to evaluate the operating status information using preset scoring rules, and obtain the target score of the target processing core in the current evaluation cycle. The target score is then transmitted to the status criterion.

[0120] The status criterion is used to trigger a cold standby request when it is determined that the score of the target processing core has not fallen within a preset score threshold range for a consecutive preset number of cycles. The cold standby request is then sent to the status controller.

[0121] The status controller, upon receiving a cold standby request, reads the interrupt flag of the target processing core from the interrupt controller and the task allocation flag of the target processing core from the task scheduler. Based on the interrupt flag and the task allocation flag, it determines whether the target processing core meets the cold standby conditions. If the target processing core meets the cold standby conditions, it performs a cold standby switchover operation on the target processing core.

[0122] Specifically, the runtime status collector can pre-read the evaluation cycle length from the configuration register, and periodically collect the runtime status information of the target processing core according to this cycle length, and transmit it to the scoring calculator. For example... Figure 3 As shown, after receiving the operating status information, the scoring calculator can evaluate the operating status information using preset scoring rules, obtain a target score, and transmit it to the status criterion. Upon receiving the target score, the status criterion can determine whether the target score falls within a preset scoring threshold range. To prevent frequent fluctuations in the score around the preset threshold, which could lead to repeated cold standby switching operations, a pre-set number of cycles (i.e., a preset number) can be set. Only when the scores corresponding to the target processing core for a consecutive preset number of cycles all fall within the preset scoring threshold range will the status criterion trigger a cold standby request and send it to the status controller.

[0123] To ensure the target processing core can handle interrupt operations promptly and avoid impacting related tasks, the state controller, upon receiving a cold standby request, can first determine if the target processing core meets the cold standby conditions. Therefore, the state controller can read the target processing core's interrupt flag from the interrupt controller and its task allocation flag from the task scheduler. Finally, the state controller can combine the interrupt flag and task allocation flag to determine if the target processing core currently needs to handle an upcoming task, i.e., whether it meets the cold standby conditions. If the target processing core meets the cold standby conditions, the state controller can directly perform a cold standby switch operation to put the target processing core into a low-power operating state, reducing resource waste. If the target processing core does not meet the cold standby conditions, the state controller can choose not to perform a cold standby switch operation, maintaining the target processing core's normal operating state so that it can complete related tasks promptly, such as executing interrupt operations or tasks allocated by the task scheduler.

[0124] In the cold standby controller of this application, during the current evaluation cycle, the running status collector can collect the running status information of the target processing core corresponding to itself, and the scoring calculator can evaluate the running status information using preset scoring rules to obtain the target score of the target processing core in the current evaluation cycle. When the status criterion determines that the score of the target processing core falls within a preset scoring threshold range for a consecutive preset number of cycles, it can trigger a cold standby request and send the request to the status controller. The status controller can read the interrupt flag of the target processing core from the interrupt controller and the task allocation flag of the target processing core from the task scheduler. Based on the interrupt flag and the task allocation flag, it determines whether the target processing core meets the cold standby conditions. If so, a cold standby switch operation can be performed on the target processing core. In this process, this solution can directly read the relevant flags from the interrupt controller and the task scheduler, without relying on operating system-level scheduling. Instead, the cold standby controller directly determines whether to perform a cold standby switch operation at the hardware level, resulting in timely response and high efficiency. Furthermore, each cold standby controller only needs to be responsible for the cold standby switching operation of its corresponding processing core, which can achieve fine power consumption control, that is, fine control granularity, and improve the flexibility of cold standby control.

[0125] In addition, the collaborative work between the various modules can realize an automated control path from state awareness to cold standby determination.

[0126] In some optional implementations, the running status information includes the idle clock cycle percentage and instruction activity of the target processing core, wherein the idle clock cycle percentage is the ratio of the number of idle clock cycles to the number of clock cycles included in the first time window, and the instruction activity is the ratio of the number of valid instructions submitted by the target processing core to the number of clock cycles included in the second time window; the preset scoring rules include a first weighting coefficient and a second weighting coefficient; and the scoring calculator is specifically used for:

[0127] The first sub-score is determined based on the proportion of idle clock cycles and the first weighting coefficient;

[0128] The second sub-score is determined based on the instruction activity level and the second weighting coefficient.

[0129] Based on the first sub-score and the second sub-score, the target score of the target processing kernel in the current evaluation period is determined.

[0130] In some alternative implementations, the state controller is specifically used for:

[0131] If the interrupt flag is used to indicate that there is no interrupt request corresponding to the target processing core in the interrupt controller, and the task allocation flag is used to indicate that there is no pending task corresponding to the target processing core in the task scheduler, then the target processing core is determined to meet the cold standby condition.

[0132] or,

[0133] If the interrupt flag is used to indicate that there is an interrupt request corresponding to the target processing core in the interrupt controller, or the task allocation flag is used to indicate that there is a pending task corresponding to the target processing core in the task scheduler, then the target processing core does not meet the cold standby condition.

[0134] In some alternative implementations, the state controller is specifically used for:

[0135] Send a cold standby preparation notification to the target processing core. The cold standby preparation notification is used to instruct the target processing core to perform a cold standby preparation operation. The cold standby preparation operation includes saving the context information corresponding to the target processing core to the target memory, performing a dirty data write-back operation and a cache invalidation operation on the target cache corresponding to the target processing core. The target cache is a level 1 data cache.

[0136] After receiving the cold standby completion notification from the target processing core, the main clock signal and main power domain corresponding to the target processing core are turned off. The cold standby completion notification is used to indicate that the target processing core has completed the cold standby preparation operation.

[0137] In some alternative implementations, the state controller is specifically used for:

[0138] Send a cold standby switch notification corresponding to the target processing core to the clock controller. The cold standby switch notification is used to instruct the clock controller to turn off the master clock signal corresponding to the target processing core.

[0139] In some alternative implementations, the state controller is specifically used for:

[0140] Send a cold standby switch notification corresponding to the target processing core to the power domain controller. The cold standby switch notification is used to instruct the power domain controller to shut down the main power domain corresponding to the target processing core.

[0141] In some alternative implementations, such as Figure 4 As shown, the cold standby controller may also include a listener / wake-up device; the listener / wake-up device is used for:

[0142] After detecting a wake-up event corresponding to the target processing core, a wake-up signal is sent to the state controller;

[0143] State controllers are also used for:

[0144] Upon receiving the wake-up signal, a wake-up operation is performed on the target processing core.

[0145] Specifically, such as Figure 5 As shown, after detecting a wake-up event, the wake-up listener generates a wake-up signal and transmits it to the state controller. Upon receiving the wake-up signal, the state controller restarts the main power domain and main clock signal of the target processing core. Then, after power and clock are restored, the target processing core loads context information from the target memory and restores the general-purpose register group, program register, status register, etc., based on the contents of the context information. Furthermore, if the wake-up event is an interrupt event (i.e., an interrupt flag is detected indicating an interrupt request corresponding to the target processing core in the interrupt controller), the target processing core can adjust to the wake-up source instruction address corresponding to the wake-up event and execute the operation corresponding to the wake-up event. If the wake-up event is a task event (i.e., a task allocation flag is detected indicating a pending task corresponding to the target processing core in the task scheduler), the target processing core can execute the task allocated by the task scheduler. Finally, the cold standby status signal can be pulled low, and the ready signal can be pulled high, i.e., the status flag is set to 0, and the ready flag is set to 1. In this way, the various modules work together to achieve an automated control path from status awareness, cold standby determination, to wake-up recovery.

[0146] In some alternative implementations, the wake-up event includes one or more of the following events:

[0147] The detected interrupt flag is used to indicate that there is an interrupt request in the interrupt controller corresponding to the target processing core;

[0148] The detected task allocation flag is used to indicate to the task scheduler that there is a pending task corresponding to the target processing core;

[0149] A bus access request corresponding to the target processing core was detected.

[0150] Input / output transaction requests corresponding to the target processing core were detected.

[0151] A memory transfer request corresponding to the target processing core was detected.

[0152] In some alternative implementations, the state controller is specifically used for:

[0153] The main clock signal and main power domain corresponding to the target processing core are started. After the main clock signal and main power domain are ready, the target processing core loads context information from the target memory and performs the operation corresponding to the wake-up event.

[0154] In some optional implementations, the target score of the target processing kernel in the current evaluation period is determined based on the first sub-score and the second sub-score, including:

[0155]

[0156]

[0157]

[0158] in, Rate the target. As the first weighting coefficient, This is the second weighting coefficient. The percentage of idle clock cycles. The number of idle clock cycles. The number of clock cycles included in the first time window. The first sub-score, For command activity, The number of valid instructions submitted. The number of clock cycles included in the second time window. This is the second sub-score.

[0159] In some optional implementations, the number of clock cycles included in the current evaluation period is greater than the number of clock cycles included in the first time window, the number of clock cycles included in the first time window is greater than the number of clock cycles included in the second time window, and the second time window is a sliding time window.

[0160] In some alternative implementations, the state controller is also used for:

[0161] Mark the state corresponding to the target processing core as cold standby state.

[0162] For a description of the features in the embodiment corresponding to the cold standby controller, please refer to the relevant description of the embodiment corresponding to the cold standby control method of the processing core, which will not be repeated here.

[0163] Embodiments of this application also provide an integrated circuit, such as... Figure 6 As shown, the integrated circuit includes at least one cold standby controller and at least one processing core, with each cold standby controller and processing core connected in a one-to-one correspondence. Any cold standby controller can be used to perform a cold standby switching operation on its corresponding processing core.

[0164] Specifically, the cold standby controller can perform the cold standby switching operation according to the cold standby control method for the processing core provided in the above embodiments. The structure of the cold standby controller can be referred to the description in the foregoing embodiments, and will not be repeated here.

[0165] The integrated circuit of the processing core in the embodiments of this application includes a cold standby controller for performing cold standby switching operations on a processing core, providing fine-grained control and high flexibility. Furthermore, at the hardware level, the cold standby controller directly performs the cold standby switching operation, resulting in timely response and high control efficiency. In addition, this solution effectively reduces the idle power consumption of the integrated circuit and significantly improves the energy efficiency ratio of multi-core systems in high-concurrency scenarios.

[0166] In some alternative implementations, any cold standby controller is specifically used for:

[0167] Send a cold standby preparation notification to the processing core corresponding to itself;

[0168] Each processing core is also used for:

[0169] After receiving a cold standby preparation notification from the cold standby controller corresponding to itself, it saves the context information corresponding to itself to the target memory.

[0170] Perform dirty data write-back and cache invalidation operations on the target cache corresponding to itself, where the target cache is a first-level data cache.

[0171] In some alternative implementations, any cold standby controller is also used for:

[0172] Upon detecting a wake-up event of its corresponding processing core, the system performs a wake-up operation on the corresponding processing core.

[0173] Each processing core is also used for:

[0174] Upon being awakened, it reads the context information corresponding to itself from the target memory;

[0175] Perform the operation corresponding to the wake-up event.

[0176] In some alternative implementations, the integrated circuit further includes a power domain controller; the power domain controller is also used for:

[0177] Upon receiving a cold standby switchover notification from the status controller in any cold standby controller, the power supply to the running status acquisition unit, scoring calculator, status criterion unit, and status controller in the cold standby controller is cut off, while the power supply to the target memory and the listening wake-up unit is maintained.

[0178] In this way, by cutting off the power supply to some modules in the cold standby controller and only retaining the power supply to the listener wake-up device, minimum response capability can be guaranteed, and the power consumption of the integrated circuit can be reduced.

[0179] In some alternative implementations, the state controller in the cold standby controller can also send a consistency domain exit request to the consistency management module in the integrated circuit to cancel the cache line copy of the target processing core connected to the cold standby controller in the consistency domain, which can prevent the target processing core from receiving a listening request for a consistency transaction in the cold standby state.

[0180] For a description of the features in the embodiment corresponding to the integrated circuit, please refer to the relevant description of the embodiment corresponding to the cold standby control method of the processing core, which will not be repeated here.

[0181] The following example illustrates the structure of an integrated circuit.

[0182] like Figure 7 As shown, a processing core is connected to a cold standby controller. Each cold standby controller is connected to a power management unit (PMU), a clock controller, a power domain controller, and a task scheduler via a control link. The task scheduler is then connected to the interrupt controller.

[0183] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0184] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiments of the cold standby control method for any of the processing cores described above when running.

[0185] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0186] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the embodiments of the cold standby control method for any of the processing cores described above.

[0187] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the cold standby control method embodiments of any of the above-described processing cores.

[0188] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0189] The foregoing has provided a detailed description of the cold standby control method, cold standby controller, integrated circuit, storage medium, and program product for processing cores provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A cold standby control method for processing nuclear cores, characterized in that, The method is executed by a cold standby controller, and the method includes: During the current evaluation period, the operating status information of the target processing core corresponding to the cold standby controller is collected. The operating status information includes the idle clock cycle ratio and instruction activity of the target processing core. The idle clock cycle ratio is the ratio of the number of idle clock cycles to the number of clock cycles included in the first time window. The instruction activity is the ratio of the number of valid instructions submitted by the target processing core to the number of clock cycles included in the second time window. The operating status information is evaluated using a preset scoring rule to obtain the target score of the target processing core in the current evaluation period, wherein the preset scoring rule includes a first weighting coefficient and a second weighting coefficient. If the scores corresponding to the target processing core for a consecutive preset number of cycles all fall within the preset score threshold range, the interrupt flag of the target processing core is read from the interrupt controller. Read the task allocation flag of the target processing core from the task scheduler; If the interrupt flag is used to indicate that there is no interrupt request corresponding to the target processing core in the interrupt controller, and the task allocation flag is used to indicate that there is no pending task corresponding to the target processing core in the task scheduler, then the target processing core is determined to meet the cold standby condition. or, If the interrupt flag is used to indicate that there is an interrupt request corresponding to the target processing core in the interrupt controller, or the task allocation flag is used to indicate that there is a pending task corresponding to the target processing core in the task scheduler, then the target processing core does not meet the cold standby condition. If the target processing core is determined to meet the cold standby conditions, a cold standby switch operation is performed on the target processing core; The step of evaluating the operating status information using preset scoring rules to obtain the target score of the target processing core in the current evaluation period includes: The first sub-score is determined based on the idle clock cycle ratio and the first weighting coefficient; The second sub-score is determined based on the instruction activity level and the second weighting coefficient; Based on the first sub-score and the second sub-score, determine the target score of the target processing core in the current evaluation period; The step of performing a cold standby switch operation on the target processing core when it is determined that the target processing core meets the cold standby conditions includes: A cold backup preparation notification is sent to the target processing core, wherein the cold backup preparation notification is used to instruct the target processing core to perform a cold backup preparation operation, the cold backup preparation operation includes saving the context information corresponding to the target processing core to the target memory, performing a dirty data write-back operation and a cache invalidation operation on the target cache corresponding to the target processing core, and the target cache is a level 1 data cache; Upon receiving the cold standby completion notification from the target processing core, the main clock signal and main power domain corresponding to the target processing core are turned off. The cold standby completion notification is used to indicate that the target processing core has completed the cold standby preparation operation.

2. The cold standby control method for processing cores according to claim 1, characterized in that, Turning off the main clock signal corresponding to the target processing core includes: A cold standby switch notification corresponding to the target processing core is sent to the clock controller, wherein the cold standby switch notification is used to instruct the clock controller to turn off the master clock signal corresponding to the target processing core.

3. The cold standby control method for processing cores according to claim 1 or 2, characterized in that, Shutting down the main power domain corresponding to the target processing core includes: Send a cold standby switch notification corresponding to the target processing core to the power domain controller, wherein the cold standby switch notification is used to instruct the power domain controller to shut down the main power domain corresponding to the target processing core.

4. The cold standby control method for processing cores according to claim 1 or 2, characterized in that, After determining that the target processing core meets the cold standby conditions and performing a cold standby switch operation on the target processing core, the method further includes: After determining that a wake-up event corresponding to the target processing core has occurred, a wake-up operation is performed on the target processing core.

5. The cold standby control method for processing cores according to claim 4, characterized in that, The wake-up event includes one or more of the following events: The detected interrupt flag is used to indicate that there is an interrupt request in the interrupt controller corresponding to the target processing core; The detected task allocation flag is used to indicate that the task scheduler has a task to be processed corresponding to the target processing core; A bus access request corresponding to the target processing core was detected. Input / output transaction requests corresponding to the target processing core were detected; A memory transfer request corresponding to the target processing core was detected.

6. The cold standby control method for processing cores according to claim 4, characterized in that, The step of performing a wake-up operation on the target processing core after determining that a wake-up event corresponding to the target processing core has occurred includes: The main clock signal and main power domain corresponding to the target processing core are started. After the main clock signal and the main power domain are ready, the target processing core loads the context information from the target memory and performs the operation corresponding to the wake-up event.

7. The cold standby control method for processing cores according to claim 1 or 2, characterized in that, The step of determining the target score of the target processing core in the current evaluation period based on the first sub-score and the second sub-score includes: in, Score the target. The first weighting coefficient, This is the second weighting coefficient. The percentage of idle clock cycles. The number of idle clock cycles, The number of clock cycles included in the first time window. The first sub-score value, The activity level of the instruction. The number of valid instructions submitted. The number of clock cycles included in the second time window. This is the second sub-score.

8. The cold standby control method for processing cores according to claim 1, characterized in that, The current evaluation period includes a greater number of clock cycles than the first time window, the first time window includes a greater number of clock cycles than the second time window, and the second time window is a sliding time window.

9. The cold standby control method for processing cores according to claim 1 or 2, characterized in that, The method further includes: The state corresponding to the target processing core is marked as cold standby state.

10. A cold standby controller, characterized in that, The cold standby controller is used to execute the cold standby control method for the processing core as described in any one of claims 1 to 9, wherein the cold standby controller comprises: The operation status collector is used to collect the operation status information of the target processing core corresponding to the cold standby controller during the current evaluation cycle; and transmit the operation status information to the scoring calculator. The scoring calculator is used to evaluate the operating status information using preset scoring rules to obtain the target score of the target processing core in the current evaluation cycle; and to transmit the target score to the status criterion. The state criterion is used to trigger a cold standby request when it is determined that the scores corresponding to the target processing core for a consecutive preset number of cycles all fall within the preset score threshold range; and to send the cold standby request to the state controller. The state controller is configured to, upon receiving the cold standby request, read the interrupt flag of the target processing core from the interrupt controller; read the task allocation flag of the target processing core from the task scheduler; determine whether the target processing core meets the cold standby conditions based on the interrupt flag and the task allocation flag; and perform a cold standby switchover operation on the target processing core if it is determined that the target processing core meets the cold standby conditions.

11. The cold standby controller according to claim 10, characterized in that, The cold standby controller further includes a listener / wake-up device; the listener / wake-up device is used for: Upon detecting a wake-up event corresponding to the target processing core, a wake-up signal is sent to the state controller; The state controller is further configured to: Upon receiving the wake-up signal, a wake-up operation is performed on the target processing core.

12. An integrated circuit, characterized in that, include: At least one cold standby controller is used to execute the cold standby control method for the processing core as described in any one of claims 1 to 9; At least one processing core; One of the cold standby controllers is connected to its corresponding processing core.

13. The integrated circuit according to claim 12, characterized in that, Any one of the aforementioned cold standby controllers is specifically used for: Send a cold standby preparation notification to the processing core corresponding to itself; Any of the aforementioned processing cores is further configured to: After receiving a cold standby preparation notification from the cold standby controller corresponding to itself, it saves the context information corresponding to itself to the target memory. Perform dirty data write-back and cache invalidation operations on the target cache corresponding to itself, wherein the target cache is a first-level data cache.

14. The integrated circuit according to claim 13, characterized in that, Any of the aforementioned cold standby controllers is further configured to: Upon detecting a wake-up event of its corresponding processing core, the system performs a wake-up operation on the corresponding processing core. Any of the aforementioned processing cores is further configured to: Upon being awakened, it reads the context information corresponding to itself from the target memory and performs the operation corresponding to the wake-up event.

15. The integrated circuit according to claim 12 or 13, characterized in that, The integrated circuit further includes a power domain controller; the power domain controller is further configured to: Upon receiving a cold standby switch notification from the status controller in any of the cold standby controllers, the power supply to the running status collector, scoring calculator, status criterion unit, and status controller in the cold standby controller is cut off, while the power supply to the target memory and the listening wake-up unit in the cold standby controller is maintained.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by the cold standby controller, implements the steps of the cold standby control method for the processing core as described in any one of claims 1 to 9.

17. A computer program product, characterized in that, The computer program product includes a computer program, wherein when the computer program is executed by a processor, it implements the steps of the cold standby control method for the processing core as described in any one of claims 1 to 9.

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