Method for integrating bipolar transistor with small-line-width complementary metal oxide semiconductor

Abstract

The invention provides a method for integrating a bipolar transistor with a small-line-width complementary metal oxide semiconductor. The method comprises the following steps: depositing a first protective dielectric layer on a semiconductor substrate on which a CMOS device and a device isolation structure are formed; performing high-speed device ion implantation on the bipolar transistor region by taking the first protective dielectric layer as an implantation protective layer; and then, depositing a second protective dielectric layer on the first protective dielectric layer. According to the invention, the deposition of the protective dielectric layer is divided into two steps, and the thin layer deposited in the first step effectively solves the problems of ion implantation channel effect and photoresist pouring; and the layer deposited in the second step is overlapped with the first layer to form a thickened composite protection layer, so that the window of the subsequent etching process is obviously enlarged. According to the method, a low-temperature process is adopted, the thermal budget is controlled, and the stability and the yield of the small-line-width BiCMOS process are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors. Background Technology

[0002] In semiconductor integrated circuits, BiCMOS technology combines the advantages of bipolar transistors and CMOS transistors, enabling high speed, high drive capability, and low power consumption performance. Therefore, it has been widely used in radio frequency (RF) and high-performance analog mixed-signal circuits.

[0003] In traditional BiCMOS integration processes, such as CMOS process platforms with a linewidth of 0.18 micrometers (μm), high-speed devices such as heterojunction bipolar transistors are typically integrated with CMOS devices. In this type of process, high-speed device ion implantation (HS IMP) usually utilizes the screen oxide layer of the source / drain ion implantation (S / D IMP) of the CMOS device as its own implantation screening layer. One of the purposes of this high-speed device ion implantation is to implant impurities into the bottom of the shallow trench isolation (STI) structure to achieve electrical connection with the pre-formed N-type buried layer (NBL), thereby reducing collector resistance and improving the device's RF performance. After ion implantation, the screen oxide layer is removed, and a new protective oxide layer, such as high-temperature oxide (HTO) formed using a furnace tube process, is then deposited to protect the CMOS device.

[0004] However, with the continuous evolution of semiconductor technology, the feature size of CMOS processes has been shrinking, reaching technology nodes such as 55 nanometers and even smaller. When the aforementioned traditional BiCMOS integration method is applied to this small linewidth CMOS process, the inventors have discovered the following technical problems that urgently need to be solved:

[0005] 1. Significant channel effect during implantation: In small-linewidth CMOS processes, to control junction depth, source / drain ion implantation is very shallow, and the screening oxide layer is typically only a very thin native oxide layer. If the traditional method is directly used as the screening layer for ion implantation in high-speed devices, the channel effect generated during ion implantation cannot be effectively suppressed. This makes it difficult to accurately control the concentration and distribution profile of implanted impurities, affecting device performance and consistency.

[0006] 2. Narrow photoresist process window: In the photolithography step of high-speed device ion implantation, when the photoresist (PR) is directly coated on the hydrophobic silicon surface or the surface of an extremely thin natural oxide layer, poor adhesion between the photoresist and the substrate is prone to occur at the edge of the pattern (such as the CD bar position), resulting in the "photoresist peeling" phenomenon (i.e., the photoresist pattern peeling or collapse), which seriously affects the pattern fidelity and process yield of subsequent implantation.

[0007] 3. Thermal Budget Constraints: Traditional processes use high-temperature oxide (HTO) deposition temperatures to protect CMOS devices. For small-linewidth CMOS devices, an excessively high thermal budget can lead to unintended diffusion of impurities in areas such as source / drain regions, altering the device's doping distribution and ultimately causing performance degradation. Therefore, low-temperature processes (such as low-temperature chemical vapor deposition, CVD) are required to deposit the protective layer.

[0008] 4. Insufficient process window for subsequent etching: In subsequent process flows, it is usually necessary to etch the protective layer, such as in the "BP etch" step. If the thickness of the low-temperature protective layer used is insufficient, the process window for this etching step will be very narrow, which can easily lead to under-etching or over-etching, thereby affecting the device yield.

[0009] In summary, the existing technology lacks a technical solution that can effectively address the problems encountered when integrating bipolar transistors in small linewidth CMOS processes, such as ion implantation channel effect, photoresist peeling, thermal budget overrun, and insufficient etching window. Summary of the Invention

[0010] The technical problem to be solved by the present invention is that the existing technology has problems such as significant ion implantation channel effect, easy photoresist peeling, excessively high process thermal budget and insufficient subsequent etching process window when integrating bipolar transistors into a small linewidth CMOS process platform.

[0011] To address the aforementioned technical problems, this invention provides a method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors, comprising the following steps:

[0012] Step 1: Deposit a first protective dielectric layer on a semiconductor substrate on which complementary metal-oxide-semiconductor devices and device isolation structures are formed;

[0013] Step 2: Using the first protective dielectric layer as the implantation protective layer, perform high-speed device ion implantation on the region of the bipolar transistor;

[0014] Step 3: Deposit a second protective medium layer on the first protective medium layer.

[0015] Preferably, the device isolation structure is a shallow trench isolation structure.

[0016] Preferably, in step one, the first protective medium layer is an oxide layer.

[0017] Preferably, in step one, the oxide layer is formed by chemical vapor deposition.

[0018] Preferably, in step one, the thickness of the first protective dielectric layer is 80 to 120 angstroms.

[0019] Preferably, in step two, before performing the high-speed device ion implantation, the method further includes:

[0020] A photoresist mask is formed and patterned on the first protective dielectric layer, the photoresist mask having openings that expose the regions of the bipolar transistor;

[0021] The high-speed device ion implantation is performed through the opening.

[0022] Preferably, in step two, the implantation energy and dose of the high-speed device ion implantation are such that the implanted impurities are electrically connected to the buried layer in the semiconductor substrate.

[0023] Preferably, in step three, the second protective medium layer is an oxide layer.

[0024] Preferably, in step three, the oxide layer is formed by chemical vapor deposition.

[0025] Preferably, in step three, the thickness of the second protective dielectric layer is 280 angstroms to 320 angstroms.

[0026] Preferably, the linewidth of the small-linewidth complementary metal-oxide semiconductor is 55 nanometers or less.

[0027] As described above, the method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to the present invention has the following beneficial effects:

[0028] This invention divides the deposition of the protective dielectric layer into two steps. The first protective dielectric layer deposited in the first step has a moderate thickness, which can effectively serve as the implantation protective layer for ion implantation of high-speed devices, suppress channel effects, improve wafer surface characteristics, solve the problem of photoresist peeling, and broaden the process window.

[0029] The present invention deposits a second protective dielectric layer directly on the first protective dielectric layer, forming a thickened composite protective layer that provides sufficient process margin for subsequent etching steps and avoids the problem of insufficient etching window caused by an excessively thin protective layer.

[0030] This invention uses low-temperature processes such as chemical vapor deposition to replace the traditional high-temperature furnace tube process, which effectively reduces the thermal budget, avoids adverse effects on the doped regions already formed in small-linewidth CMOS devices, and ensures the electrical performance of the devices. Attached Figure Description

[0031] Figure 1 The diagram shows a process flow diagram of one method of the present invention;

[0032] Figure 2 The diagram shown is a cross-sectional view of the structure before the deposition of the first protective medium layer in an embodiment of the present invention.

[0033] Figure 3 The diagram shows a cross-sectional view of the structure after the deposition of the first protective medium layer in an embodiment of the present invention.

[0034] Figure 4 The diagram shows a cross-sectional view of the structure after ion implantation of a high-speed device in an embodiment of the present invention.

[0035] Figure 5 The diagram shown is a cross-sectional view of the structure after the deposition of the second protective medium layer in an embodiment of the present invention. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Figure 1 This is a flowchart illustrating a method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to an embodiment of the present invention. Figures 2 to 5 This is a schematic cross-sectional view of a semiconductor structure at different manufacturing stages according to an embodiment of the present invention.

[0038] This invention provides a method for integrating small-linewidth complementary metal-oxide-semiconductor (CMOS) bipolar transistors. By dividing the deposition of the protective dielectric layer into two steps and performing a critical ion implantation step between the two deposition steps, this method ingeniously solves several technical challenges in small-linewidth BiCMOS process integration.

[0039] Please see Figure 1 The method provided in this embodiment of the invention mainly includes the following steps:

[0040] Step 1: Deposit a first protective dielectric layer on a semiconductor substrate on which complementary metal-oxide-semiconductor devices and device isolation structures are formed;

[0041] Step 2: Using the first protective dielectric layer as the implantation protective layer, perform high-speed device ion implantation on the region of the bipolar transistor;

[0042] Step 3: Deposit a second protective medium layer on the first protective medium layer.

[0043] The following will combine Figures 2 to 5 The above steps will be explained in detail.

[0044] Please see Figure 2 The figure illustrates a semiconductor structure prior to the execution of the method of the present invention. This structure is built on a semiconductor substrate 101 and is divided into an HBT region for forming a bipolar transistor (HBT) and a CMOS region for forming a complementary metal-oxide-semiconductor (CMOS) device. In the HBT region of the semiconductor substrate 101, a buried layer 102 is pre-formed. An epitaxial layer 103 is formed on the semiconductor substrate 101, and a device isolation structure 104 is formed in the epitaxial layer 103 to isolate different active regions. In the CMOS region, CMOS devices have been formed, including, for example, a PMOS transistor located on an N-well 105 and an NMOS transistor located on a P-well 106, wherein a deep N-well 107 may be further included below the P-well 106. The field-effect transistor 108 shown in the figure represents the substantially formed CMOS device structure. The semiconductor substrate 101 can be a conventional silicon (Si) substrate, or a silicon-on-insulator (SOI) substrate, a silicon-germanide (SiGe) substrate, or other suitable semiconductor material substrate.

[0045] In some embodiments, the device isolation structure 104 is a shallow trench isolation structure. Shallow trench isolation structures are typically formed by etching trenches on a semiconductor substrate, followed by filling with a dielectric material (e.g., silicon oxide deposited by high-density plasma chemical vapor deposition) and planarizing with chemical mechanical polishing (CMP).

[0046] Next, proceed to step one. For example... Figure 3 As shown, in Figure 2 Based on the structure shown, a first protective dielectric layer 109 is deposited on the semiconductor substrate 101. The first protective dielectric layer 109 uniformly covers the surfaces of the HBT region and the CMOS region. This step provides a high-quality implantation protection layer and photoresist adhesion layer for subsequent high-speed device ion implantation.

[0047] In some embodiments, in step one, the first protective dielectric layer 109 is an oxide layer. Specifically, it may be silicon dioxide (SiO2), which provides good dielectric insulation properties and a buffering effect against ion implantation.

[0048] In some embodiments, in step one, the oxide layer is formed by chemical vapor deposition.

[0049] In some embodiments, in step one, the thickness of the first protective dielectric layer 109 is 80 to 120 angstroms. For example, a thickness of about 100 angstroms can be deposited. This thickness can effectively serve as an implantation protection layer for subsequent high-speed device ion implantation, buffering the energy of implanted ions to prevent lattice damage to the substrate surface, and can also significantly suppress channel effects caused by the regular arrangement of crystals, ensuring good consistency and controllability of the concentration and distribution profile of implanted impurities. In addition, the presence of this first protective dielectric layer transforms the originally hydrophobic silicon surface into a hydrophilic surface, significantly improving the adhesion of subsequent photoresist coating, thereby effectively avoiding photolithography defects such as photoresist peeling at pattern edges (such as CD bar positions), and widening the photolithography process window.

[0050] Then, proceed to step two. For example... Figure 4 As shown, high-speed device ion implantation is performed on the region of the bipolar transistor (HBT) using the first protective dielectric layer 109 as the implantation protective layer to form the implantation region 111.

[0051] In some embodiments, in step two, prior to performing high-speed device ion implantation, the method further includes: forming and patterning a photoresist mask 110 on a first protective dielectric layer 109, the photoresist mask 110 having openings that expose bipolar transistor regions; wherein high-speed device ion implantation is performed through the openings. The formation of the photoresist mask follows a standard photolithography process flow, which can precisely define the ion implantation region, doping only the target region, such as forming the collector deep contact region of a heterojunction bipolar transistor (HBT).

[0052] In some embodiments, in step two, the implantation energy and dosage of high-speed device ion implantation enable the implanted impurities to electrically connect with the buried layer 102 within the semiconductor substrate 101. By precisely controlling the implantation energy, it is ensured that the doped ions reach a predetermined depth, thereby achieving a reliable electrical connection with the pre-formed buried layer 102. This effectively reduces the collector resistance (Rc) of the bipolar transistor, thereby improving the device's current drive capability and high-frequency operating characteristics (RF performance). The type of impurity implanted is selected according to the type of device to be formed; for example, for an NPN transistor, N-type dopants such as phosphorus (P) or arsenic (As) can be implanted.

[0053] Finally, step three is performed. After ion implantation and removal of the photoresist mask 110, a second protective dielectric layer 112 is deposited on the first protective dielectric layer 109, forming a structure as shown in the figure. Figure 5 The final structure shown is an example of how a two-step deposition method not only reduces process complexity but also creates a thicker composite protective layer.

[0054] In some embodiments, in step three, the second protective dielectric layer 112 is an oxide layer. Specifically, it can be silicon dioxide. This second protective dielectric layer and the first protective dielectric layer can be deposited using the same method and materials to ensure good interlayer adhesion.

[0055] In some embodiments, the first protective dielectric layer 109 and / or the second protective dielectric layer 112 are both oxide layers formed by chemical vapor deposition (CVD). CVD is a process that converts gaseous reactants (precursors) into solid thin films through chemical reactions and deposits them onto the surface of a substrate (e.g., semiconductor substrate 101). In this invention, the main advantage of using CVD is its ability to form high-quality dielectric layers at relatively low temperatures and to precisely control the thickness, uniformity, and stress of the thin films, which is crucial for protecting the underlying small-linewidth CMOS devices (e.g., field-effect transistor 108).

[0056] Specifically, various CVD techniques can be used to achieve the dielectric layer deposition in this invention. Plasma-enhanced chemical vapor deposition (PECVD) is a preferred embodiment because it utilizes plasma generated by a radio frequency (RF) or microwave source to provide the energy required for the chemical reaction, rather than relying entirely on thermal energy. This allows the reaction to proceed efficiently at lower substrate temperatures (e.g., 200°C to 450°C), thereby minimizing the thermal budget. In addition to PECVD, other low-temperature CVD techniques are also applicable, such as subatmospheric chemical vapor deposition (SACVD), which is typically performed at pressures slightly below atmospheric pressure and moderate temperatures, enabling the formation of films with excellent step coverage and conformability, particularly suitable for filling complex morphologies. In scenarios with extreme requirements for thickness control and conformability, atomic layer deposition (ALD) can also be used. ALD grows films atomically layer by layer through self-limiting surface chemical reactions, enabling uniform thickness and coverage of high aspect ratio structures.

[0057] When depositing oxide layers (such as silica), different precursor combinations can be selected based on a comprehensive consideration of film quality, deposition rate, and cost. The silicon source can be a non-organosilane, such as silane (SiH4) or dichlorosilane (SiH2Cl2), or an organosilane source, such as tetraethoxysilane (TEOS) or octamethylcyclotetrasiloxane (OMCTS). TEOS is widely used due to its high chemical stability, low toxicity, and excellent film quality. The oxygen source can be an oxidizing gas such as oxygen (O2), ozone (O3), or nitrous oxide (N2O). For example, using a combination of TEOS and O3 can yield dense and flat silica films at lower temperatures. Furthermore, inert gases, such as nitrogen (N2), argon (Ar), or helium (He), are typically introduced during the process as carrier or dilution gases to stabilize the plasma, regulate the reaction rate, and improve film uniformity. By flexibly selecting and optimizing these CVD technology types and precursor materials, the physical and chemical properties of the protective media layer (e.g., the first protective media layer 109 and the second protective media layer 112) can be precisely customized to best meet the requirements of the integrated process.

[0058] In some embodiments, in step three, the thickness of the second protective dielectric layer 112 is 280 to 320 angstroms. For example, a thickness of approximately 300 angstroms can be deposited. After the second protective dielectric layer 112 is deposited, it, together with the underlying first protective dielectric layer 109, constitutes a composite protective layer with a significantly increased total thickness, for example, a total thickness of approximately 400 angstroms. This thickened protective layer provides highly favorable conditions for subsequent process steps (e.g., the "BP etch" step, which requires etching the protective layer to form contact holes). During etching, a sufficiently thick protective layer can act as a more corrosion-resistant mask, thereby providing a wider process window, allowing for longer over-etching times, without damaging the active regions of the CMOS device due to premature etching penetration of the protective layer. This directly improves the stability of subsequent etching processes and overall product yield.

[0059] In some embodiments, the linewidth of the small-linewidth complementary metal-oxide-semiconductor (CMOS) is 55 nanometers or smaller. For example, the method of the present invention can be applied to semiconductor manufacturing technology nodes such as 55 nanometers, 40 nanometers, 28 nanometers, and more advanced nodes. In these advanced nodes, due to the continuous shrinkage of device size, more stringent requirements are placed on the control of thermal budgets, the management of process windows, and the control of defects, thus making the technical advantages brought by the present invention more prominent.

[0060] In summary, this invention proposes a novel method for integrating small-linewidth CMOS bipolar transistors. By dividing the deposition of the protective layer into two steps, the thin protective layer deposited in the first step cleverly solves the problems of ion implantation protection and photoresist adhesion. The second step deposits a thicker total protective layer, addressing the issue of insufficient etching window in subsequent processes. Furthermore, the entire process employs a low-temperature deposition process, effectively controlling the thermal budget. This method features a simple process flow, strong compatibility, and can significantly improve the manufacturing yield and device performance of high-performance BiCMOS chips at advanced process nodes.

[0061] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors, characterized in that, At least including: Step 1: Deposit a first protective dielectric layer on a semiconductor substrate on which complementary metal-oxide-semiconductor devices and device isolation structures are formed; Step 2: Using the first protective dielectric layer as the implantation protective layer, perform high-speed device ion implantation on the region of the bipolar transistor; Step 3: Deposit a second protective medium layer on the first protective medium layer.

2. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 1, characterized in that: The device isolation structure is a shallow trench isolation structure.

3. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 1, characterized in that: In step one, the first protective medium layer is an oxide layer.

4. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 3, characterized in that: In step one, the oxide layer is formed by chemical vapor deposition.

5. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 1, characterized in that: In step one, the thickness of the first protective dielectric layer is 80 to 120 angstroms.

6. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 1, characterized in that: In step two, prior to performing the high-speed device ion implantation, the method further includes: forming and patterning a photoresist mask on the first protective dielectric layer, the photoresist mask having openings that expose regions of the bipolar transistor; wherein the high-speed device ion implantation is performed through the openings.

7. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 6, characterized in that: In step two, the implantation energy and dose of the high-speed device ion implantation are such that the implanted impurities are electrically connected to the buried layer in the semiconductor substrate.

8. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 3, characterized in that: In step three, the second protective medium layer is an oxide layer.

9. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 1, characterized in that: In step three, the thickness of the second protective dielectric layer is 280 angstroms to 320 angstroms.

10. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 7, characterized in that: In step three, the oxide layer is formed by chemical vapor deposition.

11. The method for integrating small-linewidth complementary metal-oxide-semiconductor bipolar transistors according to claim 1, characterized in that: The linewidth of the small-linewidth complementary metal-oxide semiconductor is 55 nanometers or less.

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