Hybrid architecture analog-to-digital converter and control method thereof

Abstract

The invention provides a hybrid architecture analog-to-digital converter and a control method thereof. The analog-to-digital converter comprises an M-bit SAR ADC, a loop filter, a multiplexing control circuit and a digital logic circuit, an input signal is input into the loop filter to output a signal to be quantized; the multiplexing control circuit drives the SAR ADC to perform N-bit conversion on the to-be-quantized signal based on the first sampling signal and the first quantized signal to obtain an N-bit first quantized result; the multiplexing control circuit drives the SAR ADC to perform M-bit conversion on the input signal based on the second sampling signal and the second quantization signal to obtain an M-bit second quantization result; the digital logic circuit outputs an M-bit digital output result according to the first quantization result and the second quantization result. Structural multiplexing of the SAR ADC is achieved through the multiplexing control circuit, additional circuit design is not needed, the problem that the circuit occupies the area is effectively solved, and the overall power consumption condition is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of analog-to-digital converter technology, and in particular to a hybrid architecture analog-to-digital converter and its control method. Background Technology

[0002] Hybrid-architecture analog-to-digital converters (ADCs) combine two or more ADC architectures to effectively address the limitations of traditional single-architecture ADCs in terms of power consumption, area, or accuracy. Zoom ADCs combine a low-power Successive-Approximation Register (SAR) ADC with a high-precision Delta-Sigma modulator (Δ∑M), achieving both low power consumption and high accuracy. The SAR ADC acts as the first-stage coarse quantizer, and its quantization result, along with the quantization result in the second-stage fine quantizer Δ∑M, determines the feedback reference voltage of Δ∑M. The range of the feedback reference voltage is typically chosen to be the three least significant bits (LSB) of the coarse quantizer. To fully utilize this three LSB feedback reference voltage range and improve the overall accuracy of the Zoom ADC, the quantizer bit width of Δ∑M is often chosen to be 2 bits. However, 2-bit quantizers with a Δ∑M value are typically designed using a flash quantizer structure, which requires an additional reference voltage resistor network and three comparators. The resistors in the reference voltage resistor network are often chosen to be large, in the hundreds of kΩ range, to reduce the overall quiescent current of the resistor network. Furthermore, to suppress kickback noise, the top and bottom comparators typically employ a comparator structure with a continuous-time (CT) preamplifier, while the middle comparator often uses a comparator structure with a dynamic preamplifier. Therefore, this 2-bit quantizer using a flash quantizer structure not only introduces higher design complexity but also increases quiescent power consumption and circuit area overhead. Summary of the Invention

[0003] The purpose of this disclosure is to provide a hybrid architecture analog-to-digital converter and its control method to solve the problems of complex design, high static power consumption and large circuit area of ​​the finer converter in the prior art.

[0004] The embodiments of this disclosure employ the following technical solution: a hybrid architecture analog-to-digital converter, comprising: an M-bit SARADC, a loop filter, a multiplexing control circuit, and a digital logic circuit; wherein, an input signal is input to the loop filter to cause the loop filter to output a signal to be quantized; the multiplexing control circuit drives the SARADC to perform an N-bit conversion on the signal to be quantized based on a first sampling signal and a first quantization signal to obtain an N-bit first quantization result; the multiplexing control circuit drives the SARADC to perform an M-bit conversion on the input signal based on a second sampling signal and a second quantization signal to obtain an M-bit second quantization result; the digital logic circuit outputs an M-bit digital output result based on the first quantization result and the second quantization result; wherein, M and N are both positive integers, and M is greater than N.

[0005] This disclosure also provides a control method for a hybrid architecture analog-to-digital converter as described above, comprising at least: in a fine quantization stage, a multiplexing control circuit drives a SAR ADC to sample the signal to be quantized output from a loop filter according to a first sampling signal, and drives the SAR ADC to perform an N-bit conversion on the signal to be quantized according to the first quantization signal to obtain an N-bit first quantization result; in a coarse quantization stage, a multiplexing control circuit drives a SAR ADC to sample the input signal according to a second sampling signal, and drives the SAR ADC to perform an M-bit conversion on the input signal according to the second quantization signal to obtain an M-bit second quantization result; a digital logic circuit outputs an M-bit digital output result based on the first quantization result and the second quantization result; wherein M and N are both positive integers, and M is greater than N.

[0006] The beneficial effects of the embodiments disclosed herein are as follows: By reusing the control circuit to realize the structural reuse of SAR ADC, the problem of complex quantizer circuit design in traditional hybrid structure analog-to-digital converters is fundamentally solved, eliminating the need for additional circuit design. At the same time, the quantizer part of the overall circuit only requires the area of ​​SAR ADC, effectively solving the problem of circuit area occupation. In addition, by reusing SAR ADC, combined with the dynamic operation and low power consumption characteristics of SAR ADC, the overall power consumption is effectively reduced. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1This is a schematic diagram of the hybrid structure analog-to-digital converter in the first embodiment of this disclosure;

[0009] Figure 2 This is a schematic diagram of the circuit structure of the SAR ADC in the first embodiment of this disclosure;

[0010] Figure 3 This is a timing diagram of the clock signal in the first embodiment of this disclosure;

[0011] Figure 4 This is a schematic diagram of the circuit structure of the asynchronous sequential logic circuit in the first embodiment of this disclosure;

[0012] Figure 5 This is a schematic diagram of the circuit structure of the asynchronous control clock circuit in the first embodiment of this disclosure;

[0013] Figure 6 This is a circuit diagram of the Zoom ADC in the first embodiment of this disclosure;

[0014] Figure 7 This is a timing control diagram of the Zoom ADC in the first embodiment of this disclosure;

[0015] Figure 8 This is a flowchart of the control method for a hybrid architecture analog-to-digital converter in the second embodiment of this disclosure. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0017] Hybrid architecture analog-to-digital converters (ADCs) effectively address the limitations of traditional single-architecture ADCs in terms of power consumption, area, or accuracy by combining two or more ADC architectures. Zoom ADCs (Scaling ADCs) achieve both low power consumption and high accuracy by combining a low-power successive approximation register-type ADC with a high-precision Delta-Sigma modulator. In a SAR ADC, the quantization result of the first-stage coarse quantizer, together with the quantization result in the second-stage fine quantizer Δ∑M, determines the feedback reference voltage of Δ∑M. The range of the feedback reference voltage is typically chosen to be the least significant bit (LSB) voltage of the three coarse quantizers. To fully utilize this LSB feedback reference voltage range and improve the overall accuracy of the Zoom ADC, the quantizer bit width of Δ∑M is often chosen to be 2-bit. However, the 2-bit quantizer of Δ∑M is typically designed using a flash quantizer structure, which requires the introduction of an additional reference voltage resistor network and three comparators. The reference voltage resistor network typically uses large resistors in the hundreds of kΩ range to reduce the overall quiescent current of the resistor network. Furthermore, to suppress kickback noise, the top and bottom comparators usually employ comparator structures with continuous-time preamplifiers, while the middle comparators often use structures with dynamic preamplifiers. Therefore, this 2-bit quantizer using a Flash quantizer structure not only introduces higher design complexity but also increases quiescent power consumption and circuit area overhead.

[0018] The first embodiment of this disclosure provides a hybrid structure analog-to-digital converter that combines a SARADC with low power consumption and a Δ∑M with high precision, thereby achieving both low power consumption and high precision performance requirements. Figure 1 The schematic diagram of the hybrid analog-to-digital converter in this embodiment is shown. It mainly includes: an M-bit SAR ADC 10, a loop filter 20, a multiplexing control circuit 30, and a digital logic circuit 40. The M-bit SAR ADC is used to implement M-bit coarse quantization. The loop filter 20 is the main component of the Δ∑M ADC, which performs integration and noise shaping of the input signal Vin. The multiplexing control circuit 30 combines different operating signals in different precision quantization stages to drive the SAR ADC to complete the signal conversion of fine quantization and coarse quantization. Finally, the digital logic circuit 40 integrates the quantization results and outputs the digital output result.

[0019] Specifically, the input signal is fed into the loop filter 20 for integration and noise shaping, and outputs the signal to be quantized. In the subsequent fine quantization stage, the multiplexing control circuit 30 drives the SAR ADC to sample and perform N-bit conversion on the signal to be quantized based on the first sampling signal and the first quantization signal, thus completing the N-bit fine quantization acquisition and conversion of the input signal to obtain the N-bit first quantization result BS. In the coarse quantization stage, the multiplexing control circuit 30 drives the SAR ADC to perform M-bit coarse quantization acquisition and conversion on the input signal based on the second sampling signal and the second quantization signal to obtain the M-bit second quantization result K. In this embodiment, both the first quantization result and the second quantization signal are binary codes with different bit lengths. M and N are both positive integers, and M is greater than N. This ensures that the SAR ADC can perform the conventional M-bit conversion while also achieving N-bit fine quantization with a bit length less than its maximum conversion bit length. In actual implementation, M can be 4, meaning the SAR ADC is a 4-bit analog-to-digital converter, and N is 2, meaning a 2-bit fine quantization result is output through multiplexing the SAR ADC. Alternatively, the values ​​of M and N can be set according to actual conversion requirements. This embodiment does not impose any specific limitations.

[0020] Figure 2 The circuit structure diagram of the SAR ADC 10 in this embodiment is shown. This embodiment uses a 4-bit asynchronous SAR ADC architecture as an example for illustration. The SAR ADC 10 mainly includes a signal input unit 11, a sampling capacitor array 12, and a comparator unit 13. (Specific details are not provided in the original text.) Figure 2 As shown, the signal input unit in this embodiment includes at least a signal input terminal to be quantized and an input signal input terminal. Since the input signal in analog-to-digital conversion is usually differential, both the signal input terminal to be quantized and the input signal input terminal are differential inputs. The signal to be quantized includes V... INT2P and V INT2N The input signal is V IP and V IN The input terminal of the signal to be quantized is connected to the sampling capacitor array 12 through the first switch S1, and the first switch S1 is based on the first sampled signal Φ. CMP Control, in the first sampled signal Φ CMP When the signal is high, the first switch S1 closes, allowing the signal to be quantized to be input to the sampling capacitor array 12 for sampling; correspondingly, the input signal input terminal is connected to the sampling capacitor array 12 through the second switch S2, and the second switch S2 is based on the second sampling signal Φ. SAR Control, in the second sampled signal Φ SAR When the signal is high, the second switch S2 closes, allowing the input signal to be sampled by the sampling capacitor array 12. The sampling capacitor array 12 is mainly used to sample the signal to be quantized or the input signal, while the comparator unit 13 is based on the first quantized signal.CMP _ CONV The signal to be quantized is converted to output a first quantization result, and based on the second quantized signal Φ, the output is... SAR_CONV The input signal is converted to output a second quantization result. The specific implementation structure of the sampling capacitor array 12 and comparator unit 13, and their corresponding functions, can be directly controlled using the conventional sampling capacitor array and comparator structure and corresponding driving method in a SARADC to output the quantization result. This embodiment will not provide a detailed description here. Figure 2 The sampling capacitor array shown is only one specific implementation method and does not limit this embodiment.

[0021] In this embodiment, the first sampling signal Φ CMP Second sampling signal Φ SAR First quantization signal Φ CMP_CONV and the second quantization signal Φ SAR_CONV All are clock signals, and their high and low level values ​​are switched according to the actual conversion stage to control different signal sampling and conversion quantization stages. Figure 3 The timing diagram of the clock signal described above is shown. In the first sampling signal Φ CMP When the value is high, the input signal of the SAR ADC is the unquantized signal V output by the loop filter 20. INT2P and V INT2N SAR ADC is in the fine-quantization V INT2P and V INT2N During the sampling phase, the sampling capacitor array will V INT2P and V INT2N Sampled onto the array; in the second sampled signal Φ SAR When the signal is high, the input to the SARADC is the differential input signal V. IP and V IN SARADC is in coarse quantization V IP and V IN During the sampling phase, the sampling capacitor array will V IP and V IN Sampled onto the array.

[0022] The multiplexing control circuit 30 is the core part of the SAR ADC multiplexing in this embodiment. It mainly includes an asynchronous timing logic circuit 31 for determining the number of bits completed in the current quantization stage, and an asynchronous control clock circuit 32 for outputting an asynchronous control clock according to the number of bits completed in the current quantization stage to control the working state of the comparator unit.

[0023] Figure 4A schematic diagram of the asynchronous sequential logic circuit is shown, which mainly includes: a NAND gate, a first delay unit Delay1, M D flip-flops, and an OR gate; wherein, the two input terminals of the NAND gate are respectively connected to the differential output terminal of the comparator unit 13, the output terminal of the NAND gate is connected to the input terminal of the first delay unit Delay1, the output terminal of the first delay unit Delay1 is connected to the clock signal CLK terminal of all D flip-flops, all D flip-flops are connected in series, the D terminal of the i-th D flip-flop is connected to the Q terminal of the (i-1)-th D flip-flop, the D terminal of the 1st D flip-flop is connected to the power supply voltage, i = 1, 2, ..., M; the first input terminal of the OR gate is connected to the first sampling signal, the second input terminal of the OR gate is connected to the second sampling signal, and the output terminal of the OR gate is connected to the reset signal RST terminal of all D flip-flops. Figure 4 Taking a 4-bit SAR ADC as an example, i.e., M = 4, it includes a total of 4 D flip-flops. The signals output by the Q terminals of D1 to D4 are used to characterize the quantization completion status from the most significant bit (MSB) to the least significant bit (LSB).

[0024] During the quantization stage (whether it is the quantization of the signal to be quantized or the quantization of the input signal), the output of comparator unit 13 is connected to a NAND gate. The output VALID of the NAND gate represents the valid signal after one comparison is completed. The VALID signal is input to the clock input terminal CLK of the first D flip-flop through the first delay unit Delay1 composed of a chain of inverters. When the first comparison is completed, the power supply voltage VDD of the D terminal of the D flip-flop is transmitted to the Q terminal signal CLK[3], indicating that the most significant bit has been quantized. The operation of the subsequent three D flip-flops is similar. The signal level output of each D flip-flop Q terminal reflects the quantization result of different bit numbers. The first sampling signal Φ CMP Second sampled signal Φ SAR The input of the OR gate is connected to the clock signal CLKS, which controls the reset terminal RST of the D flip-flop. When CLKS is high, the D flip-flop is reset, indicating that the SAR ADC is in the sampling stage and the asynchronous sequential logic circuit is not working.

[0025] Figure 5 A schematic diagram of the asynchronous control clock circuit is shown, which includes at least a three-input NOR gate, a second delay unit Delay2, a third switch S3, and a fourth switch S4. The first input of the three-input NOR gate is connected to the output of the OR gate. The Q-terminus of the Nth D flip-flop is connected to the second input of the three-input NOR gate through the third switch S3. The third switch S3 is based on the first quantization signal Φ. CMP_CONVControl: The Q input of the Mth D flip-flop is connected to the second input of a three-input NOR gate via a fourth switch S4. The fourth switch S4 is based on the second quantization signal Φ. SAR_CONV The third input of the three-input NOR gate is connected to the output of the NAND gate, and the output of the three-input NOR gate is connected to the input of the second delay unit Delay2. The output of the second delay unit Delay2 outputs an asynchronous control clock CLKC to control the working state of the comparator unit 13.

[0026] Specifically, in this embodiment, the value of N is 2, so the output CLK[2] of the second D flip-flop and the output CLK[0] of the fourth D flip-flop are taken as the signal input to the second input terminal of the three-input NOR gate. CLK[2] is input through Φ CMP_CONV Controlling the third switch S3 to achieve connection, CLK[0] through Φ SAR_CONV The fourth switch S4 is used to connect the circuit. When Φ SAR_CONV When the value is high, the SARADC is at the differential input signal V. IP and V IN During the conversion phase, i.e., the input signal is coarsely quantized to 4 bits, CLK[0] is connected to the second input of the three-input NOR gate. When the LSB quantization of the 4-bit signal is completed, CLK[0] is pulled high, CLKC is set to 0, the asynchronous sequential logic circuit stops working, and the 4-bit coarse quantization of the input signal is completed; similarly, when Φ CMP_CONV When it is high, the SAR ADC is at V INT2P and V INT2N During the conversion phase, the 2-bit quantization of the signal to be quantized is performed. CLK[2] is connected to the second input of the three-input NOR gate. When the LSB quantization of the 2-bit signal is completed, CLK[2] is pulled high, CLKC is set to 0, the asynchronous sequential logic circuit stops working, and the 2-bit fine quantization of the signal to be quantized is completed.

[0027] In this embodiment, the digital logic circuit 40 outputs an M-bit digital output result based on the first quantization result and the second quantization result. Specifically, the digital logic circuit 40 first converts the second quantization result into a first decimal number; then, based on the adjustment number corresponding to the first quantization result, it determines the sum of the first decimal number and the adjustment number to obtain a second decimal number; finally, it converts the second decimal number into a binary digital output result D. OUTThis is the analog-to-digital conversion result. It should be noted that the adjustment number corresponding to the first quantization result can be preset. For example, for the first quantization result of 2 bits, when it is 11, the corresponding adjustment number is the decimal number 2; when it is 10, the corresponding adjustment number is the decimal number 1; when it is 01, the corresponding adjustment number is the decimal number 0; and when it is 00, the corresponding adjustment number is the decimal number -1.

[0028] In some embodiments, the hybrid architecture analog-to-digital converter further includes an N-bit feedback DAC for outputting a feedback voltage V. DAC The input signal is determined by combining the input signal with the input signal, wherein the input terminal of the feedback DAC is connected to the input signal, and the output terminal of the feedback DAC is connected to the input terminal of the loop filter. Furthermore, the digital logic circuit is also used to adjust the capacitor array of the feedback DAC according to the digital output result to adjust the feedback voltage V. DAC The value is used to obtain the output result of the loop filter.

[0029] The following description uses a specific example of a hybrid architecture analog-to-digital converter to further illustrate this embodiment. Specifically, this analog-to-digital converter is a Zoom ADC that combines a coarse quantization 4-bit SAR ADC with fine quantization (2-bit Δ∑M) using quantizer multiplexing technology. Its circuit diagram is shown below. Figure 6 As shown, its timing control diagram is as follows: Figure 7 As shown, the left side of the loop filter 20 is connected to the input signal V. IP and V IN The dashed box section corresponds to a 4-bit feedback DAC, and Figure 6 The specific circuit structure of the 4-bit SAR ADC, multiplexing control circuit, and digital logic circuit is not shown in the diagram. Figure 6 The 2-bit quantizer marked by the dashed box on the right is used to represent the 2-bit fine quantization stage implemented by driving the 4-bit SAR ADC through the multiplexing control circuit. The first quantization result BS is output to the digital logic circuit.

[0030] Specifically, the loop filter (LF) contains two switched-capacitor integrators, powered by two non-overlapping clock phases Φ1 and Φ2. 1D Φ2, Φ 2D Control, input sampling capacitor C S1 Designed to 12pF to avoid sampling thermal noise limiting SQNR, while C S1 Also serving as the feedback DAC capacitor, it consists of 16 unit capacitors. The second-stage sampling capacitor C... S2 The value is very small; the main consideration is its compatibility with other capacitors. Integrating capacitor Ci1 C i2 The values ​​are designed based on the integrator coefficients of the LF, ensuring that the operational transconductance amplifier (OTA) output does not saturate while achieving second-order noise shaping. Furthermore, the first-stage integrator employs correlated double sampling (CDS) technology to suppress low-frequency noise and offset; the sampling switch uses a bootstrap switch to improve the linearity of the sampled signal. In fact, Figure 6 The specific circuit structure of the loop filter shown can be directly implemented by referring to the conventional loop filter design of Δ∑M ADC. No specific restrictions are imposed in this embodiment.

[0031] In the actual sampling and conversion process, by multiplexing the same 4-bit asynchronous SAR ADC, the first sampled signal Φ is obtained at the clock. CMP Second sampling signal Φ SAR First quantization signal Φ CMP_CONV and the second quantization signal Φ SAR_CONV Under the control of the clock, 4-bit coarse quantization and 2-bit quantization are completed in a time-division manner. SAR , ΦΦ SAR_CONV When the rising edges arrive sequentially, the SARADC completes 4-bit coarse quantization, outputs a 4-bit digital value K, and stores it in a register. When the clock Φ... CMP Φ CMP_CONV When the rising edges arrive sequentially, the SAR ADC completes 2-bit quantization, outputs a 2-bit digital value BS, and stores it in a register. K and BS are input to the digital logic circuit, which combines K and BS to obtain the 4-bit Zoom ADC output D. OUT and D OUT The corresponding 16-bit thermometer code CTL[15:0] controls the feedback DAC capacitor C. S1 Whether the 16 unit capacitors are connected to the first-stage integrator or not, different feedback reference voltages V can be achieved. DAC The specific formula is as follows:

[0032]

[0033] Among them, V LSB,C This is the LSB voltage of the SAR ADC. Furthermore, the 16-bit thermometer code CTL[15:0] is processed using a data-weighted averaging (DWA) algorithm to reduce the nonlinear effects caused by DAC capacitor mismatch.

[0034] in addition, Figure 6The circuit shown also includes a residual feedforward path, utilizing the feedforward capacitor C. inFF and a set of binary CDACs controlled by K. resDAC A residual feedforward path is formed to generate the residual quantization error of 4-bit coarse quantization. By introducing the residual feedforward path, the leakage of residual quantization error generated by coarse quantization is reduced.

[0035] This embodiment achieves structural reuse of the SAR ADC by reusing the control circuit, fundamentally solving the problem of complex quantizer circuit design in traditional hybrid analog-to-digital converters. No additional circuit design is required, and the quantizer part of the overall circuit only needs the area of ​​the SAR ADC, effectively solving the problem of circuit area occupation. In addition, by reusing the SAR ADC, combined with the dynamic operation and low power consumption characteristics of the SAR ADC, the overall power consumption is effectively reduced.

[0036] Based on the same inventive concept, the second embodiment of this disclosure provides a control method for a hybrid architecture analog-to-digital converter according to the first embodiment of this disclosure, the flowchart of which is shown below. Figure 8 As shown, it includes at least:

[0037] S100, in the fine quantization stage, the multiplexing control circuit drives the SAR ADC to sample the signal to be quantized output by the loop filter according to the first sampling signal, and drives the SAR ADC to perform N-bit conversion on the signal to be quantized according to the first quantization signal to obtain the N-bit first quantization result.

[0038] S200, in the coarse quantization stage, the multiplexing control circuit drives the SAR ADC to sample the input signal according to the second sampling signal, and drives the SAR ADC to perform M-bit conversion on the input signal according to the second quantization signal to obtain the M-bit second quantization result;

[0039] S300, the digital logic circuit outputs an M-bit digital output result based on the first quantization result and the second quantization result; where M and N are both positive integers, and M is greater than N.

[0040] When step S300 is executed, the digital logic circuit first converts the second quantization result into a first decimal number; then, based on the adjustment number corresponding to the first quantization result, it determines the sum of the first decimal number and the adjustment number to obtain the second decimal number; finally, it converts the second decimal number into a binary digital output result D. OUT This is the result of analog-to-digital conversion. Furthermore, the digital logic circuit determines the thermometer code based on the digital output result and adjusts the capacitor array of the feedback DAC according to the thermometer code to adjust the feedback voltage.

[0041] The specific implementation processes corresponding to steps S100 and S200, as well as the specific adjustment principle of the feedback voltage by the digital logic circuit, have been described in detail in the first embodiment of this disclosure, and will not be repeated here.

[0042] This embodiment achieves structural reuse of the SAR ADC by reusing the control circuit, fundamentally solving the problem of complex quantizer circuit design in traditional hybrid analog-to-digital converters. No additional circuit design is required, and the quantizer part of the overall circuit only needs the area of ​​the SAR ADC, effectively solving the problem of circuit area occupation. In addition, by reusing the SAR ADC, combined with the dynamic operation and low power consumption characteristics of the SAR ADC, the overall power consumption is effectively reduced.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A hybrid architecture analog-to-digital converter, characterized in that, include: The system includes an M-bit SAR ADC, a loop filter, a multiplexing control circuit, and digital logic circuits; among which, The input signal is input to the loop filter so that the loop filter outputs the signal to be quantized; The multiplexing control circuit drives the SAR ADC to perform an N-bit conversion on the signal to be quantized based on the first sampling signal and the first quantization signal, so as to obtain an N-bit first quantization result; The multiplexing control circuit drives the SAR ADC to perform an M-bit conversion on the input signal based on the second sampling signal and the second quantization signal, so as to obtain an M-bit second quantization result; The digital logic circuit outputs an M-bit digital output result based on the first quantization result and the second quantization result; Where M and N are both positive integers, and M is greater than N.

2. The hybrid architecture analog-to-digital converter according to claim 1, characterized in that, The SAR ADC includes at least: a signal input unit, a sampling capacitor array, and a comparator unit; wherein, The signal input unit includes at least a signal input terminal to be quantized and an input signal input terminal. The signal input terminal to be quantized is connected to the sampling capacitor array via a first switch, which is controlled based on the first sampling signal. The input signal input terminal is connected to the sampling capacitor array via a second switch, which is controlled based on the second sampling signal. The sampling capacitor array is used to sample the signal to be quantized or the input signal; The comparator unit converts the signal to be quantized based on the first quantization signal to output the first quantization result, and converts the input signal based on the second quantization signal to output the second quantization result.

3. The hybrid architecture analog-to-digital converter according to claim 2, characterized in that, The multiplexing control circuit includes at least: an asynchronous sequential logic circuit and an asynchronous control clock circuit; wherein... The asynchronous sequential logic circuit is used to determine the current number of bits completed in the quantization stage; the asynchronous control clock circuit is used to output an asynchronous control clock according to the current number of bits completed in the quantization stage to control the working state of the comparator unit.

4. The hybrid architecture analog-to-digital converter according to claim 3, characterized in that, The asynchronous sequential logic circuit includes at least: a NAND gate, a first delay unit, M D flip-flops, and an OR gate; wherein... The two input terminals of the NAND gate are respectively connected to the differential output terminal of the comparator unit. The output terminal of the NAND gate is connected to the input terminal of the first delay unit. The output terminal of the first delay unit is connected to the clock signal terminal of all D flip-flops. All D flip-flops are connected in series. The D terminal of the i-th D flip-flop is connected to the Q terminal of the (i-1)-th D flip-flop. The D terminal of the 1-th D flip-flop is connected to the operating voltage. i = 1, 2, ..., M. The first input terminal of the OR gate is connected to the first sampling signal, the second input terminal of the OR gate is connected to the second sampling signal, and the output terminal of the OR gate is connected to the reset signal terminal of all D flip-flops.

5. The hybrid architecture analog-to-digital converter according to claim 4, characterized in that, The asynchronous control clock circuit includes at least: a three-input NOR gate, a second delay unit, a third switch, and a fourth switch; wherein... The first input of the three-input NOR gate is connected to the output of the OR gate. The Q terminal of the Nth D flip-flop is connected to the second input of the three-input NOR gate through the third switch, which is controlled based on the first quantization signal. The Q terminal of the Mth D flip-flop is connected to the second input of the three-input NOR gate through the fourth switch, which is controlled based on the second quantization signal. The third input of the three-input NOR gate is connected to the output of the NAND gate. The output of the three-input NOR gate is connected to the input of the second delay unit. The output of the second delay unit outputs the asynchronous control clock to control the operating state of the comparator unit.

6. The hybrid architecture analog-to-digital converter according to any one of claims 1 to 5, characterized in that, Also includes: An N-bit feedback DAC, wherein the input terminal of the feedback DAC is connected to the input signal, and the output terminal of the feedback DAC is connected to the input terminal of the loop filter, so as to determine the input signal of the loop filter based on the feedback voltage and the input signal.

7. The hybrid architecture analog-to-digital converter according to claim 6, characterized in that, The digital logic circuit is also used to adjust the capacitor array of the feedback DAC according to the digital output result, so as to adjust the feedback voltage.

8. A control method for a hybrid architecture analog-to-digital converter as described in any one of claims 1 to 7, characterized in that, At least including: In the fine quantization stage, the multiplexing control circuit drives the SAR ADC to sample the signal to be quantized output by the loop filter according to the first sampling signal, and drives the SAR ADC to perform N-bit conversion on the signal to be quantized according to the first quantization signal to obtain the N-bit first quantization result. In the coarse quantization stage, the multiplexing control circuit drives the SAR ADC to sample the input signal according to the second sampling signal, and drives the SAR ADC to perform M-bit conversion on the input signal according to the second quantization signal to obtain the M-bit second quantization result; The digital logic circuit outputs an M-bit digital output result based on the first quantization result and the second quantization result; where M and N are both positive integers, and M is greater than N.

9. The control method according to claim 8, characterized in that, The digital logic circuit outputs an M-bit digital output result based on the first quantization result and the second quantization result, including: Convert the second quantization result into a decimal number; Based on the adjustment number corresponding to the first quantization result, the sum of the first decimal number and the adjustment number is determined to obtain the second decimal number; Convert the second decimal number into a binary number and output the result.

10. The control method according to claim 8 or 9, characterized in that, Also includes: The digital logic circuit determines the thermometer code based on the digital output result, and adjusts the capacitor array of the feedback DAC according to the thermometer code to adjust the feedback voltage.

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