Instruction execution device and method, chip, board card and equipment

Abstract

The invention discloses an instruction execution device and method, a chip, a board card and equipment, and belongs to the field of chips. The device comprises a first scheduling assembly, a second scheduling assembly and an execution assembly, the output end of the first scheduling assembly is connected with the input end of the execution assembly, and the output end of the second scheduling assembly is connected with the input end of the execution assembly; the first scheduling component is responsible for scheduling an instruction sequence for a first thread, the second scheduling component is responsible for scheduling a branch instruction sequence for a second thread, the execution component comprises at least two execution channels, and the at least two execution channels are in one-to-one correspondence with the threads; the first scheduling component is used for scheduling a first branch instruction in the instruction sequence to the execution component; the second scheduling component is used for scheduling a second branch instruction in the instruction sequence to the execution component; and the execution component is used for executing the first branch instruction and the second branch instruction in parallel through at least two execution channels. By adopting the scheme provided by the embodiment of the invention, the utilization rate of the processor can be improved.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to an instruction execution device, method, chip, board, and apparatus. Background Technology

[0002] Different processors handle branch instructions differently. Single-threaded processors typically use branch prediction, which predicts the jump address and direction of the current branch instruction based on historical branch information. With high branch prediction accuracy, this can achieve high instruction execution performance. However, in multi-threaded processors, multiple threads execute instructions simultaneously, and each thread may have a different branch path, meaning each thread's branch jump direction may differ, making branch prediction mechanisms less effective.

[0003] In related technologies, multithreaded processors typically employ a lockstep execution method. This means that all threads execute identical instructions, and branch instructions are executed serially by at least two threads. While one thread is executing a branch instruction, the execution channel for the corresponding thread remains idle. However, too many branch instructions can leave multiple execution channels in the processor idle, resulting in low processor utilization. Summary of the Invention

[0004] This application provides an instruction execution device, method, chip, board, and equipment, the technical solutions of which are as follows.

[0005] On one hand, embodiments of this application provide an instruction execution device, the device including a first scheduling component, a second scheduling component, and an execution component, wherein the output terminal of the first scheduling component is connected to the input terminal of the execution component, and the output terminal of the second scheduling component is connected to the input terminal of the execution component;

[0006] The first scheduling component is responsible for scheduling instruction sequences for the first thread, and the second scheduling component is responsible for scheduling branch instruction sequences for the second thread. The branch instruction sequence includes a portion of the branch instructions in the instruction sequence. The execution component includes at least two execution channels, and the at least two execution channels correspond one-to-one with the threads.

[0007] The first scheduling component is configured to schedule the first branch instruction in the instruction sequence to the execution component, wherein the first branch instruction corresponds to the first instruction branch in the instruction sequence;

[0008] The second scheduling component is used to schedule the second branch instruction in the instruction sequence to the execution component, wherein the second branch instruction corresponds to the second instruction branch in the instruction sequence;

[0009] The execution component is used to execute the first branch instruction and the second branch instruction in parallel through the at least two execution channels.

[0010] On the other hand, embodiments of this application provide an instruction execution method for an instruction execution device. The device includes a first scheduling component, a second scheduling component, and an execution component. The output terminal of the first scheduling component is connected to the input terminal of the execution component, and the output terminal of the second scheduling component is connected to the input terminal of the execution component.

[0011] The first scheduling component is responsible for scheduling instruction sequences for the first thread, and the second scheduling component is responsible for scheduling branch instruction sequences for the second thread. The branch instruction sequence includes a portion of the branch instructions in the instruction sequence. The execution component includes at least two execution channels, and the at least two execution channels correspond one-to-one with the threads.

[0012] The method includes:

[0013] The first scheduling component schedules the first branch instruction in the instruction sequence to the execution component, whereby the first branch instruction corresponds to the first instruction branch in the instruction sequence.

[0014] The second scheduling component schedules the second branch instruction in the instruction sequence to the execution component, whereby the second branch instruction corresponds to the second instruction branch in the instruction sequence.

[0015] The first branch instruction and the second branch instruction are executed in parallel through at least two execution channels in the execution component.

[0016] On the other hand, embodiments of this application provide a chip that includes at least one load memory unit as described above.

[0017] On the other hand, embodiments of this application provide a board card that is provided with the chip described above.

[0018] On the other hand, embodiments of this application provide a computer device, which is provided with the boards as described above.

[0019] The beneficial effects of the technical solutions provided in this application include at least the following:

[0020] By setting corresponding scheduling components for different threads, with the first scheduling component responsible for scheduling instruction sequences for the first thread and the second scheduling component responsible for scheduling branch instruction sequences for the second thread, and by mapping the execution channels in the execution component to threads one-to-one, it is possible to schedule the first branch instruction in the instruction sequence to the execution component through the first scheduling component and the second branch instruction in the instruction sequence to the execution component when there are branches in the instruction sequence. This allows at least two execution channels of the execution component to execute the first and second branch instructions in parallel, avoiding the problem of idle execution channels caused by serial execution of branch instructions. This can improve the utilization rate of the execution components in the processor and thus improve instruction execution efficiency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram illustrating the sequential execution of branch instructions using at least two threads in related technologies is shown.

[0023] Figure 2 This invention provides a schematic diagram of the structure of an instruction execution apparatus according to an exemplary embodiment of the present application.

[0024] Figure 3 A schematic diagram of the structure of an instruction execution apparatus provided in another exemplary embodiment of this application is shown;

[0025] Figure 4 This invention provides a schematic diagram of the structure of a branch processing component according to an exemplary embodiment of the present application.

[0026] Figure 5 This invention provides a schematic diagram of the structure of an execution component according to an exemplary embodiment of the present application.

[0027] Figure 6 This illustration shows a schematic diagram of a first thread and a second thread executing branch instructions in parallel, according to an exemplary embodiment of this application.

[0028] Figure 7 This illustration shows a schematic diagram of an access register file provided in an exemplary embodiment of this application;

[0029] Figure 8 This invention illustrates a schematic diagram of the structure of a scheduling component provided in an exemplary embodiment of this application;

[0030] Figure 9A flowchart illustrating an exemplary embodiment of the instruction execution method provided in this application is shown;

[0031] Figure 10 A flowchart of an instruction execution method provided by another exemplary embodiment of this application is shown;

[0032] Figure 11 A schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0035] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0036] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0037] First, a brief introduction to the terms used in the embodiments of this application:

[0038] Branch instructions: A class of instructions used to control the execution flow of a program. They allow the program to determine the execution path based on specific conditions or values, such as skipping execution of certain code segments or repeating execution of certain code segments. Optionally, branch instructions are conditional; whether a branch instruction is executed depends on whether the condition is met.

[0039] A multithreaded processor is a processor capable of handling multiple threads simultaneously on a single physical processor core. Using a multithreaded processor can improve processor resource utilization, enhance parallel processing capabilities, and improve overall performance.

[0040] In using pipelining to improve instruction execution efficiency, pipelining typically breaks down the instruction execution process into multiple stages to achieve parallel processing. When conditional branch instructions are encountered, the processor needs to wait for the condition check and the branch instruction to complete before determining the next instruction, which may lead to pipelining interruptions.

[0041] In single-threaded processors, branch prediction is typically used to predict the jump address and jump direction of the current branch instruction based on historical branch information. With high branch prediction accuracy, high instruction execution performance can be achieved.

[0042] In multithreaded processors, multiple threads execute instructions simultaneously. When branch instructions appear, each thread may have a different branch path, meaning each thread may jump to a different branch direction. This makes it difficult for branch prediction mechanisms to function effectively in multithreaded processors.

[0043] In related technologies, lockstep execution is typically used in multi-threaded processors to control the instruction sequence of threads. This means all threads execute the same instruction sequence, and branch instructions are executed serially in groups of at least two threads. For example, thread 0 executes the first branch instruction in the instruction sequence during the first clock cycle, and thread 1 executes the second branch instruction during the second clock cycle. This means that the execution channel corresponding to thread 1 is idle during the first clock cycle, and the execution channel corresponding to thread 0 is idle during the second clock cycle. Therefore, with a large number of branch instructions, multiple execution channels will be idle, resulting in low utilization of the processor's execution components.

[0044] Indicative, such as Figure 1 As shown, it illustrates a schematic diagram of the sequential execution of branch instructions by at least two threads in related technologies. Figure 1The example uses threads 0 and 1 as one group, and threads 2 and 3 as another group. In the case of instructions with branches, for if-else instructions, threads 0 and 2 execute the if branch instruction in the first clock cycle, while threads 1 and 3 are in an idle state, meaning the hardware execution components corresponding to threads 1 and 3 are in an idle state. In the second clock cycle, threads 1 and 3 execute the else branch instruction, while threads 0 and 2 are in an idle state, meaning the hardware execution components corresponding to threads 0 and 2 are in an idle state.

[0045] In this embodiment, in order to fully utilize processor resources and improve the execution efficiency of branch instructions in a multi-threaded processor, a corresponding scheduling component is set for different threads in the front-end instruction scheduling part of the processor. The first scheduling component is responsible for scheduling the instruction sequence for the first thread, and the second scheduling component is responsible for scheduling the branch instruction sequence for the second thread. The execution channels in the execution component are mapped one-to-one with the threads. This allows the first branch instruction in the instruction sequence to be scheduled to the execution component by the first scheduling component and the second branch instruction in the instruction sequence to be scheduled to the execution component by the second scheduling component when there is a branch instruction. The first branch instruction and the second branch instruction are executed in parallel by at least two execution channels of the execution component, avoiding the problem of idle execution channels caused by the serial execution of two branch instructions.

[0046] The instruction execution device proposed in this application will now be described in detail through specific embodiments.

[0047] Please refer to Figure 2 The diagram illustrates the structure of an instruction execution device provided in an exemplary embodiment of this application. The instruction execution device includes a first scheduling component 201, a second scheduling component 202, and an execution component 203.

[0048] The output of the first scheduling component 201 is connected to the input of the execution component 203, and the output of the second scheduling component 202 is connected to the input of the execution component 203.

[0049] Optionally, the first scheduling component 201 is responsible for scheduling the instruction sequence for the first thread, the second scheduling component 202 is responsible for scheduling the branch instruction sequence for the second thread, and the execution component 203 includes at least two execution channels, each corresponding to a thread.

[0050] Optionally, the first thread can be called the main thread, responsible for executing the main instruction flow. The second thread can be called a sub-thread, responsible for executing specific instruction flows. Optionally, if there are instruction branches in the instruction sequence executed by the first thread, the first thread can be responsible for executing the first branch instruction in the instruction sequence, while the second branch instruction in the instruction sequence is assigned to the second thread for execution. That is, the branch instruction sequence executed by the second thread includes a portion of the branch instructions in the instruction sequence executed by the first thread.

[0051] For example, if there is an if-else instruction branch in the instruction sequence, the first thread is responsible for executing the if branch instruction, and the second thread is responsible for executing the else branch instruction.

[0052] Optionally, to ensure that if an instruction sequence executed by the first thread contains instruction branches, the second branch instruction in the instruction sequence can be allocated to the second thread, the number of first threads and the number of second threads are the same. Optionally, the multithreaded processor may include n first threads and n second threads, in which case the first scheduling component is responsible for scheduling instruction sequences for the n first threads, and the second scheduling component is responsible for scheduling branch instruction sequences for the n second threads.

[0053] Optionally, to improve the parallelism of instruction execution, the execution channels in the execution component need to correspond one-to-one with threads, meaning each thread has its own execution channel within the execution component. Optionally, the execution component includes 2n execution channels.

[0054] The first scheduling component 201 is used to schedule the first branch instruction in the instruction sequence to the execution component, wherein the first branch instruction corresponds to the first instruction branch in the instruction sequence.

[0055] The second scheduling component 202 is used to schedule the second branch instruction in the instruction sequence to the execution component, where the second branch instruction corresponds to the second instruction branch in the instruction sequence.

[0056] Optionally, in the process of improving instruction execution efficiency using pipeline technology, when there are instruction branches in the instruction sequence, since the branch jump conditions corresponding to the instruction branches may not have been judged yet, in order to avoid pipeline stalls, in a multi-threaded processor, the first branch instruction and the second branch instruction of the instruction sequence can be executed by two threads respectively.

[0057] Optionally, to improve the efficiency of the instruction pipeline, the position of instructions in the instruction sequence can be changed by the scheduling component to reorder the instructions. Optionally, when there are instruction branches in the instruction sequence, the first scheduling component can be used to schedule the first branch instruction in the instruction sequence to the execution component, and the second scheduling component can be used to schedule the second branch instruction in the instruction sequence to the execution component.

[0058] In this instruction sequence, the first branch instruction corresponds to the first instruction branch, and the second branch instruction corresponds to the second instruction branch. For example, in an if-else instruction, the first branch instruction can be an if branch instruction, and the second branch instruction can be an else branch instruction.

[0059] Optionally, instruction scheduling may include three stages: instruction fetch, instruction decoding, and instruction issuance. Instruction fetch can be performed by retrieving the instruction sequence from memory through the instruction fetch unit, or by retrieving the instruction sequence from the cache through the instruction fetch unit. Instruction decoding involves decoding the instructions into a format that the processor can understand and execute. Instruction issuance involves sequentially issuing the instruction sequence to the corresponding execution units, which then execute the instruction sequence.

[0060] Optionally, if there are no instruction branches in the instruction sequence, the first scheduling component is used to schedule the instruction sequence to the execution component in sequence, while the second scheduling component is idle; if there are instruction branches in the instruction sequence, the first scheduling component is used to schedule a portion of the branch instructions in the instruction sequence to the execution component, while the second scheduling component is used to schedule another portion of the branch instructions in the instruction sequence to the execution component.

[0061] Execution component 203 is used to execute the first branch instruction and the second branch instruction in parallel through at least two execution channels.

[0062] Optionally, the execution component includes at least two execution channels, with each channel corresponding one-to-one with a thread. That is, the first thread and the second thread each have their own execution channel. Thus, after the execution component receives the first branch instruction and the second branch instruction scheduled by the first scheduling component and the second scheduling component, the execution component can execute the first branch instruction and the second branch instruction in parallel through the respective execution channels of each thread. In other words, while the execution channel corresponding to the first thread is executing the first branch instruction, the execution channel corresponding to the second thread is simultaneously executing the second branch instruction, without any issue of execution channels being idle due to instruction branches.

[0063] Optionally, after both the first branch instruction and the second branch instruction have been executed, the execution component may temporarily store the execution result of the first instruction corresponding to the first branch instruction and the execution result of the second instruction corresponding to the second branch instruction. After the instruction pipeline completes the branch jump condition judgment, the execution data of one of the branch instructions that does not meet the branch jump condition will be deleted to optimize storage space.

[0064] In summary, in this embodiment, by setting corresponding scheduling components for different threads, with the first scheduling component responsible for scheduling instruction sequences for the first thread and the second scheduling component responsible for scheduling branch instruction sequences for the second thread, and by mapping the execution channels in the execution component to threads one-to-one, it is possible to schedule the first branch instruction in the instruction sequence to the execution component through the first scheduling component and the second branch instruction in the instruction sequence to the execution component when there are branches in the instruction sequence. This allows at least two execution channels of the execution component to execute the first branch instruction and the second branch instruction in parallel, avoiding the problem of idle execution channels caused by serial execution of branch instructions. This improves the utilization rate of the execution components in the processor and thus improves instruction execution efficiency.

[0065] In some embodiments, in order to implement instruction scheduling by assigning branch instructions in the instruction sequence to the corresponding scheduling components in the presence of instruction branches, the instruction execution device may further include a branch processing component.

[0066] Please refer to Figure 3 The diagram illustrates the structure of an instruction execution device provided in another exemplary embodiment of this application. The instruction execution device includes a first scheduling component 301, a second scheduling component 302, an execution component 303, and a branch processing component 304.

[0067] Indicative, such as Figure 3 As shown, the input of the branch processing component 304 is connected to the output of the execution component 303, the output of the branch processing component 304 is connected to the input of the first scheduling component 301, and the output of the branch processing component 304 is connected to the input of the second scheduling component 302.

[0068] Branch processing component 304 is used to assign the first branch instruction in the instruction sequence to the first scheduling component and the second branch instruction in the instruction sequence to the second scheduling component when there is an instruction branch in the instruction sequence.

[0069] Optionally, when instruction branches exist in the instruction sequence, the branch processing component can calculate the instruction address corresponding to the branch instruction and determine whether to execute the branch jump based on the branch jump condition. However, in the instruction pipeline, if the branch jump condition is not yet ready—that is, if the relevant instructions used to determine the branch jump condition have not yet been executed—the branch processing component can distribute the branch instruction to different threads, allowing each thread to execute different branch instructions to ensure execution for each branch jump scenario.

[0070] Optionally, the branch processing component can determine whether an instruction is a branch instruction based on its opcode. For example, for a conditional branch instruction, which contains a condition code field, the branch processing component determines that the instruction has an instruction branch if it detects the presence of a condition code in the instruction. Thus, the branch processing component can assign the first branch instruction to the first scheduling component and the second branch instruction to the second scheduling component.

[0071] The branch processing component 304 is also used to transmit the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction to the first scheduling component and the second scheduling component.

[0072] Optionally, when the branch processing component detects the existence of an instruction branch, it can also calculate the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction.

[0073] Optionally, for conditional branch instructions, the instruction typically includes an offset, which indicates the address of one of the branch instructions relative to the current instruction. Optionally, for the first branch instruction, its corresponding first instruction address can be the current instruction address plus the number of bytes in a single instruction; for the second branch instruction, its corresponding second instruction address is the current instruction address plus the number of bytes in a single instruction plus the offset.

[0074] Furthermore, after obtaining the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction, the branch processing component can transmit the instruction address to the scheduling component, which then schedules the instructions based on the instruction address.

[0075] Optionally, to improve the efficiency and accuracy of branch instruction execution, branch jumps can be implemented quickly after the branch jump condition is determined. When assigning the first branch instruction to the first scheduling component, the branch processing component can simultaneously transmit the second instruction address to the first scheduling component, in addition to transmitting the first instruction address, so that the first scheduling component can temporarily store the second instruction address. Similarly, when assigning the second branch instruction to the second scheduling component, the branch processing component can simultaneously transmit the first instruction address to the second scheduling component, in addition to transmitting the second instruction address, so that the second scheduling component can temporarily store the first instruction address.

[0076] The first scheduling component 301 is used to schedule the first branch instruction to the execution component based on the first instruction address.

[0077] Optionally, after receiving the first instruction address and the second instruction address, the first scheduling component can store the second instruction address, retrieve the first branch instruction from memory or cache according to the first instruction address, decode the first branch instruction, and then transmit the decoded first branch instruction to the execution component.

[0078] Optionally, in the instruction pipeline, the first scheduling component continuously fetches instructions from memory and writes the fetched instructions into a cache. In one possible implementation, if a first instruction address is received and the cache already contains the first branch instruction corresponding to the first instruction address, the first scheduling component directly schedules the first branch instruction in the cache to the execution component. In another possible implementation, if a first instruction address is received and the cache does not contain the first branch instruction corresponding to the first instruction address, the first scheduling component needs to fetch the first branch instruction from memory and schedule the first branch instruction to the execution component.

[0079] The second scheduling component 302 is used to schedule the second branch instruction to the execution component based on the second instruction address.

[0080] Optionally, after receiving the first instruction address and the second instruction address, the second scheduling component can store the first instruction address, retrieve the second branch instruction from memory or cache according to the second instruction address, decode the second branch instruction, and then transmit the decoded second branch instruction to the execution component.

[0081] Optionally, if the first scheduling component continuously fetches instructions from memory and writes the fetched instructions into the cache, the second scheduling component, upon receiving the address of the second instruction, can first attempt to fetch the second branch instruction from the cache. If the second branch instruction is already stored in the cache, the second scheduling component can directly schedule the second branch instruction in the cache to the execution component; if the second branch instruction is not stored in the cache, the second scheduling component needs to fetch the second branch instruction from memory and schedule the second branch instruction to the execution component.

[0082] In the above embodiments, branch instructions are allocated to the first scheduling component and the second scheduling component by the branch processing component, so that the first scheduling component and the second scheduling component can schedule their respective branch instructions in parallel and transmit them to the execution component in parallel. The execution component processes the first branch instructions and the second branch instructions in parallel, which improves the efficiency and accuracy of branch instruction execution.

[0083] In some embodiments, considering that the branch instruction sequence executed by the second thread may include multiple sub-instructions, and that there may be instruction branches in the instruction pipeline, that is, when there is an instruction branch in the current instruction, the second thread may still be executing the sub-branch instructions in the previous instruction branch and cannot execute the branch instructions in the current instruction, in order to improve the efficiency of allocating instructions to various scheduling components, before allocating branch instructions, the branch processing component also needs to determine the thread state of the second thread and determine whether to allocate branch instructions to the second scheduling component based on the thread state.

[0084] Please refer to Figure 4 This illustration shows a schematic diagram of the structure of a branch processing component provided in an exemplary embodiment of this application. It is illustrative, as shown below. Figure 4 As shown, the branch processing component 410 includes a first branch processing unit 411, a multiplexer 413, and a status register 414.

[0085] The input terminal of the first branch processing unit 411 is connected to the output terminal of the execution component 440, the output terminal of the first branch processing unit 411 is connected to the input terminal of the multiplexer 413, the output terminal of the first branch processing unit 411 is connected to the first scheduling component 420, the output terminal of the status register 414 is connected to the selection terminal of the multiplexer 413, and the output terminal of the multiplexer 413 is connected to the second scheduling component 430.

[0086] Status register 414 is used to store the status information of the second thread and input the status information into the multiplexer.

[0087] Optionally, if there is an instruction branch, the branch processing component will allocate a second branch instruction to the second scheduling component. The second branch instruction may include a single sub-instruction, multiple sub-instructions, or multiple sub-branch instructions. This application embodiment does not limit this.

[0088] Optionally, when the branch processing component assigns a second branch instruction to the second scheduling component, it signifies that the second thread starts, begins processing the second branch instruction, and enters a busy state. After the execution component executes the second branch instruction through the execution channel corresponding to the second thread and obtains the execution result of the second instruction, it signifies that the second thread enters an idle state, and the branch processing component can continue to assign branch instructions to the second scheduling component.

[0089] Optionally, the status register is used to store the status information of the second thread and input the status information into the multiplexer. The multiplexer can then determine whether to transmit the instruction address to the second scheduling component based on the status information. Optionally, the status register can be represented as idle_S.

[0090] Optionally, when the second thread is in an idle state, its corresponding status information can be set to 0; when the second thread is in a busy state, its corresponding status information can be set to 1.

[0091] The first branch processing unit 411 is used to input the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction to the first scheduling component when there is an instruction branch in the instruction sequence executed by the first thread.

[0092] Optionally, the first branch processing unit (Bru) can be represented as bru_M.

[0093] Optionally, the first branch processing unit is responsible for processing instruction branches in the instruction sequence executed by the first thread. If an instruction branch is detected in the instruction sequence executed by the first thread, the first branch processing unit needs to further determine the first branch instruction and the second branch instruction in the instruction sequence, and allocate the first branch instruction to the first scheduling component and the second branch instruction to the second scheduling component.

[0094] Optionally, if an instruction branch is detected in the instruction sequence executed by the first thread, the first branch processing unit calculates the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction, and transmits the first instruction address and the second instruction address to the first scheduling component.

[0095] Optionally, during the execution of the first branch instruction by the first thread, the first branch processing unit is also responsible for detecting whether there is an instruction branch in the first branch instruction. If there is an instruction branch in the first branch instruction, the unit calculates the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the first branch instruction, and inputs the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the first branch instruction to the first scheduling component.

[0096] The first branch processing unit 411 is also used to input the first instruction address and the second instruction address to the multiplexer.

[0097] Optionally, in addition to inputting the first instruction address and the second instruction address to the first scheduling component, the first branch processing unit also needs to input the first instruction address and the second instruction address to the multiplexer, so that the multiplexer can determine whether to transmit the first instruction address and the second instruction address to the second scheduling component based on the status information of the second thread.

[0098] Multiplexer 413 is used to transmit the first instruction address and the second instruction address to the second scheduling component when the status information indicates that the second thread is in an idle state.

[0099] Optionally, after receiving the first instruction address and the second instruction address input by the first branch processing unit, the multiplexer (MUX) can transmit the first instruction address and the second instruction address to the second scheduling component if the status information indicates that the second thread is in an idle state; otherwise, if the status information indicates that the second thread is in a busy state, the first instruction address and the second instruction address will not be transmitted to the second scheduling component.

[0100] Optionally, considering that the second branch instruction may contain sub-branch instructions when the second thread is busy, i.e., during the execution of the second branch instruction by the second thread, the branch processing component may also include a second branch processing unit in order to improve the instruction execution efficiency of the second thread.

[0101] Indicative, such as Figure 4 As shown, the branch processing component 410 further includes a second branch processing unit 412. The input of the second branch processing unit 412 is connected to the output of the execution component 440, and the output of the second branch processing unit 412 is connected to the input of the multiplexer 413.

[0102] The second branch processing unit 412 is used to input the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction into the multiplexer when there is an instruction branch in the second branch instruction.

[0103] Optionally, the second branch processing unit can be represented as bru_S.

[0104] Optionally, during the execution of the second branch instruction by the second thread, the second branch processing unit is responsible for detecting whether there is an instruction branch in the second branch instruction. If there is an instruction branch in the second branch instruction, it calculates the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the second branch instruction, and inputs the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the second branch instruction into the multiplexer.

[0105] Multiplexer 413 is used to transmit the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction to the second scheduling component when the status information indicates that the second thread is busy.

[0106] Optionally, if the received status information indicates that the second thread is in a busy state, and the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction are received from the second branch processing unit, the multiplexer can directly transmit the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction to the second scheduling component, and the second scheduling component can continue to schedule the sub-branch instructions in the second branch instruction.

[0107] The second scheduling component 430 is used to serially schedule the first sub-branch instruction and the second sub-branch instruction.

[0108] Optionally, for sub-branch instructions that exist in the second branch instruction, other threads will no longer be used to execute them in parallel. Instead, the second thread will execute the first sub-branch instruction and the second sub-branch instruction serially. That is, the second scheduling component will schedule the first sub-branch instruction and the second sub-branch instruction serially.

[0109] Optionally, the second thread can use branch prediction to first execute the first sub-branch instruction. If the branch jump condition corresponding to the first sub-branch instruction is met, the second sub-branch instruction will not be executed. If the branch jump condition corresponding to the second sub-branch instruction is met, the execution of the first sub-branch instruction will stop and the execution of the second sub-branch instruction will return.

[0110] In the above embodiments, in the branch processing component, the instruction sequence executed by the first thread is processed by the first branch processing unit. If there are instruction branches in the instruction sequence executed by the first thread, the first branch processing unit outputs the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction. The scheduling component then schedules the instructions based on these instruction addresses, improving the accuracy of instruction scheduling. Furthermore, the second branch processing unit processes the sub-branch instructions present in the second branch instruction, ensuring the effective scheduling and execution of nested branch instructions and optimizing the efficiency of parallel execution of branch instructions.

[0111] In some embodiments, in order to enable the execution of the first branch instruction and the second branch instruction in parallel in the execution component, the execution component needs to set up a corresponding execution channel for each thread, and the corresponding branch instruction is executed by the execution channel of each thread. The instruction execution process will be described below through specific embodiments.

[0112] Please refer to Figure 5 The diagram illustrates the structure of an execution component provided in an exemplary embodiment of this application.

[0113] Indicative, such as Figure 5As shown, the execution component 510 includes a register file 511 and a multiple instruction multiple data unit (MIBMU) 512. The input of register file 511 is connected to the output of the first scheduling component 520, the input of register file 511 is connected to the output of the second scheduling component 530, the input of register file 511 is connected to the output of the MIBMU 512, the output of register file 511 is connected to the input of the MIBMU 512, and the output of register file 511 is connected to the input of the branch processing component 540.

[0114] Register file 511 is used to provide first register data for the first branch instruction and second register data for the second branch instruction.

[0115] Optionally, a register file, also known as a register set, consists of a series of registers, each with a unique identifier, such as registers r1, r2, r3, etc. The registers store data and address information used during program execution. Optionally, the register file includes multiple read and write ports, allowing data to be read from and written to multiple registers simultaneously.

[0116] Optionally, the register file can be used to provide first register data for the first branch instruction and second register data for the second branch instruction.

[0117] Optionally, to improve the access efficiency of the register file, the register file is usually divided into at least two banks, and each bank has an independent access port, thereby allowing parallel access to multiple banks.

[0118] Optionally, register addresses are typically mapped to different memory banks according to certain rules. For example, they can be mapped using consecutive address mapping, where consecutive register addresses are mapped to different memory banks. Taking a register file divided into 32 registers, with each bank containing 8 registers, as an example, registers at addresses 0 to 7 would be mapped to Bank 0, registers at addresses 8 to 15 would be mapped to Bank 1, and so on. Alternatively, they can be mapped using circular address mapping, where register addresses are cyclically mapped to different banks. Optionally, the address mapping in the register file can be dynamic; for example, banks can be allocated according to the current data access mode and requirements to reduce bank conflicts.

[0119] In this embodiment, to ensure that the first thread and the second thread can simultaneously access the same memory bank in the register file during the parallel execution of the first branch instruction and the second branch instruction, each memory bank in the register file is further divided into at least two sub-memory banks, with each sub-memory bank corresponding to a thread. Optionally, to satisfy the parallel execution of instructions by n first threads and n second threads, each memory bank is divided into 2n sub-memory banks, so that each thread can access its corresponding sub-memory bank, avoiding access conflicts and improving the access efficiency of the register file.

[0120] Indicative, such as Figure 5 As shown, taking a processor with two first threads (thread0 and thread2) and two second threads (thread1 and thread3) as an example, each bank in the register file is divided into four sub-banks (S0-S3), and in each bank, S0 corresponds to the first thread thread0, S1 corresponds to the second thread thread1, S2 corresponds to the first thread thread2, and S3 corresponds to the second thread thread3.

[0121] The Multiple Instruction Multiple Data Unit 512 is used to execute the first branch instruction based on the data in the first register through the execution channel corresponding to the first thread.

[0122] Optionally, the Multi-Instruction Multi-Data (MIMD) method, after obtaining the first register data corresponding to the first branch instruction, can execute the first branch instruction through the execution channel corresponding to the first thread based on the first register data.

[0123] Optionally, a multiple instruction multiple data unit (MIB) is used to read first register data from the sub-memory bank corresponding to the first thread in the register file, and to perform instruction operations, such as arithmetic operations and logical operations, based on the obtained first register data. Then, after obtaining the execution result of the first instruction corresponding to the first branch instruction, the execution result of the first instruction is written into the sub-memory bank corresponding to the first thread in the register file.

[0124] The Multiple Instruction Multiple Data Unit 512 is used to execute the second branch instruction based on the data in the second register through the execution channel corresponding to the second thread.

[0125] Optionally, after obtaining the second register data corresponding to the second branch instruction, the Multiple Instruction Multiple Data Unit can execute the second branch instruction through the execution channel corresponding to the second thread based on the second register data.

[0126] Optionally, a multiple instruction multiple data unit (MIB) is used to read second register data from the sub-memory of the second thread in the register file, and to perform instruction operations, such as arithmetic operations and logical operations, based on the obtained second register data. After obtaining the execution result of the second instruction corresponding to the second branch instruction, the execution result of the second instruction is written into the sub-memory of the second thread in the register file.

[0127] Indicative, such as Figure 5 As shown, taking a processor with two first threads (thread0 and thread2) and two second threads (thread1 and thread3) as an example, the Multiple Instruction Multiple Data Unit includes four execution channels, where execution channel lane0 corresponds to the first thread thread0, execution channel lane1 corresponds to the second thread thread1, execution channel lane2 corresponds to the first thread thread2, and execution channel lane3 corresponds to the second thread thread3.

[0128] Indicative, such as Figure 6 As shown, for if-else branch instructions, the if branch instruction is r2 = r0 + r1, and the else branch instruction is r6 = r4 - r5. The first thread (thread0) and the second thread (thread1) are grouped together; thread0 executes the if branch instruction, and thread1 executes the else branch instruction. Similarly, the first thread (thread2) and the second thread (thread3) are grouped together; thread2 executes the if branch instruction, and thread3 executes the else branch instruction. After the multi-instruction multiple-data unit (MINU) retrieves the first and second register data from the register file, the branch instructions corresponding to each thread can be executed in parallel through four execution channels, thus fully utilizing the execution components.

[0129] Indicative, such as Figure 7 As shown, Figure 7Taking registers r0 and r4 as mapped to bank0, registers r1 and r5 as mapped to bank1, registers r2 and r6 as mapped to bank2, and registers r3 and r7 as mapped to bank3 as an example, for if-else branch instructions, the if branch instruction is r2 = r0 + r1, and the else branch instruction is r6 = r4 - r5. Taking bank0 as an example, r0_w0 is the 0th word of register r0, corresponding to the first thread thread0; r0_w2 is the 2nd word of register r0, corresponding to the first thread thread2; r4_w1 is the 1st word of register r4, corresponding to the second thread thread1; r4_w3 is the 3rd word of register r4, corresponding to the second thread thread3, and so on for other banks. Since the first threads, thread0 and thread2, execute the if branch instruction, they access r0_w0 and r0_w2 in bank0; since the second threads, thread1 and thread3, execute the else branch instruction, they access r4_w1 and r4_w3 in bank0.

[0130] Furthermore, for if-else branch instructions, the if branch instruction is r2 = r0 + r1, and the else branch instruction is r6 = r4 - r5. Multiple instruction multiple data units (MINUs) can read the instruction data required by the first thread (thread0) (r0_w0 and r1_w0), the first thread (thread2) (r0_w2 and r1_w2), the second thread (thread1) (r4_w1 and r5_w1), and the second thread (thread3) (r4_w3 and r5_w3) from register files bank0 and bank1 respectively. Addition operations are performed through execution channels lane0 and lane2, and subtraction operations are performed through execution channels lane1 and lane3. This results in the instruction execution results for the first thread (thread0) being written to r2_w0, the second thread (thread1) to r6_w1, the first thread (thread2) to r2_w2, and the second thread (thread3) to r6_w3.

[0131] In the above embodiments, in the execution component, by dividing each storage bank in the register file into at least two sub-storage banks, such that each sub-storage bank corresponds one-to-one with a thread, the first thread and the second thread can read the register data required for executing branch instructions from the register file in parallel, improving the instruction access efficiency in the register file. Furthermore, by corresponding each execution channel within the multi-instruction multiple-data unit (MIB) to a thread, the branch instructions corresponding to each thread can be executed in parallel within the MIB, improving the parallel execution degree of branch instructions.

[0132] In some embodiments, to ensure the orderliness of instruction scheduling, instruction scheduling can be divided into three stages: instruction acquisition, instruction decoding, and instruction issuance. These three stages are completed sequentially by different scheduling units. The instruction scheduling process will be described below through specific embodiments.

[0133] Please refer to Figure 8 The diagram illustrates the structure of a scheduling component provided in an exemplary embodiment of this application.

[0134] Indicative, such as Figure 8 As shown, the first scheduling component 810 includes a first instruction fetch unit 811, a buffer unit 830, a first decoder 812, a first buffer 813, and a first transmission unit 814.

[0135] The output of the first instruction fetch unit 811 is connected to the input of the buffer unit 830, the output of the buffer unit 830 is connected to the input of the first decoder 812, the output of the first decoder 812 is connected to the input of the first buffer 813, the output of the first buffer 813 is connected to the input of the first transmit unit 814, and the output of the first transmit unit 814 is connected to the execution component 840.

[0136] The first instruction fetch unit 811 is used to fetch the first branch instruction from memory based on the first instruction address and store the first branch instruction into the cache unit 830.

[0137] Optionally, the first instruction fetch unit (IFU) is used to fetch the first branch instruction from memory based on the first instruction address and store the first branch instruction into the cache unit. Optionally, the first instruction fetch unit can be represented as IFU_M.

[0138] Optionally, in the instruction pipeline, the first instruction fetch unit continuously fetches instructions from memory and writes the fetched instructions into a cache unit. In one possible implementation, when a first instruction address is received and the cache unit already stores the first branch instruction corresponding to the first instruction address, the first instruction fetch unit directly fetches the first branch instruction from the cache unit and sends it to the first decoder. In another possible implementation, when a first instruction address is received and the cache unit does not store the first branch instruction corresponding to the first instruction address, the first instruction fetch unit needs to fetch the first branch instruction from memory, write the first branch instruction into the cache unit, and then fetch the first branch instruction from the cache unit and send it to the first decoder.

[0139] Optionally, to improve the orderliness of the instruction fetching process, the first instruction fetching unit may include a first stack and a first program pointer generator (PC_gen).

[0140] Indicative, such as Figure 8 As shown, the first instruction fetch unit 811 includes a first stack 815 and a first program pointer generator 816. The input of the first stack 815 is connected to the output of the branch processing component 850, the output of the first stack 815 is connected to the input of the first program pointer generator 816, and the output of the first program pointer generator 816 is connected to the input of the cache unit 830.

[0141] Optionally, the first stack 815 is used to store the address of the second instruction corresponding to the second branch instruction.

[0142] Optionally, the first instruction fetch unit maintains the instruction address corresponding to the branch instruction through the first stack. When an instruction branch exists and the first scheduling component schedules the first branch instruction, the first stack stores the address of the second instruction corresponding to the second branch instruction. Optionally, the first stack may also store the thread information corresponding to the second branch instruction, so that after executing the branch instruction, the processor can reassemble the thread based on the instruction address and thread information saved in the stack.

[0143] Optionally, if there is an instruction branch in the first branch instruction, when the first scheduling component schedules the first sub-branch instruction in the first branch instruction, it can push the address of the second instruction corresponding to the second sub-branch instruction in the first branch instruction onto the stack for management, thereby ensuring the efficient execution of nested branch instructions.

[0144] Optionally, the first program pointer generator 816 is used to update the first program pointer based on the first instruction address corresponding to the first branch instruction.

[0145] Optionally, the first program pointer generator maintains a first program pointer, which indicates the address of the instruction corresponding to the currently fetched instruction. Optionally, to ensure the accuracy of instruction fetching, after receiving the address of the first instruction corresponding to the first branch instruction, the first program pointer generator can update the first program pointer based on the first instruction address.

[0146] Optionally, the first branch instruction can correspond to the instruction branch when the branch condition in the instruction is not met, and the second branch instruction corresponds to the instruction branch when the branch condition in the instruction is met. Optionally, the first instruction address corresponding to the first branch instruction can be the address of the next instruction to be executed in the instruction sequence, and the second instruction address corresponding to the second branch instruction is the branch jump address. Alternatively, the first instruction address corresponding to the first branch instruction can be the branch jump address, and the second instruction address corresponding to the second branch instruction is the address of the next instruction to be executed in the instruction sequence.

[0147] Optionally, the first instruction fetch unit 811 is used to fetch the first branch instruction from memory based on the updated first program pointer.

[0148] Optionally, after the first program pointer is updated, the first instruction fetch unit can fetch the first branch instruction from the instruction address indicated by the first program pointer in memory according to the updated first program pointer.

[0149] The first decoder 812 is used to decode the first branch instruction and write the decoded first branch instruction into the first buffer 813.

[0150] Optionally, considering that the processor may not understand the meaning of instructions fetched directly from memory, the first branch instruction needs to be decoded by the first decoder in order to execute subsequent instructions, and the decoded instruction is written into the first buffer, where it waits to be issued to the execution component.

[0151] The first issuing unit 814 is used to issue the first branch instruction in the first buffer 813 to the execution component 840 when the instruction issuing conditions are met.

[0152] Optionally, the first issuing unit is responsible for issuing the decoded first branch instruction from the first buffer to the execution component. Optionally, for the instruction to be issued, the first issuing unit first determines whether the instruction issuance conditions are met. Only if the instruction issuance conditions are met will the first issuing unit issue the instruction to the execution component.

[0153] Optionally, satisfying the instruction issuance conditions may include that the data required to execute the instruction is ready, the execution channel is idle and there is no register access conflict, and may also include other conditions determined based on the specific hardware design. This application embodiment does not limit these conditions.

[0154] Optionally, if it is determined that the first branch instruction meets the instruction issuance conditions, the first issuing unit issues the first branch instruction to the execution component, and the execution channel corresponding to the first thread in the execution component executes the first branch instruction.

[0155] Indicative, such as Figure 8 As shown, the second scheduling component 820 includes a second instruction fetch unit 821, a buffer unit 830, a second decoder 822, a second buffer 823, and a second transmit unit 824.

[0156] The output of the second instruction fetch unit 821 is connected to the input of the buffer unit 830, the output of the buffer unit 830 is connected to the input of the second decoder 822, the output of the second decoder 822 is connected to the input of the second buffer 823, the output of the second buffer 823 is connected to the input of the second transmit unit 824, and the output of the second transmit unit 824 is connected to the execution component 840.

[0157] The second instruction fetch unit 821 is used to fetch the second branch instruction from memory based on the second instruction address and store the second branch instruction into the cache unit.

[0158] Optionally, the second instruction fetch unit is used to fetch the second branch instruction from memory based on the second instruction address and store the second branch instruction into the cache unit. Optionally, the first instruction fetch unit can be represented as IFU_S.

[0159] Optionally, when the first instruction fetch unit continuously fetches instructions from memory and writes the fetched instructions into the cache unit, upon receiving the address of the second instruction, the second instruction fetch unit can first attempt to fetch the second branch instruction from the cache unit. If the second branch instruction is already stored in the cache unit, the second instruction fetch unit can directly fetch the second branch instruction from the cache unit and send it to the second decoder; if the second branch instruction is not stored in the cache, the second instruction fetch unit needs to fetch the second branch instruction from memory, write the second branch instruction into the cache unit, and then fetch the second branch instruction from the cache unit and send it to the second decoder.

[0160] Optionally, to improve the orderliness of the instruction fetching process, the second instruction fetching unit may include a second stack and a second program pointer generator.

[0161] Indicative, such as Figure 8As shown, the second instruction fetch unit 821 includes a second stack 825 and a second program pointer generator 826. The input of the second stack 825 is connected to the output of the branch processing component 850, the output of the second stack 825 is connected to the input of the second program pointer generator 826, and the output of the second program pointer generator 826 is connected to the input of the cache unit 830.

[0162] Optionally, the second stack 825 is used to store the address of the first instruction corresponding to the first branch instruction.

[0163] Optionally, the second instruction fetch unit maintains the instruction address corresponding to the branch instruction through a second stack. When an instruction branch exists and the second scheduling component schedules the second branch instruction, the second stack stores the address of the first instruction corresponding to the first branch instruction. Optionally, the second stack may also store the thread information corresponding to the first branch instruction, so that after executing the branch instruction, the processor can reassemble the thread based on the instruction address and thread information saved in the stack.

[0164] Optionally, if there is an instruction branch in the second branch instruction, the second scheduling component can push the address of the second instruction corresponding to the second sub-branch instruction in the second branch instruction onto the stack for management when scheduling the first sub-branch instruction in the second branch instruction, thereby ensuring the efficient execution of nested branch instructions.

[0165] Optionally, a second program pointer generator 826 is used to update the second program pointer based on the address of the second instruction corresponding to the second instruction.

[0166] Optionally, the second program pointer generator maintains a second program pointer, which indicates the address of the instruction corresponding to the currently fetched instruction. Optionally, to ensure the accuracy of instruction fetching, after receiving the address of the second instruction corresponding to the second branch instruction, the second program pointer generator can update the second program pointer based on the second instruction address.

[0167] Optionally, the second branch instruction can correspond to the instruction branch when the branch condition in the instruction is not met, while the first branch instruction corresponds to the instruction branch when the branch condition in the instruction is met. Optionally, the second instruction address corresponding to the second branch instruction can be the address of the next instruction to be executed in the instruction sequence, then the first instruction address corresponding to the first branch instruction is the branch jump address. Alternatively, the second instruction address corresponding to the second branch instruction can be the branch jump address, then the first instruction address corresponding to the first branch instruction is the address of the next instruction to be executed in the instruction sequence.

[0168] Optionally, the second instruction fetch unit 821 is used to fetch a second branch instruction from memory based on the updated second program pointer.

[0169] Optionally, after the second program pointer is updated, the second instruction fetch unit can fetch the second branch instruction from the instruction address indicated by the second program pointer in memory according to the updated second program pointer.

[0170] The second decoder 822 is used to decode the second branch instruction and write the decoded second branch instruction into the second buffer 823.

[0171] Optionally, considering that the processor may not understand the meaning of instructions fetched directly from memory, the second branch instruction needs to be decoded by a second decoder in order to execute subsequent instructions, and the decoded instruction is written into a second buffer, where it waits to be issued to the execution component.

[0172] The second issuing unit 824 is used to issue the second branch instruction in the second buffer 823 to the execution component 840 when the instruction issuing conditions are met.

[0173] Optionally, the second issuing unit is responsible for sending the decoded second branch instruction from the second buffer to the execution component. Optionally, for the instruction to be sent, the second issuing unit first determines whether the instruction sending conditions are met. Only if the instruction sending conditions are met will the second issuing unit send the instruction to the execution component.

[0174] Optionally, satisfying the instruction issuance conditions may include that the data required to execute the instruction is ready, the execution channel is idle and there is no register access conflict, and may also include other conditions determined based on the specific hardware design. This application embodiment does not limit these conditions.

[0175] Optionally, if it is determined that the second branch instruction meets the instruction issuance conditions, the second issuing unit issues the second branch instruction to the execution component, and the execution channel corresponding to the second thread in the execution component executes the second branch instruction.

[0176] In the above embodiments, for the first scheduling component and the second scheduling component, the instruction scheduling process is divided into three stages: instruction fetching, instruction decoding, and instruction issuing. Thus, the instruction fetching unit fetches the instruction, the decoder decodes the instruction, and the issuing unit issues the instruction to the execution component, thereby ensuring the orderly execution of the front-end instruction scheduling and improving the efficiency of instruction scheduling.

[0177] Please refer to Figure 9 The diagram illustrates a flowchart of an instruction execution method provided in an exemplary embodiment of this application. This embodiment uses the method in the instruction execution apparatus of the above embodiments as an example, where the instruction execution apparatus includes a first scheduling component, a second scheduling component, and an execution component.

[0178] The output of the first scheduling component is connected to the input of the execution component, and the output of the second scheduling component is connected to the input of the execution component.

[0179] Optionally, the first scheduling component is responsible for scheduling the instruction sequence for the first thread, the second scheduling component is responsible for scheduling the branch instruction sequence for the second thread, and the execution component includes at least two execution channels, with each execution channel corresponding to a thread.

[0180] Optionally, the first thread can be called the main thread, responsible for executing the main instruction flow. The second thread can be called a sub-thread, responsible for executing specific instruction flows. Optionally, if there are instruction branches in the instruction sequence executed by the first thread, the first thread can be responsible for executing the first branch instruction in the instruction sequence, while the second branch instruction in the instruction sequence is assigned to the second thread for execution. That is, the branch instruction sequence executed by the second thread includes a portion of the branch instructions in the instruction sequence executed by the first thread.

[0181] For example, if there is an if-else instruction branch in the instruction sequence, the first thread is responsible for executing the if branch instruction, and the second thread is responsible for executing the else branch instruction.

[0182] Optionally, to ensure that if an instruction sequence executed by the first thread contains instruction branches, the second branch instruction in the instruction sequence can be allocated to the second thread, the number of first threads and the number of second threads are the same. Optionally, the multithreaded processor may include n first threads and n second threads, in which case the first scheduling component is responsible for scheduling instruction sequences for the n first threads, and the second scheduling component is responsible for scheduling branch instruction sequences for the n second threads.

[0183] Optionally, to improve the parallelism of instruction execution, the execution channels in the execution component need to correspond one-to-one with threads, meaning each thread has its own execution channel within the execution component. Optionally, the execution component includes 2n execution channels.

[0184] The method includes the following steps:

[0185] Step 901: The first branch instruction in the instruction sequence is scheduled to the execution component by the first scheduling component. The first branch instruction corresponds to the first instruction branch in the instruction sequence.

[0186] Step 902: The second branch instruction in the instruction sequence is scheduled to the execution component through the second scheduling component. The second branch instruction corresponds to the second instruction branch in the instruction sequence.

[0187] Optionally, in the process of improving instruction execution efficiency using pipeline technology, when there are instruction branches in the instruction sequence, since the branch jump conditions corresponding to the instruction branches may not have been judged yet, in order to avoid pipeline stalls, in a multi-threaded processor, the first branch instruction and the second branch instruction of the instruction sequence can be executed by two threads respectively.

[0188] Optionally, to improve the efficiency of the instruction pipeline, the position of instructions in the instruction sequence can be changed by the scheduling component to reorder the instructions. Optionally, when there are instruction branches in the instruction sequence, the first scheduling component can be used to schedule the first branch instruction in the instruction sequence to the execution component, and the second scheduling component can be used to schedule the second branch instruction in the instruction sequence to the execution component.

[0189] In this instruction sequence, the first branch instruction corresponds to the first instruction branch, and the second branch instruction corresponds to the second instruction branch. For example, in an if-else instruction, the first branch instruction can be an if branch instruction, and the second branch instruction can be an else branch instruction.

[0190] Optionally, instruction scheduling may include three stages: instruction fetch, instruction decoding, and instruction issuance. Instruction fetch can be performed by retrieving the instruction sequence from memory through the instruction fetch unit, or by retrieving the instruction sequence from the cache through the instruction fetch unit. Instruction decoding involves decoding the instructions into a format that the processor can understand and execute. Instruction issuance involves sequentially issuing the instruction sequence to the corresponding execution units, which then execute the instruction sequence.

[0191] Optionally, if there are no instruction branches in the instruction sequence, the first scheduling component is used to schedule the instruction sequence to the execution component in sequence, while the second scheduling component is idle; if there are instruction branches in the instruction sequence, the first scheduling component is used to schedule a portion of the branch instructions in the instruction sequence to the execution component, while the second scheduling component is used to schedule another portion of the branch instructions in the instruction sequence to the execution component.

[0192] Step 903: Execute the first branch instruction and the second branch instruction in parallel through at least two execution channels in the execution component.

[0193] Optionally, the execution component includes at least two execution channels, with each channel corresponding one-to-one with a thread. That is, the first thread and the second thread each have their own execution channel. Thus, after the execution component receives the first branch instruction and the second branch instruction scheduled by the first scheduling component and the second scheduling component, the execution component can execute the first branch instruction and the second branch instruction in parallel through the respective execution channels of each thread. In other words, while the execution channel corresponding to the first thread is executing the first branch instruction, the execution channel corresponding to the second thread is simultaneously executing the second branch instruction, without any issue of execution channels being idle due to instruction branches.

[0194] Optionally, after both the first branch instruction and the second branch instruction have been executed, the execution component may temporarily store the execution result of the first instruction corresponding to the first branch instruction and the execution result of the second instruction corresponding to the second branch instruction. After the instruction pipeline completes the branch jump condition judgment, the execution data of one of the branch instructions that does not meet the branch jump condition will be deleted to optimize storage space.

[0195] In summary, in this embodiment, by setting corresponding scheduling components for different threads, with the first scheduling component responsible for scheduling instruction sequences for the first thread and the second scheduling component responsible for scheduling branch instruction sequences for the second thread, and by mapping the execution channels in the execution component to threads one-to-one, it is possible to schedule the first branch instruction in the instruction sequence to the execution component through the first scheduling component and the second branch instruction in the instruction sequence to the execution component when there are branches in the instruction sequence. This allows at least two execution channels of the execution component to execute the first branch instruction and the second branch instruction in parallel, avoiding the problem of idle execution channels caused by serial execution of branch instructions. This improves the utilization rate of the execution components in the processor and thus improves instruction execution efficiency.

[0196] Please refer to Figure 10 This document illustrates a flowchart of an instruction execution method provided in an exemplary embodiment of this application. This embodiment uses the method applied to the instruction execution apparatus in the above embodiments as an example for description. The method includes the following steps:

[0197] Step 1001: If there are instruction branches in the instruction sequence, the first branch instruction in the instruction sequence is assigned to the first scheduling component through the branch processing component, and the second branch instruction in the instruction sequence is assigned to the second scheduling component.

[0198] Optionally, the branch processing component can determine whether an instruction is a branch instruction based on its opcode. For example, for a conditional branch instruction, which contains a condition code field, the branch processing component determines that the instruction has an instruction branch if it detects the presence of a condition code in the instruction. Thus, the branch processing component can assign the first branch instruction to the first scheduling component and the second branch instruction to the second scheduling component.

[0199] Optionally, the branch processing component includes a first branch processing unit, a multiplexer, and a status register.

[0200] Optionally, if there are instruction branches in the instruction sequence, the branch processing component will allocate a second branch instruction to the second scheduling component. The second branch instruction may include a single sub-instruction, multiple sub-instructions, or multiple sub-branch instructions. This application embodiment does not limit this.

[0201] Optionally, when the branch processing component assigns a second branch instruction to the second scheduling component, it signifies that the second thread starts, begins processing the second branch instruction, and enters a busy state. After the execution component executes the second branch instruction through the execution channel corresponding to the second thread and obtains the execution result of the second instruction, it signifies that the second thread enters an idle state, and the branch processing component can continue to assign branch instructions to the second scheduling component.

[0202] Optionally, the status register is used to store the status information of the second thread and input the status information into the multiplexer. The multiplexer can then determine whether to transmit the instruction address to the second scheduling component based on the status information. Optionally, when the second thread is in an idle state, its corresponding status information can be set to 0; when the second thread is in a busy state, its corresponding status information can be set to 1.

[0203] Optionally, the first branch processing unit is responsible for processing instruction branches in the instruction sequence executed by the first thread. If an instruction branch is detected in the instruction sequence executed by the first thread, the first branch processing unit needs to further determine the first branch instruction and the second branch instruction in the instruction sequence, and allocate the first branch instruction to the first scheduling component and the second branch instruction to the second scheduling component.

[0204] Step 1002: The branch processing component transmits the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction to the first scheduling component and the second scheduling component.

[0205] Optionally, when the branch processing component detects the existence of an instruction branch, it can also calculate the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction.

[0206] Optionally, for conditional branch instructions, the instruction typically includes an offset, which indicates the address of one of the branch instructions relative to the current instruction. Optionally, for the first branch instruction, its corresponding first instruction address can be the current instruction address plus the number of bytes in a single instruction; for the second branch instruction, its corresponding second instruction address is the current instruction address plus the number of bytes in a single instruction plus the offset.

[0207] Furthermore, after obtaining the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction, the branch processing component can transmit the instruction address to the scheduling component, which then schedules the instructions based on the instruction address.

[0208] Optionally, to improve the efficiency and accuracy of branch instruction execution, branch jumps can be implemented quickly after the branch jump condition is determined. When assigning the first branch instruction to the first scheduling component, the branch processing component can simultaneously transmit the second instruction address to the first scheduling component, in addition to transmitting the first instruction address, so that the first scheduling component can temporarily store the second instruction address. Similarly, when assigning the second branch instruction to the second scheduling component, the branch processing component can simultaneously transmit the first instruction address to the second scheduling component, in addition to transmitting the second instruction address, so that the second scheduling component can temporarily store the first instruction address.

[0209] Optionally, if an instruction branch is detected in the instruction sequence executed by the first thread, the first branch processing unit calculates the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction, and transmits the first instruction address and the second instruction address to the first scheduling component.

[0210] Optionally, during the execution of the first branch instruction by the first thread, the first branch processing unit is also responsible for detecting whether there is an instruction branch in the first branch instruction. If there is an instruction branch in the first branch instruction, the unit calculates the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the first branch instruction, and inputs the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the first branch instruction to the first scheduling component.

[0211] Optionally, in addition to inputting the first instruction address and the second instruction address to the first scheduling component, the first branch processing unit also needs to input the first instruction address and the second instruction address to the multiplexer, so that the multiplexer can determine whether to transmit the first instruction address and the second instruction address to the second scheduling component based on the status information of the second thread.

[0212] Optionally, after receiving the first instruction address and the second instruction address input by the first branch processing unit, the multiplexer can transmit the first instruction address and the second instruction address to the second scheduling component if the status information indicates that the second thread is in an idle state; otherwise, if the status information indicates that the second thread is in a busy state, the first instruction address and the second instruction address will not be transmitted to the second scheduling component.

[0213] Optionally, considering that the second branch instruction may contain sub-branch instructions when the second thread is busy, i.e., during the execution of the second branch instruction by the second thread, the branch processing component may also include a second branch processing unit in order to improve the instruction execution efficiency of the second thread.

[0214] Optionally, during the execution of the second branch instruction by the second thread, the second branch processing unit is responsible for detecting whether there is an instruction branch in the second branch instruction. If there is an instruction branch in the second branch instruction, it calculates the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the second branch instruction, and inputs the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction in the second branch instruction into the multiplexer.

[0215] Optionally, if the received status information indicates that the second thread is in a busy state, and the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction are received from the second branch processing unit, the multiplexer can directly transmit the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction to the second scheduling component, and the second scheduling component can continue to schedule the sub-branch instructions in the second branch instruction.

[0216] Step 1003: Based on the first instruction address, the first branch instruction is scheduled to the execution component through the first scheduling component.

[0217] Optionally, after receiving the first instruction address and the second instruction address, the first scheduling component can store the second instruction address, retrieve the first branch instruction from memory or cache according to the first instruction address, decode the first branch instruction, and then transmit the decoded first branch instruction to the execution component.

[0218] Optionally, in the instruction pipeline, the first scheduling component continuously fetches instructions from memory and writes the fetched instructions into a cache. In one possible implementation, if a first instruction address is received and the cache already contains the first branch instruction corresponding to the first instruction address, the first scheduling component directly schedules the first branch instruction in the cache to the execution component. In another possible implementation, if a first instruction address is received and the cache does not contain the first branch instruction corresponding to the first instruction address, the first scheduling component needs to fetch the first branch instruction from memory and schedule the first branch instruction to the execution component.

[0219] Step 1004: Based on the second instruction address, the second branch instruction is scheduled to the execution component through the second scheduling component.

[0220] Optionally, after receiving the first instruction address and the second instruction address, the second scheduling component can store the first instruction address, retrieve the second branch instruction from memory or cache according to the second instruction address, decode the second branch instruction, and then transmit the decoded second branch instruction to the execution component.

[0221] Optionally, if the first scheduling component continuously fetches instructions from memory and writes the fetched instructions into the cache, the second scheduling component, upon receiving the address of the second instruction, can first attempt to fetch the second branch instruction from the cache. If the second branch instruction is already stored in the cache, the second scheduling component can directly schedule the second branch instruction in the cache to the execution component; if the second branch instruction is not stored in the cache, the second scheduling component needs to fetch the second branch instruction from memory and schedule the second branch instruction to the execution component.

[0222] Step 1005: Provide first register data for the first branch instruction and second register data for the second branch instruction through the register file.

[0223] Optionally, a register file can also be called a register set. A register file includes a series of registers, each with a unique identifier, such as registers r1, r2, r3, etc. The registers store data and address information used during program execution. Optionally, the register file includes multiple read and write ports, allowing data to be read from and written to multiple registers simultaneously.

[0224] Optionally, the register file can be used to provide first register data for the first branch instruction and second register data for the second branch instruction.

[0225] Optionally, to improve the access efficiency of the register file, the register file is usually divided into at least two storage banks, each with an independent access port, thereby allowing parallel access to multiple storage banks.

[0226] Optionally, register addresses are typically mapped to different memory banks according to certain rules. For example, they can be mapped using consecutive address mapping, where consecutive register addresses are mapped to different memory banks. Taking a register file divided into 32 registers, with each bank containing 8 registers, as an example, registers at addresses 0 to 7 would be mapped to Bank 0, registers at addresses 8 to 15 would be mapped to Bank 1, and so on. Alternatively, they can be mapped using circular address mapping, where register addresses are cyclically mapped to different banks. Optionally, the address mapping in the register file can be dynamic; for example, banks can be allocated according to the current data access mode and requirements to reduce bank conflicts.

[0227] In this embodiment, to ensure that the first thread and the second thread can simultaneously access the same memory bank in the register file during the parallel execution of the first branch instruction and the second branch instruction, each memory bank in the register file is further divided into at least two sub-memory banks, with each sub-memory bank corresponding to a thread. Optionally, to satisfy the parallel execution of instructions by n first threads and n second threads, each memory bank is divided into 2n sub-memory banks, so that each thread can access its corresponding sub-memory bank, avoiding access conflicts and improving the access efficiency of the register file.

[0228] Step 1006: Based on the data in the first register, execute the first branch instruction through the execution channel corresponding to the first thread in the multiple instruction multiple data unit.

[0229] Optionally, a multiple instruction multiple data unit (MIB) is used to read first register data from the sub-memory bank corresponding to the first thread in the register file, and to perform instruction operations, such as arithmetic operations and logical operations, based on the obtained first register data. Then, after obtaining the execution result of the first instruction corresponding to the first branch instruction, the execution result of the first instruction is written into the sub-memory bank corresponding to the first thread in the register file.

[0230] Step 1007: Based on the data in the second register, execute the second branch instruction through the execution channel corresponding to the second thread in the multiple instruction multiple data unit.

[0231] Optionally, a multiple instruction multiple data unit (MIB) is used to read second register data from the sub-memory of the second thread in the register file, and to perform instruction operations, such as arithmetic operations and logical operations, based on the obtained second register data. After obtaining the execution result of the second instruction corresponding to the second branch instruction, the execution result of the second instruction is written into the sub-memory of the second thread in the register file.

[0232] In the above embodiments, in the branch processing component, the instructions executed by the first thread are processed by the first branch processing unit. If there are instruction branches in the instruction sequence executed by the first thread, the first branch processing unit outputs the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction. The scheduling component then schedules the instructions based on these instruction addresses, improving the accuracy of instruction scheduling. Furthermore, the second branch processing unit processes the sub-branch instructions present in the second branch instruction, ensuring the effective scheduling and execution of nested branch instructions and optimizing the efficiency of parallel execution of branch instructions.

[0233] In the front-end instruction scheduling part, by setting up corresponding scheduling components for different threads, the first scheduling component schedules the first branch instruction, and the second scheduling component schedules the second branch instruction, thus ensuring the efficiency of front-end instruction scheduling.

[0234] In the back-end instruction execution section, by dividing each memory bank in the register file into at least two sub-memory banks, and ensuring that each sub-memory bank corresponds one-to-one with a thread, the first and second threads can read the register data required for executing branch instructions from the register file in parallel, improving the instruction access efficiency in the register file. Furthermore, by corresponding each execution channel within the multi-instruction multiple-data unit (MIB) to a thread, the branch instructions corresponding to each thread can be executed in parallel within the MIB, improving the parallel execution degree of branch instructions.

[0235] It should also be noted that the description of the embodiments of the instruction execution method can be found in the description of the embodiments of the instruction execution device provided in the above embodiments, and will not be repeated here.

[0236] The solutions shown in the above embodiments of this application can be applied to chips. Specifically, this application also provides a chip that includes at least one instruction execution device as shown in the various embodiments described.

[0237] Optionally, the chip may include a processor, such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), or other processors that require access to memory units. This application embodiment does not limit this.

[0238] This application also provides a board card, which is provided with the chip described above.

[0239] This board may include a printed circuit board (PCB) whose supported interface types match the chip, which can be connected to an integrated circuit board. For example, this board can be a single-board computer, a graphics card, a sound card, etc. Alternatively, the PCB may be a motherboard, with the chip directly connected to it. This board can also be a main control board, a line card, a network card, etc.

[0240] This application also provides a computer device, which in some embodiments may be a server.

[0241] See Figure 11 , Figure 11 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application.

[0242] Specifically, the computer device 1100 includes a system bus 1101, a board 1102, and other devices 1104. The board 1102 includes a chip 1103. The chip 1103 includes a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU).

[0243] Optionally, other devices 1104 include system memory consisting of random access memory and read-only memory, a basic input / output (I / O) system that facilitates information transfer between various devices within the computer, and a mass storage device for storing the operating system, applications, and other program modules. The basic input / output system includes a display for showing information and input devices such as a mouse and keyboard for user input. Both the display and the input devices are connected to the processing unit via an input / output controller connected to the system bus 1101. The basic input / output system may also include an input / output controller for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller also provides output to a display screen, printer, or other types of output devices.

[0244] The mass storage device is connected to the processing unit via a mass storage controller connected to the system bus 1101. The mass storage device and its associated computer-readable media provide non-volatile storage for the computer device 1100. That is, the mass storage device may include computer-readable media such as a hard disk or drive.

[0245] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The aforementioned system memories and mass storage devices can be collectively referred to as memory.

[0246] The memory stores one or more programs, which are configured to be executed by one or more processing units. The one or more programs contain instructions for implementing the methods described above, and the processing units execute the one or more programs to implement the methods provided in the various method embodiments described above.

[0247] According to various embodiments of this application, the computer device 1100 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 1100 can be connected to a network via a network interface unit connected to the system bus 1101, or it can use a network interface unit to connect to other types of networks or remote computer systems.

[0248] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0249] The above are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An instruction execution device, characterized in that, The device includes a first scheduling component, a second scheduling component, and an execution component. The output of the first scheduling component is connected to the input of the execution component, and the output of the second scheduling component is connected to the input of the execution component. The first scheduling component is responsible for scheduling instruction sequences for the first thread, and the second scheduling component is responsible for scheduling branch instruction sequences for the second thread. The branch instruction sequence includes a portion of the branch instructions in the instruction sequence. The execution component includes at least two execution channels, and the at least two execution channels correspond one-to-one with the threads. The first scheduling component is configured to schedule the first branch instruction in the instruction sequence to the execution component, wherein the first branch instruction corresponds to the first instruction branch in the instruction sequence; The second scheduling component is used to schedule the second branch instruction in the instruction sequence to the execution component, wherein the second branch instruction corresponds to the second instruction branch in the instruction sequence; The execution component is used to execute the first branch instruction and the second branch instruction in parallel through the at least two execution channels.

2. The apparatus according to claim 1, characterized in that, The device includes a branch processing component, the input of which is connected to the output of the execution component, the output of which is connected to the input of the first scheduling component, and the output of which is connected to the input of the second scheduling component. The branch processing component is configured to, when there is an instruction branch in the instruction sequence, assign the first branch instruction in the instruction sequence to the first scheduling component, and assign the second branch instruction in the instruction sequence to the second scheduling component; The branch processing component is further configured to transmit the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction to the first scheduling component and the second scheduling component; The first scheduling component is configured to schedule the first branch instruction to the execution component based on the first instruction address; The second scheduling component is used to schedule the second branch instruction to the execution component based on the second instruction address.

3. The apparatus according to claim 2, characterized in that, The branch processing component includes a first branch processing unit, a multiplexer, and a status register; The input of the first branch processing unit is connected to the output of the execution component, the output of the first branch processing unit is connected to the input of the multiplexer, the output of the first branch processing unit is connected to the first scheduling component, the output of the status register is connected to the selection terminal of the multiplexer, and the output of the multiplexer is connected to the second scheduling component. The status register is used to store the status information of the second thread and input the status information into the multiplexer; The first branch processing unit is configured to input the first instruction address corresponding to the first branch instruction and the second instruction address corresponding to the second branch instruction to the first scheduling component when there is an instruction branch in the instruction sequence executed by the first thread; The first branch processing unit is further configured to input the first instruction address and the second instruction address to the multiplexer; The multiplexer is used to transmit the first instruction address and the second instruction address to the second scheduling component when the status information indicates that the second thread is in an idle state.

4. The apparatus according to claim 3, characterized in that, The branch processing component further includes a second branch processing unit, the input of which is connected to the output of the execution component, and the output of which is connected to the input of the multiplexer. The second branch processing unit is used to input the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction into the multiplexer when there is an instruction branch in the second branch instruction; The multiplexer is used to transmit the first instruction address corresponding to the first sub-branch instruction and the second instruction address corresponding to the second sub-branch instruction to the second scheduling component when the status information indicates that the second thread is in a busy state. The second scheduling component is used to serially schedule the first sub-branch instruction and the second sub-branch instruction.

5. The apparatus according to claim 2, characterized in that, The execution component includes a register file and a multiple instruction multiple data unit. The input of the register file is connected to the output of the first scheduling component, the input of the register file is connected to the output of the second scheduling component, and the input of the register file is connected to the output of the multiple instruction multiple data unit. The output of the register file is connected to the input of the multiple instruction multiple data unit, and the output of the register file is connected to the input of the branch processing component. The register file is used to provide first register data for the first branch instruction and second register data for the second branch instruction; The multiple instruction multiple data unit is used to execute the first branch instruction based on the first register data through the execution channel corresponding to the first thread; The multiple instruction multiple data unit (MIB) is used to execute the second branch instruction based on the second register data through the execution channel corresponding to the second thread.

6. The apparatus according to claim 5, characterized in that, The register file is divided into at least two storage bodies, and each storage body is further divided into at least two sub-storage bodies, with each sub-storage body corresponding to a thread. The multiple instruction multiple data unit is used to read the first register data from the sub-memory corresponding to the first thread in the register file; The Multiple Instruction Multiple Data Unit (MID) is used to read the second register data from the sub-memory corresponding to the second thread in the register file.

7. The apparatus according to claim 6, characterized in that, The multiple instruction multiple data unit is also used for: Write the execution result of the first instruction corresponding to the first branch instruction into the sub-memory of the first thread in the register file; Write the execution result of the second instruction corresponding to the second branch instruction into the sub-memory of the second thread in the register file.

8. The apparatus according to claim 2, characterized in that, The first scheduling component includes a first instruction fetch unit, a buffer unit, a first decoder, a first buffer, and a first transmit unit; The output of the first instruction fetch unit is connected to the input of the buffer unit, the output of the buffer unit is connected to the input of the first decoder, the output of the first decoder is connected to the input of the first buffer, the output of the first buffer is connected to the input of the first transmit unit, and the output of the first transmit unit is connected to the execution component. The first instruction fetch unit is configured to fetch the first branch instruction from memory based on the first instruction address and store the first branch instruction into the cache unit; The first decoder is used to decode the first branch instruction and write the decoded first branch instruction into the first buffer; The first issuing unit is configured to issue the first branch instruction in the first buffer to the execution component when the instruction issuing conditions are met.

9. The apparatus according to claim 8, characterized in that, The first instruction fetch unit includes a first stack and a first program pointer generator; the input of the first stack is connected to the output of the branch processing component, the output of the first stack is connected to the input of the first program pointer generator, and the output of the first program pointer generator is connected to the input of the cache unit. The first stack is used to store the address of the second instruction corresponding to the second branch instruction; The first program pointer generator is used to update the first program pointer based on the address of the first instruction corresponding to the first branch instruction; The first instruction fetch unit is configured to fetch the first branch instruction from the memory based on the updated first program pointer.

10. The apparatus according to claim 2, characterized in that, The second scheduling component includes a second instruction fetch unit, a buffer unit, a second decoder, a second buffer, and a second transmit unit; The output of the second instruction fetch unit is connected to the input of the buffer unit, the output of the buffer unit is connected to the input of the second decoder, the output of the second decoder is connected to the input of the second buffer, the output of the second buffer is connected to the input of the second transmit unit, and the output of the second transmit unit is connected to the execution component. The second instruction fetch unit is used to fetch the second branch instruction from memory based on the second instruction address, and store the second branch instruction into the cache unit; The second decoder is used to decode the second branch instruction and write the decoded second branch instruction into the second buffer; The second issuing unit is configured to issue the second branch instruction in the second buffer to the execution component when the instruction issuing conditions are met.

11. The apparatus according to claim 10, characterized in that, The second instruction fetch unit includes a second stack and a second program pointer generator; the input of the second stack is connected to the output of the branch processing component, the output of the second stack is connected to the input of the second program pointer generator, and the output of the second program pointer generator is connected to the input of the cache unit. The second stack is used to store the address of the first instruction corresponding to the first branch instruction; The second program pointer generator is used to update the second program pointer based on the address of the second instruction corresponding to the second instruction; The second instruction fetch unit is used to fetch the second branch instruction from the memory according to the updated second program pointer.

12. A method for executing instructions, characterized in that, The method is used in an instruction execution device, the device including a first scheduling component, a second scheduling component, and an execution component, wherein the output terminal of the first scheduling component is connected to the input terminal of the execution component, and the output terminal of the second scheduling component is connected to the input terminal of the execution component; The first scheduling component is responsible for scheduling instruction sequences for the first thread, and the second scheduling component is responsible for scheduling branch instruction sequences for the second thread. The branch instruction sequence includes a portion of the branch instructions in the instruction sequence. The execution component includes at least two execution channels, and the at least two execution channels correspond one-to-one with the threads. The method includes: The first scheduling component schedules the first branch instruction in the instruction sequence to the execution component, whereby the first branch instruction corresponds to the first instruction branch in the instruction sequence. The second scheduling component schedules the second branch instruction in the instruction sequence to the execution component, whereby the second branch instruction corresponds to the second instruction branch in the instruction sequence. The first branch instruction and the second branch instruction are executed in parallel through at least two execution channels in the execution component.

13. A chip, characterized in that, The chip includes at least one instruction execution device as described in any one of claims 1 to 11.

14. A circuit board, characterized in that, The board is equipped with the chip as described in claim 13.

15. A computer device, characterized in that, The computer device is equipped with the board as described in claim 14.

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