A dual-power memory and microprocessor architecture
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PHYTIUM TECH CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-05-26
Smart Images
Figure CN122090890A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, specifically to a dual-power memory and microprocessor architecture. Background Technology
[0002] With the increasing urgency of low-power design requirements in the field of computer technology, Dynamic Voltage and Frequency Scaling (DVFS) technology has been widely used. To meet this design requirement, Array Dual Rail (ADR) memory has been widely used in microprocessor architecture. The components of Array Dual Rail memory operate in different voltage domains. The memory array and word line driver circuit operate in the VDDA voltage domain, while the peripheral circuits other than the memory array and word line driver circuit operate in the VDD voltage domain.
[0003] The inventors discovered that when the voltage difference between the VDD and VDDA voltage domains is large, the delay characteristics exhibited by circuits operating in different voltage domains differ significantly. The timing constraints between the control signals of the word line drive circuit and the control signals of other circuits are difficult to meet, requiring a large timing margin. While this can solve the timing violation problem, it will inevitably affect the read and write efficiency of the memory and limit the further improvement of the overall performance of the dual-power memory. Summary of the Invention
[0004] In view of this, this application aims to provide a dual-power memory and microprocessor architecture to solve the problem that the read and write efficiency of dual-power memory provided by related technologies is limited and the overall performance is difficult to improve further.
[0005] In a first aspect, this application provides a dual-power memory, comprising: The storage array operates in the first voltage domain and includes multiple storage cells with independent read and write ports; The read operation circuit operates in the second voltage domain and is connected to the read port to perform read operations; A write operation circuit for performing write operations includes a word line write operation circuit, wherein the word line write operation circuit includes a first level conversion circuit, wherein... The front-end circuit connected to the input terminal of the first level conversion circuit in the word line write operation circuit operates in the second voltage domain, and the back-end circuit connected to the output terminal of the first level conversion circuit in the word line write operation circuit operates in the first voltage domain. The back-end circuit is connected to the write port. The first level conversion circuit is used to convert the signal output by the front-end circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, so as to drive the rear-end circuit.
[0006] In one optional embodiment, the write operation circuit further includes: a write control circuit and a bit line write operation circuit, wherein, The write control circuit is connected to the word line write operation circuit and the bit line write operation circuit respectively, and controls the word line write operation circuit and the bit line write operation circuit to perform write operations; The write control circuit and the bit line write operation circuit operate in the second voltage domain.
[0007] In one optional embodiment, the write operation circuit further includes: a write control circuit and a bit line write operation circuit, wherein, The bit line write operation circuit includes a write column selection circuit connected to the write port. The write column selection circuit operates in the second voltage domain and is used to control whether to perform a bit line write operation on the connected memory cell. The write control circuit includes a write column selection decoding circuit, a second level conversion circuit, and a write column selection driving circuit connected in sequence, and the write column selection driving circuit is connected to the write column selection circuit. The write column selection decoding circuit operates in the second voltage domain; The write column selection drive circuit operates in the first voltage domain; The second level conversion circuit is used to convert the signal output by the write column select decoding circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, so as to drive the write column select driving circuit.
[0008] In one optional embodiment, the bit line write operation circuit further includes: an input data latch and drive circuit and a write bit line precharge circuit, wherein, The input data latching and driving circuit is used to receive and latch input data, and write the input data to the write bit line through the write column selection circuit; The write bit line precharge circuit is used to precharge the write bit line pair connected to the write port. The input data latch and drive circuit and the write bit precharge circuit operate in the second voltage domain.
[0009] In one alternative implementation, the plurality of storage units are arranged in a matrix; The read operation circuit includes a word line read operation circuit and a bit line read operation circuit, wherein... The word line read operation circuit is used to perform word line read operations on memory cells in the same row; The bit-line read operation circuit is used to perform bit-line read operations on the storage cells of the selected column.
[0010] In one optional embodiment, the word line reading operation circuit includes a word line decoding circuit and a word line driving circuit, wherein, The character line decoding circuit is connected to the character line driving circuit; The word line driving circuit is connected to the word line corresponding to the memory cell in the same row.
[0011] In one optional implementation, the bit line read operation circuit includes a read bit line precharge circuit, a read detection and column selection circuit, and a data latch and output drive circuit connected in sequence.
[0012] In one optional implementation, the read operation circuit further includes a read control circuit, wherein, The read control circuit is connected to the word line read operation circuit and the bit line read operation circuit respectively, and controls the word line read operation circuit and the bit line read operation circuit to perform read operations.
[0013] In one optional implementation, the operating voltage range of the second voltage domain is greater than or equal to the operating voltage range of the first voltage domain.
[0014] In a second aspect, this application provides a microprocessor architecture including at least one dual-power memory as provided in any embodiment of the first aspect of this application.
[0015] Based on the above, the dual-power memory provided in this application includes a storage array, a read operation circuit, and a write operation circuit. The write operation circuit includes a first level conversion circuit. The storage array and the subsequent circuit connected to the output of the first level conversion circuit in the write operation circuit operate in a first voltage domain. The read operation circuit and the front-end circuit connected to the input of the first level conversion circuit in the write operation circuit operate in a second voltage domain. The first level conversion circuit converts the signal output by the front-end circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, realizing the conversion between the first and second voltage domains and ensuring the normal operation of the subsequent circuits. Since the read port of the memory is unrelated to the stability and data writing capability of the storage cell, this application only places the storage cell and the subsequent circuit connected to it in the first voltage domain, and sets the read operation circuit connected to the read port in the second voltage domain. Compared with related technologies, the read operation circuit does not involve the conversion between different voltage domains, and the level conversion circuit can be eliminated. The area overhead and read delay caused by the level conversion circuit are eliminated, and the timing margin can be further reduced, which helps to improve the data read efficiency of the dual-power memory and thus improve the overall performance of the dual-power memory. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a block diagram of an array dual-power memory provided by related technologies.
[0018] Figure 2 This is a structural block diagram of a dual-power memory provided in an embodiment of this application.
[0019] Figure 3 This is a structural block diagram of another dual-power memory provided in the embodiments of this application.
[0020] Figure 4 This is a structural block diagram of another dual-power memory provided in the embodiments of this application.
[0021] Figure 5 It is a circuit topology diagram of a storage unit provided by related technologies.
[0022] Figure 6 This is a structural block diagram of a dual-power interface memory provided in related technologies.
[0023] Figure 7 This is a structural block diagram of another dual-power memory provided in the embodiments of this application.
[0024] Figure 8 This is a structural block diagram of another dual-power memory provided in the embodiments of this application.
[0025] Figure 9 This is a structural block diagram of another dual-power memory provided in the embodiments of this application.
[0026] Figure 10 This is a structural block diagram of another dual-power memory provided in the embodiments of this application.
[0027] Figure 11 This is a circuit topology diagram of another storage unit provided by related technologies. Detailed Implementation
[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0029] With the continuous evolution of semiconductor technology and the miniaturization of semiconductor manufacturing processes, the industry's demand for low-power design is becoming increasingly urgent. Low-power design is not only an important way to continue to improve the performance of microprocessor architecture, but also an effective solution to improve the lifespan and reliability of microprocessor architecture. Dynamic Voltage and Frequency Scaling (DVFS) technology can dynamically adjust the operating voltage and frequency according to the load conditions to achieve a balance between performance and power consumption. In recent years, it has been widely used as an effective means of low-power design.
[0030] DVFS technology requires that the operating voltage of each component within the microprocessor architecture can be dynamically adjusted within a wide range. To meet this design requirement, array dual-power (ADR) memory is widely used in microprocessor architectures. A typical architecture of array dual-power memory can be found in [reference needed]. Figure 1 As shown, it includes a control circuit, a data input circuit, a data output circuit, a word line decoding circuit, a level conversion circuit, a word line driving circuit, and a storage array. The components of the dual-power array memory operate in different voltage domains, combined with... Figure 1 As shown in the gray area, only the memory array and word line driver circuit operate in the VDDA voltage domain, while other circuits besides the memory array and word line driver circuit operate in the VDD voltage domain.
[0031] The inventors discovered that when the voltage difference between the VDD and VDDA voltage domains is large, the delay characteristics exhibited by circuits operating in different voltage domains differ significantly. The timing constraints between the control signals of the word line drive circuit and the control signals of other circuits are difficult to meet, requiring a large timing margin. While this can solve the timing violation problem, it will inevitably affect the read and write efficiency of the memory and limit the further improvement of the overall performance of the dual-power memory.
[0032] To address the aforementioned issues, this application provides a dual-power memory that places only the storage cells and their connected downstream circuits in the first voltage domain, while setting the read operation circuit connected to the read port in the second voltage domain. Compared to related technologies, the read operation circuit does not involve conversion between different voltage domains, eliminating the need for a level conversion circuit. This eliminates the area overhead and readout delay caused by the level conversion circuit, further reducing the timing margin and improving the data readout efficiency of the dual-power memory, thereby enhancing the overall performance of the dual-power memory.
[0033] The dual-power memory provided in this application includes: a memory array, a read operation circuit, and a write operation circuit.
[0034] Combination Figure 2 As shown, the storage array includes multiple storage cells, each with its own independent read and write ports. In practical applications, the multiple storage cells in a dual-power memory are arranged in a matrix, divided into multiple rows and columns. Based on the mapping relationship between data input / output ports and storage columns, different design architectures can be formed: if one data input / output bit corresponds to a single column of storage cells, it is the MUX1 architecture; if one data input / output bit corresponds to two columns of storage cells, and these two columns share the same set of data write and read circuits through column selection circuits, it constitutes the MUX2 architecture, and so on, resulting in different memory architectures.
[0035] Combination Figure 2 As shown, any memory cell includes multiple independent read and write ports, specifically including word line read ports, word line write ports, bit line read ports, and word line write ports. It should be noted that the number of each of these ports varies depending on the specific function of the memory cell and the circuit topology; please refer to relevant technical implementations for details, which will not be elaborated here. To facilitate access to each memory cell, the memory array also includes connection lines for connecting each port, combined with... Figure 2 As shown, it includes at least a read word line (RWL) for connecting the word line read ports of each memory cell, a write word line (WWL) for connecting the word line write ports, a read bit line (RBL) for connecting the bit line read ports, and a write bit line (WBL) and a write bit line complementary line (WBLB) for connecting the bit line write ports. In another optional embodiment, the read bit line may also include two paths, one is RBLA and the other is RBLB.
[0036] In the dual-power memory provided in this embodiment, the memory array operates in a first voltage domain (shown in gray). Considering practical application requirements, this first voltage domain can be the VDDA voltage domain. It is understood that the VDDA voltage domain has a smaller operating voltage adjustment range compared to the VDD voltage domain; that is, the operating voltage range of the second voltage domain mentioned in this embodiment is greater than or equal to the operating voltage range of the first voltage domain. Furthermore, generally speaking, the operating voltage of the first voltage domain should be higher than or equal to the operating voltage of the second voltage domain. Of course, there may be some applications where it is necessary to increase the voltage for a short period to improve performance. However, due to the small operating voltage range of the memory cells, it is impossible to increase it synchronously, resulting in the operating voltage of the second voltage domain being higher than that of the first voltage domain in such cases. Naturally, this difference is generally very small. For aspects of the memory array not detailed here, relevant technologies can be referenced for implementation, and will not be elaborated further here.
[0037] The read operation circuit includes word line read operation circuit, bit line read operation circuit, and read control circuit, combined with Figure 2 As shown, the word line read operation circuit is connected to the read word line, and through the read word line, it is connected to the word line read port of the memory cell to perform word line read operations on memory cells in the same row. Correspondingly, the bit line read operation circuit is connected to the read bit line, and through the read bit line, it is connected to the bit line read port of the memory cell to perform bit line read operations on the selected column of memory cells. It should be noted that, as mentioned earlier, the multiple memory cells in the memory array are arranged in a matrix, divided into different columns and rows. Each row corresponds to one read word line. Therefore, in practical applications, multiple word line read operation circuits are set, each corresponding to one read word line; correspondingly, at least one bit line read operation circuit is required, each corresponding to at least one read bit line, that is, at least one column of memory cells.
[0038] The read control circuit is connected to both the word line read operation circuit and the bit line read operation circuit (not shown in the figure), controlling them to perform read operations. In practical applications, the read control circuit includes multiple sub-circuits, including but not limited to address latch circuits, word line pre-decoding circuits, bit line decoding circuits, column selection drive circuits, and clock control circuits, which will not be listed here. For specific implementation details, please refer to relevant technical documents.
[0039] Based on the above, in the dual-power memory provided in this embodiment, the read operation circuit operates in the second voltage domain and performs read operations based on the above connection relationship. As an optional implementation, the second voltage domain can be the VDD voltage domain. Compared with the VDDA voltage domain, the voltage adjustment range of the VDD voltage domain is wider, which can more flexibly adjust the working voltage of the relevant load, thereby achieving the purpose of low power consumption operation. Of course, in practical applications, other voltage domains can also be selected according to the power network of the microprocessor architecture, as long as the working voltage range of the second voltage domain is greater than or equal to the working voltage range of the first voltage domain. These will not be listed one by one here. As for the specific implementation of the read operation circuit, it can be implemented with reference to relevant technologies, which will not be described in detail here.
[0040] The write operation circuit is used to perform write operations related to memory cells, including word line write operation circuitry, and further includes bit line write operation circuitry and write control circuitry, combined with... Figure 2 As shown, the word line write operation circuit includes a first level conversion circuit for level conversion. For ease of description, in this embodiment, the circuit connected to the input terminal of the first level conversion circuit in the word line write operation circuit is defined as the pre-stage circuit, and correspondingly, the circuit connected to the output terminal of the first level conversion circuit is defined as the post-stage circuit. Figure 2As shown, the pre-stage circuit, the first level conversion circuit, and the post-stage circuit are connected in sequence. The post-stage circuit is connected to the write port of the memory unit (specifically the word line write port) through the write word line.
[0041] Based on the above-described word line write operation circuit configuration, the front-end circuit operates in the second voltage domain. The first level conversion circuit converts the signal output from the front-end circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, driving the subsequent circuit to operate in the first voltage domain (shown in gray in the figure). It can be understood that the first level conversion circuit, as a connecting circuit between the first and second voltage domains, is used to adjust the signal voltage amplitude during cross-voltage domain signal transmission. Therefore, in Figure 2 The first level conversion circuit in the diagram is shown in half white and half gray.
[0042] Furthermore, in combination Figure 2 As shown, the word line write operation circuit is connected to the write word line, which in turn connects to the word line write port of the memory cell to perform word line write operations on memory cells in the same row. Correspondingly, the bit line write operation circuit is connected to the write bit line pair, which in turn connects to the bit line write port of the memory cell to perform bit line write operations on memory cells in the selected column. It should be noted that, as mentioned earlier, the multiple memory cells in the memory array are arranged in a matrix, divided into different columns and rows. Each row corresponds to one write word line. Therefore, in practical applications, multiple word line write operation circuits are set, each corresponding to one write word line. Correspondingly, at least one bit line write operation circuit is required, each corresponding to at least one write bit line, i.e., at least one column of memory cells.
[0043] The write control circuit is connected to both the word line write operation circuit and the bit line write operation circuit (not shown in the figure), controlling them to perform write operations. Both the write control circuit and the bit line write operation circuit operate in the second voltage domain. In practical applications, the write control circuit includes multiple sub-circuits, including but not limited to address latch circuits, word line pre-decoding circuits, bit line decoding circuits, column selection drive circuits, and clock control circuits, which will not be listed here. For specific implementation details, please refer to relevant technical specifications.
[0044] It should be noted that, Figure 2 The front-end circuit and back-end circuit connected to the first level conversion circuit shown in the embodiment can be configured in various ways in actual applications, and will vary depending on the specific implementation of the word line write operation circuit. The specific implementation of the front-end circuit and back-end circuit will not be described in detail.
[0045] See Figure 3As shown, in one optional implementation, the word line write operation circuit includes a word line decoding circuit, a first level conversion circuit, and a word line drive circuit connected in sequence. It can be understood that in the word line write operation circuit provided in this embodiment, the word line decoding circuit serves as the pre-stage circuit of the first level conversion circuit and operates in the second voltage domain. Correspondingly, the word line drive circuit serves as the post-stage circuit of the first level conversion circuit and operates in the first voltage domain. The first level conversion circuit is used to convert the signal output by the word line decoding circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, thereby driving the word line drive circuit to ensure that the word line drive circuit operates normally in the first voltage domain.
[0046] Furthermore, as another alternative implementation, Figure 3 The write line decoding circuit shown in the embodiment can also be used as a follow-up circuit to the first level conversion circuit. For details, see [link to documentation]. Figure 4 As shown, in the word line writing operation circuit provided in this embodiment, the front-end circuit operates in the second voltage domain, and its specific implementation can be referred to related technologies. The back-end circuit includes a word line decoding circuit and a word line driving circuit. The front-end circuit is connected to the input terminal of the first level conversion circuit. The output terminal of the first level conversion circuit is connected to the word line decoding circuit and the word line driving circuit in sequence. The first level conversion circuit is used to convert the signal output by the front-end circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, and drive the back-end word line decoding circuit and the word line driving circuit to ensure that they operate in the first voltage domain.
[0047] Based on the above, it can be seen that in the dual-power memory provided in this embodiment, only the memory array and the subsequent circuit connected to the memory array operate in the first voltage domain, while the other circuits in the memory operate in the second voltage domain. When the first voltage domain is the VDDA voltage domain and the second voltage domain is the VDD voltage domain, the second voltage domain has a wider operating voltage adjustment range, which allows for more flexible low-power operation control, ensuring the reliability of data reading / writing in the memory unit and meeting the power supply requirements of the memory unit.
[0048] Figure 5 This paper illustrates an optional implementation of a memory cell, which can be roughly divided into three parts: a read port composed of RPG and RPD transistors, responsible for data reading; a write port composed of NPG0 and NPG1, responsible for data writing; and a pair of inverters connected end-to-end and cross-coupled by four transistors to achieve data latching. Through research on the memory cell circuit structure, the inventors discovered that the read port of the memory is independent of the stability and data writing capability of the memory cell, and the read port can operate within a relatively wide voltage range, just like external circuits.
[0049] Based on the above, the dual-power memory provided in this embodiment places only the storage cell and its connected subsequent circuitry in the first voltage domain, and sets the read operation circuit connected to the read port in the second voltage domain. Compared with related technologies, the read operation circuit does not involve the conversion between different voltage domains, the level conversion circuit can be eliminated, the area overhead and read delay caused by the level conversion circuit can be eliminated, the timing margin can be further reduced, which helps to improve the data read efficiency of the dual-power memory, and thus improve the overall performance of the dual-power memory.
[0050] Furthermore, the read operation circuit adopts a single power supply design to avoid signal competition between multiple voltage domains. The write operation circuit adopts an array dual power supply design. The storage array and its connected subsequent circuits are maintained in the first voltage domain with a higher voltage. At the same time, the remaining circuits in the write operation circuit operate in the second voltage domain. This allows the operating voltage to be adjusted within a wide voltage range, ensuring both the data stability of the storage array and the data writing capability of the storage cells, while also enabling dynamic adjustment of the operating voltage and frequency to achieve the goal of low power consumption design.
[0051] Related technologies also provide an interface dual rail (IDR) memory, the basic structure of which can be found in [reference needed]. Figure 6 As shown, it includes a level conversion circuit, a data writing circuit, an output reading circuit, a word line decoding circuit, a word line driving circuit, a control circuit, and a memory array. The level conversion circuit is used to convert the VDD voltage domain to the VDDA voltage domain. Figure 6 The two level conversion circuits shown in the figure receive other circuits in the dual-power supply memory, all of which operate in the VDDA voltage domain.
[0052] Since all circuits other than the level conversion circuit are located in the VDDA voltage domain and cannot be adjusted with the external circuit voltage, the power consumption of the interface dual-supply memory is difficult to reduce effectively, which is far from the low-power control concept of DVSF technology. It also limits the power consumption reduction of the entire microprocessor architecture. In addition, due to the presence of the level conversion circuit at the interface end, the input signal setup time and data access time of the interface dual-supply memory will increase under normal voltage compared to single-supply memory, and the memory area will also increase.
[0053] More importantly, since part of the data readout timing path is located in the VDDA voltage domain, while the rest of the circuits are all located in the VDD voltage domain, when the voltage difference between VDD and VDDA is large, the signal delay difference between the different voltage domains is large. Compared with the slower latch clock signal outside the memory, the excessively fast memory data readout time may cause insufficient data retention time. This problem is particularly prominent in interface dual-power memory. Of course, the array dual power supply provided by related technologies also has this problem to some extent.
[0054] Compared to the dual-power interface memory provided by related technologies, the memory provided in this application embodiment only designs the storage array and the connected subsequent circuits in the VDDA voltage domain. The first level conversion circuit is located between the front-end circuit (such as the write line decoding circuit) and the subsequent circuit (such as the write line driving circuit), while other circuits are located in the VDD voltage domain. The input and output ports of the memory do not require level conversion circuits. While ensuring the stability of the storage cell and the write capability, it achieves a truly low-power design. At the same time, it avoids the problems of increased input signal setup time, slower data read speed, and longer read data retention time caused by adding level conversion circuits at the interface end in the dual-power interface design.
[0055] This application provides another dual-power memory, see [link to example]. Figure 7 As shown, in the dual-power memory provided in this embodiment, the word line read operation circuit includes a word line decoding circuit and a word line driving circuit. The word line decoding circuit is connected to the word line driving circuit, and the word line driving circuit is connected to the word line corresponding to the memory cell in the same row. The bit line read operation circuit includes a read bit line pre-charge circuit, a read detection and column selection circuit, and a data latch and output driving circuit connected in sequence. The bit line write operation circuit includes an input data latch and driving circuit, a write column selection circuit, and a write bit line pre-charge circuit. The input data latch and driving circuit receives and latches input data, and writes the input data to the write bit line through the write column selection circuit. The write bit line pre-charge circuit pre-charges the write bit line pairs connected to the write port. Referring to the dual-power memory provided in the foregoing embodiments, the word line reading operation circuit, the word line decoding circuit, the word line driving circuit, the bit line writing operation circuit, the bit line reading operation circuit, the write control circuit, and the read control circuit in the word line reading operation circuit all operate in the second voltage domain, while only the word line writing operation circuit and the memory cell in the memory array operate in the first voltage domain.
[0056] for Figure 7 The dual-power memory provided in the illustrated embodiment Figure 8 The illustrated embodiment provides optional implementations of some of the circuitry, in conjunction with... Figure 8As shown, the write bit lines, write operation circuit, and write control circuit all operate in the VDD voltage domain, allowing for flexible adjustment of the operating voltage over a wide voltage range to achieve low-power design. The write word line driver circuit operates in the VDDA voltage domain to ensure the write capability of the memory cell. A first level conversion circuit is inserted between the write word line driver circuit and the write word line decoding circuit to achieve the conversion from the VDD voltage domain to the VDDA voltage domain.
[0057] The read bit line to read line read operation circuit, as well as the read control circuit, read word line decoding circuit, and read word line drive circuit, all operate in the VDD voltage domain. On the one hand, this can achieve the design goal of low power consumption. On the other hand, the single voltage domain design avoids the competition between timing control signals of different voltage domains, as well as the resulting slowdown and read data hold time issues. It also avoids the problems of increased area and slowed timing caused by inserting level conversion circuits in related technologies.
[0058] This application embodiment also provides another dual-power memory, combined with Figure 9 as well as Figure 10 As shown, in the dual-power memory provided in this embodiment, the bit line write operation circuit includes an input data latch and drive circuit, a write column selection circuit, and a write bit line precharge circuit. The write column selection circuit is connected to the write port of the memory cell through the write bit line pair. The write column selection circuit operates in the second voltage domain and is used to control whether to perform a write bit line operation on the connected memory cell. In conjunction with the foregoing, the other circuits in the bit line write operation circuit also operate in the second voltage domain.
[0059] Furthermore, as mentioned earlier, the write control circuit includes multiple sub-circuits for implementing different functions. Figure 10 The diagram illustrates the relevant sub-circuits for controlling the write column selection circuit, specifically including a write column selection decoding circuit, a second level conversion circuit, and a write column selection driving circuit connected in sequence. The write column selection driving circuit is connected to the write column selection circuit in the bit line write operation circuit. Further, the write column selection decoding circuit operates in the second voltage domain, and the second level conversion circuit converts the signal output by the write column selection decoding circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, driving the write column selection driving circuit so that the write column selection driving circuit operates in the first voltage domain. The configuration of the voltage domains of other circuits in the dual-power memory can be referred to the relevant content of the foregoing embodiments, and will not be repeated here.
[0060] In summary, the dual-power memory provided in this embodiment operates the write column selection driver circuit in the first voltage domain (e.g., the VDDA voltage domain). A second level conversion circuit is configured between the write column selection driver circuit and the write column selection decoding circuit. Considering that the write operation is a competition process between the write driver circuit (including the transmission gate in the write column selection circuit) and the memory cell, since the memory cell is located in the first voltage domain and the operating voltage of the first voltage domain is generally higher than that of the second voltage domain, if the write column selection driver circuit operates in the second voltage domain, when the operating voltages of the first and second voltage domains are large, the driving capability of the write column selection driver circuit is small and cannot compete with the pull-up transistor of the memory cell, which will eventually lead to write failure. In this embodiment, the write column selection driver circuit is arranged in the first voltage domain, which can increase the driving capability of the bit line to ground, thereby enhancing the write capability of the memory cell and improving the success rate of data writing.
[0061] It should be noted that the storage units mentioned in the foregoing embodiments can be adopted. Figure 5 The circuit topology shown can also utilize other memory units with independent read / write ports. Specifically, taking... Figure 11 Taking the shown memory cell as an example, this memory cell has a read port on each of its left and right sides, consisting of a read control transistor (RPG0 / RPG1) and a read pull-down transistor (RPD0 / RPD1), for a total of two read ports and one write port. Figure 5 The difference between the storage units shown is that Figure 11 The storage cell shown includes two read word lines and two read bit lines, namely read word line RWLA and read word line RWLB, and read bit lines RBLA and read bit lines RBLB. The definitions of the remaining word lines and bit lines can be found in the aforementioned related content and will not be repeated here. Based on Figure 11 The storage unit shown can also be used to construct a dual-power memory similar to any of the aforementioned embodiments. Of course, Figure 11 The storage cell shown and its associated write word line driver circuit also need to operate in the first voltage domain. Since the read and write ports are independent of each other, the read and write operation circuits are also independent of each other. The write operation circuit adopts an array dual-power supply design, while the two read operation circuits each adopt a single-power supply design. This achieves low power consumption while realizing better speed and area, avoiding the shortcomings of traditional array dual-power supply memories.
[0062] It should also be noted that the dual-power memory provided in the foregoing embodiments involves various types of functional circuits, such as read control circuits, write control circuits, data latch and output drive circuits, read detection and column selection circuits, and read bit line precharge circuits. The specific functions and circuit topologies of these related functional circuits in the dual-power memory can be implemented with reference to relevant technologies, and this application does not limit them.
[0063] This application also provides a microprocessor architecture including at least one dual-power memory provided in any of the foregoing embodiments.
[0064] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.
[0065] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.
[0066] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.
[0067] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.
[0068] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.
[0069] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.
Claims
1. A dual-power memory, characterized in that, include: The storage array operates in the first voltage domain and includes multiple storage cells with independent read and write ports; The read operation circuit operates in the second voltage domain and is connected to the read port to perform read operations; A write operation circuit for performing write operations includes a word line write operation circuit, wherein the word line write operation circuit includes a first level conversion circuit, wherein... The front-end circuit connected to the input terminal of the first level conversion circuit in the word line write operation circuit operates in the second voltage domain, and the back-end circuit connected to the output terminal of the first level conversion circuit in the word line write operation circuit operates in the first voltage domain. The back-end circuit is connected to the write port. The first level conversion circuit is used to convert the signal output by the front-end circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, so as to drive the rear-end circuit.
2. The dual-power memory according to claim 1, characterized in that, The write operation circuit further includes: a write control circuit and a bit line write operation circuit, wherein... The write control circuit is connected to the word line write operation circuit and the bit line write operation circuit respectively, and controls the word line write operation circuit and the bit line write operation circuit to perform write operations; The write control circuit and the bit line write operation circuit operate in the second voltage domain.
3. The dual-power memory according to claim 1, characterized in that, The write operation circuit further includes: a write control circuit and a bit line write operation circuit, wherein... The bit line write operation circuit includes a write column selection circuit connected to the write port. The write column selection circuit operates in the second voltage domain and is used to control whether to perform a bit line write operation on the connected memory cell. The write control circuit includes a write column selection decoding circuit, a second level conversion circuit, and a write column selection driving circuit connected in sequence, and the write column selection driving circuit is connected to the write column selection circuit. The write column selection decoding circuit operates in the second voltage domain; The write column selection drive circuit operates in the first voltage domain; The second level conversion circuit is used to convert the signal output by the write column select decoding circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain, so as to drive the write column select driving circuit.
4. The dual-power memory according to claim 3, characterized in that, The bitline write operation circuit further includes: an input data latch and drive circuit and a write bitline precharge circuit, wherein... The input data latching and driving circuit is used to receive and latch input data, and write the input data to the write bit line through the write column selection circuit; The write bit line precharge circuit is used to precharge the write bit line pair connected to the write port. The input data latch and drive circuit and the write bit precharge circuit operate in the second voltage domain.
5. The dual-power memory according to claim 1, characterized in that, The multiple storage units are arranged in a matrix; The read operation circuit includes a word line read operation circuit and a bit line read operation circuit, wherein... The word line read operation circuit is used to perform word line read operations on memory cells in the same row; The bit-line read operation circuit is used to perform bit-line read operations on the storage cells of the selected column.
6. The dual-power memory according to claim 5, characterized in that, The word line reading operation circuit includes a word line decoding circuit and a word line driving circuit, wherein, The character line decoding circuit is connected to the character line driving circuit; The word line driving circuit is connected to the word line corresponding to the memory cell in the same row.
7. The dual-power memory according to claim 5, characterized in that, The bit line read operation circuit includes a read bit line precharge circuit, a read detection and column selection circuit, and a data latch and output drive circuit connected in sequence.
8. The dual-power memory according to claim 5, characterized in that, The read operation circuit also includes a read control circuit, wherein... The read control circuit is connected to the word line read operation circuit and the bit line read operation circuit respectively, and controls the word line read operation circuit and the bit line read operation circuit to perform read operations.
9. The dual-power memory according to any one of claims 1 to 8, characterized in that, The operating voltage range of the second voltage domain is greater than or equal to the operating voltage range of the first voltage domain.
10. A microprocessor architecture, characterized in that, It includes at least one dual-power memory as described in any one of claims 1 to 9.