Method for dynamically trimming operation voltage of flash memory, electronic equipment and storage medium

By dynamically adjusting the flash memory operating voltage, the bit line, control gate, and word line voltages and levels are adjusted chip by chip. This solves the problem of chip characteristic differences caused by process fluctuations, improves wafer yield and reliability, and ensures normal chip operation and data retention capabilities.

CN122090904APending Publication Date: 2026-05-26HUA HONG SEMICON WUXI LTD
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Patent Information

Application Number
CN202610017877.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-01-07
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

In the manufacturing of large-size flash memory chips, due to the differences in physical characteristics between chips and within the same chip's storage bits, existing adjustment methods adjust all chips to a uniform target voltage. This results in some chips having voltages that are too low or too high, affecting yield and reliability.

Method used

The method of dynamically adjusting the flash memory operating voltage is adopted. By adjusting the bit line, control gate and word line voltage and level of each chip, the optimal operating voltage of each chip is dynamically determined. This includes setting the initial voltage, programming-applying voltage-reading-judging loop, and finding the optimal voltage and level based on the programming depth and physical characteristics of each chip.

Benefits of technology

It significantly improves wafer yield and chip reliability, enhances product quality, reduces the failure rate in wafer-level reliability testing, and improves chip data retention capabilities.

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Abstract

The invention provides a method for dynamically trimming the operating voltage of a flash memory, electronic equipment and a storage medium, and relates to the field of semiconductor testing. The method comprises the following steps: trimming a bit line voltage and a control gate voltage of the flash memory chip to preset values; adjusting the voltage gear of the control gate and keeping the voltage gear of the bit line unchanged to program the array; adjusting word line voltage and setting a reading gear; reading an array state, and if the array state passes, recording a current voltage and a gear as an operation voltage; and if not, adjusting a bit line or a control gate voltage gear, and circularly programming and reading until the bit line or the control gate voltage gear passes or reaches the highest gear. According to the method, the optimal operation voltage is dynamically determined one by one, the problem that programming is too deep or too shallow due to unified target voltage trimming is solved, current increase after baking is covered, and the wafer yield and the chip reliability are remarkably improved.
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