A Dynamic Adjustment Method for Mobile Power Stability Based on Time-Series Modeling

Abstract

This invention discloses a dynamic adjustment method for power stability of a mobile power bank based on time-series modeling, relating to the field of mobile power bank technology. The method includes: real-time acquisition of the output current and voltage waveforms of the mobile power bank within a continuous time unit; extraction of the periodic decay characteristics of the waveform oscillation frequency and the instantaneous response hysteresis characteristics during load abrupt changes; establishment of a power compensation function based on the correlation between the decay and hysteresis characteristics; prediction of the probability of load abrupt changes in subsequent time units using the compensation function; generation of dual adjustment parameters including amplitude compensation and phase calibration direction when a phase shift is detected between the current waveform oscillation frequency and the historical decay trajectory; real-time adjustment of the switching device conduction sequence based on the dual parameters; comparison of the actual output waveform with the expected trajectory of the compensation function after adjustment; and automatic backtracking correction of the decay rate weight coefficient when the deviation exceeds a threshold. This invention effectively suppresses voltage drops, overshoot, and high-frequency oscillations, ensuring stable operation of connected devices.

Description

Technical Field

[0001] This invention relates to the field of mobile power technology, and in particular to a method for dynamic adjustment of mobile power stability based on time-series modeling. Background Technology

[0002] The stability of a power bank's output power directly affects the reliability of connected devices. Currently, mainstream regulation methods rely primarily on the passive response mechanism of hardware circuitry to load current. However, when connected to high-power devices or experiencing rapid load changes, the inherent delay in current detection and feedback often leads to transient voltage drops or overshoots in the output voltage. These power fluctuations can cause malfunctions in connected devices in minor cases, and in severe cases, even permanent damage to delicate components.

[0003] To address this issue, existing technologies attempt to provide buffering by increasing energy storage capacitors or suppressing fluctuations by optimizing feedback loop parameters. However, capacitor expansion is strictly limited by the size of the power bank, while fixed parameter strategies struggle to adapt to diverse and abrupt changes, failing to provide sufficient flexibility and adaptability. In recent years, although some research has introduced load prediction algorithms to adjust power output in advance through prediction, the complex timing modeling of these algorithms often faces computational bottlenecks in mobile embedded systems, leading to a disconnect between prediction and control, and failing to effectively achieve the desired control effect.

[0004] Therefore, how to achieve proactive power pre-adjustment before load changes, that is, to adjust the output power of the power bank in advance before the load changes to meet the upcoming load demand, while meeting the requirements of real-time performance, lightweight design and low cost of the power bank, has become a technical challenge that the industry urgently needs to overcome. Summary of the Invention

[0005] In view of this, the present invention proposes a dynamic adjustment method for mobile power stability based on time-series modeling to solve the problem of power instability caused by sudden load changes in mobile power in the prior art.

[0006] The specific technical solution of this invention is as follows: A dynamic adjustment method for mobile power stability based on time-series modeling includes: Real-time acquisition of output current and voltage waveforms of mobile power supply within a continuous time unit, extraction of periodic decay characteristics of waveform oscillation frequency and instantaneous response hysteresis characteristics during load changes; A power compensation function is established based on the correlation between attenuation and hysteresis characteristics. This function takes load change events as the trigger condition, historical fluctuation attenuation rate as the correction factor, and the compensation amount increases exponentially with the increase of the difference in attenuation rate between adjacent time units. The probability of load mutation in subsequent time units is predicted by using the compensation function. When a phase shift is detected between the current waveform oscillation frequency and the historical attenuation trajectory, dual adjustment parameters containing amplitude compensation and phase calibration direction are generated. The switching device turn-on timing is adjusted in real time based on dual parameters, and compensation is injected before load changes and high-frequency oscillation energy accumulation is eliminated through reverse phase calibration. After adjustment, the actual output waveform is compared with the expected trajectory of the compensation function. If it deviates from the threshold, the attenuation rate weight coefficient is automatically corrected.

[0007] Specifically, the method for extracting periodic decay characteristics is as follows: frequency domain analysis is performed on the voltage or current waveform in each time unit to identify the main oscillation frequency component, the amplitude change of this component in continuous time units is tracked and its envelope is calculated, and the decay constant is obtained by fitting the envelope with an exponential function. This decay constant characterizes the periodic decay characteristics.

[0008] Specifically, the method for extracting the instantaneous response hysteresis feature is as follows: when the absolute value of the rate of change of current between adjacent sampling points exceeds a preset threshold, a load change event is determined. The instantaneous voltage value at the moment of the change and the steady-state voltage reference value before the change are recorded. The deviation between the two is calculated and the time required for the deviation to decay to a preset ratio is recorded. This time value is defined as the instantaneous response hysteresis feature.

[0009] Specifically, the construction logic of the power compensation function is as follows: based on the negative correlation between the lag characteristic value and the attenuation characteristic value of the adjacent previous time unit in the historical data, the function expression is set to the compensation amount equal to the benchmark compensation coefficient multiplied by the exponential function, and its exponential term includes the adaptive gain coefficient derived from the historical fluctuation attenuation rate. This gain coefficient is dynamically adjusted upward as the standard deviation of the historical attenuation characteristic value increases.

[0010] Specifically, the generation mechanism of the dual adjustment parameters is as follows: based on the potential disturbance intensity index output by the compensation function, combined with the phase offset and direction of the current oscillation frequency and the expected decay trajectory, the amplitude compensation amount is calculated to adjust the output voltage reference; at the same time, the phase calibration direction is determined according to the phase offset direction, and the calibration intensity is determined according to the offset magnitude. The two together constitute the dual adjustment parameters.

[0011] Specifically, the operation of adjusting the turn-on timing of the switching devices is as follows: the amplitude compensation amount is converted into the reference offset of the voltage error amplifier to adjust the duty cycle; the phase calibration parameter is converted into a precise time adjustment amount for the transmission time of the drive signal, so that the turn-on or turn-off action of the switching devices is advanced or delayed by a specified time, so as to realize the injection of compensation amount before the load change and the phase cancellation of high frequency oscillation.

[0012] Specifically, the process of automatically backtracking and correcting the attenuation rate weight coefficient is as follows: at the end of each time unit, the actual attenuation characteristic value is extracted, and the absolute deviation between it and the expected value of the compensation function is calculated; when the deviation exceeds the preset threshold, the most recent weight coefficient update point is located and the trend of subsequent adjustment effect is analyzed, and the weight coefficient is adjusted in reverse using the gradient descent method.

[0013] Specifically, a digital signal processor is used as the core control unit, including: preprocessing the sampled waveform through a finite-length unit impulse response filter, performing fast Fourier transform and exponential envelope fitting to extract attenuation features; constructing a software algorithm compensation function containing an exponentially increasing relationship; monitoring phase shift through a digital comparator and generating dual adjustment parameters; and controlling the pulse width modulation controller to dynamically adjust the switching timing.

[0014] Specifically, a field-programmable gate array (FPGA) is used as the core logic unit, including: real-time calculation of the oscillation frequency through a sliding window zero-crossing detection hardware circuit; implementation of the exponential response characteristics of the compensation function using a lookup table structure, with the table contents dynamically updated according to the historical fluctuation decay rate; comparison of the zero-crossing time difference between the real-time waveform and the ideal waveform of the numerically controlled oscillator using a digital phase detector; and direct adjustment of the initial value of the pulse width modulation counter to achieve nanosecond-level phase calibration.

[0015] Specifically, it is implemented using a custom mixed-signal application-specific integrated circuit, including: outputting the attenuation characteristic voltage through an on-chip analog envelope detector; measuring the response lag time using a time-to-digital converter module; realizing the exponential characteristic of the compensation function by combining digital calculation with analog transconductance units; injecting compensation current into the error amplifier through a digital-to-analog converter, while controlling the programmable delay line to adjust the timing of the drive signal.

[0016] The beneficial effects of this invention are as follows: 1. Based on the correlation between attenuation characteristics and hysteresis characteristics, a power compensation function is established with load change events as the trigger condition and historical fluctuation attenuation rate as the correction factor. This makes the output value of the compensation function increase exponentially as the difference in attenuation rate in adjacent time units increases, thereby improving the compensation strength.

[0017] 2. By using the compensation function to predict the probability of load change, and when the phase shift between the waveform oscillation frequency and the historical attenuation trajectory is detected, dual adjustment parameters including amplitude compensation and phase calibration direction are generated to provide a precise basis for power output adjustment.

[0018] 3. Adjust the switching device turn-on timing in real time based on dual adjustment parameters, complete the compensation injection before load sudden change, and eliminate the accumulation of high-frequency oscillation energy through reverse phase calibration to ensure stable power output.

[0019] 4. After completing the adjustment of each time unit, compare the actual output waveform with the expected trajectory of the compensation function. If the deviation exceeds the threshold, automatically backtrack and correct the attenuation rate weight coefficient of the power compensation function to ensure continuous optimization of the adjustment effect.

[0020] 5. By employing different hardware such as high-performance digital signal processors, field-programmable gate arrays, or custom mixed-signal application-specific integrated circuits, and combining their respective advantages, efficient dynamic adjustment of power stability can be achieved in different scenarios. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating the dynamic adjustment method for mobile power stability based on time-series modeling according to the present invention. Detailed Implementation

[0023] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0024] This invention proposes a dynamic adjustment method for mobile power stability based on time-series modeling. The core of this method is to predict potential load change disturbances by performing real-time modeling and analysis of the time-series characteristics of the mobile power output, and to actively inject dynamic compensation before or when the disturbance occurs. This significantly improves the transient response speed and steady-state accuracy of the power output, effectively suppresses problems such as voltage drop, overshoot and high-frequency oscillation, and ensures the stable operation of connected devices.

[0025] like Figure 1 As shown, the method of the present invention mainly includes: Step 1: Real-time acquisition of the output current and voltage waveforms of the power bank within a continuous time unit, and extraction of the periodic decay characteristics of the waveform oscillation frequency and the instantaneous response hysteresis characteristics during load changes within each time unit. Step 2: Based on the correlation between attenuation characteristics and hysteresis characteristics, establish a power compensation function with load change events as the trigger condition and historical fluctuation attenuation rate as the correction factor. The output value of the compensation function increases exponentially with the increase of the difference in attenuation rate in adjacent time units. Step 3: Use the compensation function to predict the probability of load mutation in subsequent time units. When a phase shift is detected between the current waveform oscillation frequency and the historical attenuation trajectory, generate dual adjustment parameters including amplitude compensation amount and phase calibration direction. Step 4: Adjust the switching timing of the switching devices in real time according to the dual adjustment parameters so that the power output waveform completes the compensation injection before the load change, and at the same time eliminates the accumulation of high frequency oscillation energy through reverse phase calibration. Step 5: After completing the adjustment of each time unit, compare the degree of fit between the actual output waveform and the expected trajectory of the compensation function. When the deviation exceeds the preset threshold, automatically backtrack and correct the attenuation rate weighting coefficient of the power compensation function.

[0026] In view of the above-mentioned technology, the present invention provides the following embodiments: Example 1 employs a high-performance digital signal processor (DSP) as the core control unit, combined with a high-precision sampling circuit, a drive circuit, and power switching devices such as metal-oxide-semiconductor (MOSFETs) to form the main implementation. The DC output of the power bank acquires analog signals of the output current and voltage in real time through a current sampling circuit composed of a precision shunt resistor and a differential amplifier, and a voltage sampling circuit composed of a resistor divider network. These analog signals are converted into discrete digital time sequences by a high-speed analog-to-digital converter (ADC), and transmitted to the DSP for real-time processing within a fixed time window, for example, 100 μs per time unit containing 1000 sampling points.

[0027] In step 1, the digital signal processor first preprocesses the digital current and voltage sequences within each time unit, including using a finite-length impulse response filter to eliminate high-frequency noise interference. Subsequently, feature extraction is performed on the preprocessed waveform data.

[0028] The specific method for extracting the periodic decay characteristics is as follows: Perform a Fast Fourier Transform on the voltage or current waveform within the current time unit to identify the main oscillation frequency component; then, track the amplitude variation of this main oscillation frequency component within continuous time units and calculate its envelope; finally, fit the envelope to an exponential function using the least squares method. The decay constant of the resulting fitted function is the periodic decay characteristic value representing the waveform oscillation frequency within that time unit. This value reflects the system's damping characteristics and the rate of energy dissipation.

[0029] The specific method for extracting the instantaneous response hysteresis feature is as follows: A load surge event detection mechanism is set up within the digital signal processor. For example, when the absolute value of the rate of change of current between adjacent sampling points exceeds a preset threshold (e.g., 10 A / μs), a load surge event is determined to have occurred. The precise time point of the surge event is recorded, along with the instantaneous value of the voltage waveform at that moment. The deviation between this instantaneous voltage value and the steady-state voltage reference value before the surge is calculated, and the time required for this deviation to decay to a preset ratio, such as 10%, is recorded. This time value is defined as the instantaneous response hysteresis feature value of this load surge event. This value reflects the system's response speed to sudden load increases or decreases.

[0030] In step 2, the digital signal processor performs correlation analysis between the stored attenuation characteristic values ​​and the corresponding hysteresis characteristic values ​​within the historical time units. Analysis of extensive experimental data reveals a significant negative linear correlation between the hysteresis characteristic value and the attenuation characteristic value of the adjacent previous time unit under specific circuit parameters. Specifically, the faster the oscillation decays in the previous time unit (the larger the attenuation characteristic value), the shorter the response hysteresis time (i.e., the hysteresis characteristic value) during the current load change. Based on this correlation, a power compensation function is constructed with load change events as the trigger condition. The core expression of this function is: Compensation amount = benchmark compensation coefficient × exponential function; The exponential term of an exponential function = ×Adaptive gain coefficient; The historical fluctuation attenuation rate is represented by an adaptive gain coefficient, which is dynamically adjusted based on the standard deviation of the attenuation characteristic values ​​over multiple past time units (e.g., the most recent 10 time units). The larger the standard deviation, the more severe the historical fluctuations, and the larger the adaptive gain coefficient. This makes the sensitivity of the compensation function to the difference in attenuation rates between adjacent time units increase exponentially, thus providing stronger compensation near the system stability boundary.

[0031] In step 3, the digital signal processor (DSP) uses the constructed compensation function to make a prediction. Specifically, at the beginning of each time unit, even if no explicit load change event has been detected, the processor calculates a "potential disturbance intensity" index based on the compensation function. Simultaneously, the processor continuously monitors the waveform oscillation frequency acquired in real-time within the current time unit and compares it with the "expected attenuation trajectory" predicted by extrapolation based on historical attenuation characteristic values. The expected attenuation trajectory is predicted by linear extrapolation or Kalman filtering of the attenuation characteristic values ​​of the most recent three time units. When a phase shift exceeding a preset threshold (e.g., 5 degrees) is detected between the current actual oscillation frequency and the expected trajectory, it is determined that there is a risk of an impending or ongoing power disturbance. At this time, the DSP activates the dual adjustment parameter generation module. This module first calculates the required amplitude compensation amount based on the "potential disturbance intensity" index output by the compensation function, combined with the direction (leading or lagging) and magnitude of the current phase shift. The amplitude compensation amount mainly acts to raise or lower the output voltage reference to offset the expected voltage drop or overshoot. Secondly, based on the specific value and direction of the phase shift, the phase calibration direction and intensity are calculated. The phase calibration direction is designed to counteract detected phase shifts; for example, if the current frequency phase lags behind the expected trajectory, the calibration direction is to advance the switching timing in the forward direction; its strength is proportional to the amount of phase shift. The final output dual regulation parameters include a specific voltage amplitude fine-tuning amount (in mV) and a phase advance or delay amount for the switching timing (in ns).

[0032] In step 4, the dual adjustment parameters generated by the digital signal processor are transmitted to the pulse width modulation controller in real time. Based on the received amplitude compensation, the pulse width modulation controller dynamically adjusts the reference value of its internal voltage error amplifier, thereby changing the setpoint of the output voltage. Simultaneously, based on the received phase calibration direction and intensity, it precisely adjusts the turn-on and turn-off timing of the drive signals sent to the main power circuit switching devices. For example, if a 5ns phase advance is required, the controller will send the turn-on signals of all switching devices in the next cycle five nanoseconds earlier. The key to this timing adjustment is that it needs to inject the compensation into the power output circuit before the predicted load surge actually occurs, or at its very early stage. Amplitude compensation acts directly on the voltage loop, providing energy support or absorption; while phase calibration, by precisely controlling the turn-on timing of the switching devices, changes the equivalent output impedance characteristics or energy transfer phase of the power converter, effectively interrupting the energy accumulation process that may lead to high-frequency oscillations, especially by intentionally creating a small disturbance with a phase opposite to the detected harmful oscillation, thus achieving energy cancellation.

[0033] In step 5, after the adjustment of each time unit is completed, the digital signal processor (DSP) starts the verification program. This program collects the actual output current and voltage waveform data after adjustment for this time unit and calculates the actual attenuation characteristic value using the same feature extraction method as in step 1. Simultaneously, based on the compensation function initially constructed for this time unit and the input parameters, such as the attenuation characteristic difference at that time and the historical fluctuation attenuation rate, the processor calculates the "expected attenuation characteristic value" that the function is expected to reach at the end of this time unit. Then, the absolute deviation between the actual attenuation characteristic value and the expected attenuation characteristic value is calculated. This deviation is compared with a preset stability boundary threshold, for example, a maximum allowable deviation of 15% of the expected value. If the deviation exceeds the threshold, it indicates that the attenuation rate weighting coefficient (i.e., the adaptive gain coefficient) in the currently used power compensation function is not set ideally and fails to accurately reflect the dynamic characteristics or load change patterns of the system. At this time, the system automatically triggers a backtracking correction mechanism. This mechanism first locates the time point of the most recent weight coefficient update, analyzes the adjustment effect of all time units since that point, i.e., the changing trend of the consistency between the actual and expected decay characteristics. Then, it uses gradient descent or the least mean square algorithm to make small-scale reverse adjustments to the weight coefficients. For example, if the actual decay is generally slower than expected, the weight coefficients are appropriately reduced to decrease the compensation intensity, and the corrected weight coefficients are applied to the compensation function calculation of subsequent time units. This closed-loop process ensures that the model can adapt to the aging drift of load characteristics or component parameters, continuously optimizing the adjustment effect.

[0034] Example 2 uses a field-programmable gate array (FPGA) as the core logic processing unit, emphasizing the high-speed advantage of parallel hardware logic processing, making it suitable for applications with extremely high response speed requirements. Current and voltage signal acquisition is also accomplished through a precision sampling circuit and a high-speed analog-to-digital converter (ADC). The converted digital timing data is directly input to the high-speed parallel input / output interface of the FPGA.

[0035] In step 1, a highly parallel digital signal processing pipeline is implemented internally within the field-programmable gate array (FPGA). For the extraction of periodic decay characteristics, a sliding window combined with zero-crossing detection and period counting hardware logic is used. Specifically, a configurable-width sliding window is designed to calculate the number of zero-crossing points of the voltage or current waveform within the window in real time. Combined with a high-precision timer, the current oscillation frequency is directly calculated. Then, a set of parallel exponential envelope fitting units, which use a lookup table method and linear interpolation to achieve approximate exponential operations, performs real-time envelope fitting on the frequency values ​​calculated from multiple consecutive windows, directly outputting the decay characteristic value at the current moment. This process can be updated at each sampling point, and the feature value update rate is much higher than once per time unit in Example 1. The extraction of instantaneous response hysteresis characteristics is implemented through a hardware comparator and a timer chain. Load mutations are monitored in real time by the hardware circuitry using the current differential signal. When the differential value exceeds a preset threshold, a hardware interrupt signal is immediately triggered. This signal simultaneously latches the current voltage value and starts a high-precision digital timer. The state machine inside the field-programmable gate array monitors the voltage recovery process. When the digital comparator detects that the voltage value has recovered to 90% of the steady-state value before the sudden change, the timer is stopped. This time value is the hysteresis characteristic value.

[0036] In step 2, the Field-Programmable Gate Array (FPGA) utilizes its abundant internal storage cells to construct a lookup table structure to approximate the compensation function. The address lines of this lookup table consist of two key inputs: the currently detected load mutation event flag, which serves as the highest-order address, and the quantized absolute value of the difference between the decay characteristic values ​​of adjacent time units (which can be defined more precisely, such as 10 μs). The content of the lookup table, i.e., the output value, is dynamically updated based on the historical fluctuation decay rate. The historical fluctuation decay rate is calculated by a dedicated statistical module within the FPGA. This module continuously calculates the moving average and variance of the decay characteristic values ​​over the most recent historical period, quantizing the variance value as an index dimension of the lookup table, or as the basis for content updates. The content of the lookup table is designed so that its output value increases exponentially with the increase of the "decay rate difference" address segment in the address lines, achieved by filling a pre-calculated exponential value table.

[0037] In step 3, the field-programmable gate array (FPGA) utilizes its parallel processing capabilities to run multiple prediction channels simultaneously. The compensation function (represented by a lookup table output) directly provides a quantified "disturbance risk level." Phase offset detection is achieved through a dedicated digital phase detector, which continuously compares the zero-crossing point of the real-time oscillation waveform with the zero-crossing point of an "ideal" oscillation waveform predicted from historical attenuation features. This ideal waveform is generated by a numerically controlled oscillator, whose frequency control word is extrapolated from historical attenuation features. The time difference between the two zero-crossing points is measured in real time and converted into a phase difference. When the phase difference exceeds a preset tolerance and the disturbance risk level exceeds a threshold, the state machine transitions to the parameter generation state. The amplitude compensation amount is directly generated from the current disturbance risk level through a linear mapping relationship. The phase calibration direction is determined by the sign (positive or negative) of the detected phase difference, and the calibration strength is determined by the absolute value of the phase difference and the disturbance risk level, implemented through another small lookup table or hardware multiplier. The generated dual adjustment parameters—amplitude compensation amount, phase direction, and strength—are latched and output.

[0038] In step 4, the field-programmable gate array (FPGA) directly generates the pulse width modulation (PWM) waveform. The amplitude compensation is converted into a direct offset to the duty cycle setting of the internal digital PWM module. Phase calibration is manifested as real-time phase accumulation or subtraction of the PWM carrier counter. For example, if a 1ns advance is detected, the initial value of the counter is subtracted from the value corresponding to that time difference at the beginning of the next carrier cycle, thereby precisely controlling the rising and falling edges of the output drive pulse. This direct hardware-level control ensures extremely low latency in the compensation action, enabling compensation injection to be completed within several switching cycles or even before load abrupt changes. Phase calibration, by finely adjusting the switching timing, actively disrupts the fixed phase relationship between the switching frequency and parasitic parameters that may cause resonance, introducing damping and eliminating the accumulation of high-frequency oscillation energy.

[0039] In step 5, the field-programmable gate array (FPGA) performs micro-verification at the end of each adjustment cycle (which can be synchronized with the switching cycle). The actual effect is quickly assessed by monitoring the waveform stability in the following few switching cycles after adjustment, such as whether the peak-to-peak voltage ripple decreases or whether new oscillations appear. The expected effect is based on the "expected disturbance suppression effect" model at the output of the compensation function, which may be based on the empirical relationship between the compensation amount and the expected effect. If the actual observed ripple or residual oscillation amplitude exceeds the allowable value calculated based on the expected model, a backtracking correction is triggered. The correction process is controlled by a state machine. Based on the statistics of recent multiple verification results, if the effect is unsatisfactory three times in a row, the content value corresponding to the current operating point (address) in the lookup table is adjusted according to preset rules, or the historical fluctuation attenuation rate calculation parameters affecting the lookup table content are adjusted, such as the moving average window length. Embodiment 2 of this invention, through the parallelism and high speed of hardware logic, is particularly suitable for high-frequency switching converters, realizing nanosecond-level dynamic response and adjustment.

[0040] Example 3 employs a custom-designed mixed-signal application-specific integrated circuit (ASIC), combining the advantages of fast response speed of analog circuits and flexible control of digital circuits. Current and voltage sampling utilizes an on-chip integrated differential amplifier and analog-to-digital converter.

[0041] In step 1, the extraction of the periodic decay characteristics utilizes on-chip analog circuitry. Specifically, before analog-to-digital conversion, the voltage or current signal passes through an analog envelope detector consisting of a transconductance amplifier and a capacitor. The output of this detector is a DC voltage proportional to the amplitude decay trend of the input signal envelope. This voltage is sampled by a low-speed, high-precision analog-to-digital converter, and its sampled value directly reflects the periodic decay characteristics. The update rate is set to once every time unit, such as 200 μs. The instantaneous response hysteresis characteristics are handled entirely by the digital section. Load mutations are detected by digital logic through rapid comparison of the differences between the current sampled values. The measurement of hysteresis time is similar to that in Example 2, but a nanosecond-level resolution hysteresis time value is obtained using an on-chip high-precision time-to-digital converter module.

[0042] In step 2, the digital processor core, such as a built-in microcontroller core, receives the attenuation characteristic value provided by the analog section and the hysteresis characteristic value measured by the digital section. The processor core runs dedicated firmware to execute correlation analysis algorithms, such as linear regression analysis. The implementation of the compensation function combines digital calculation with analog assistance. The core's exponential increase relationship is calculated digitally. However, the output value of this function, i.e., the compensation amount, is converted into an analog current or voltage signal and injected into the error amplifier input of the main power circuit or directly modulated to the reference voltage. The "exponential increase" characteristic can be achieved through digital calculation or through an analog transconductance unit with exponential transfer characteristics, such as utilizing the characteristics of a bipolar transistor. The digital section mainly controls the bias point or gain of this analog unit to ensure that its equivalent transfer characteristics satisfy the exponential relationship. The historical fluctuation attenuation rate is calculated by the digital processor core and used to dynamically adjust the bias current of the aforementioned analog transconductance unit, thereby changing the steepness of its equivalent exponential curve, i.e., the gain.

[0043] In step 3, the digital processor core uses the compensation function calculation results for prediction. Phase shift detection employs a digital method: the analog signal output from the envelope detector undergoes analog-to-digital conversion at a rate higher than the attenuation feature update rate, followed by digital phase detection, such as multiplier phase detection or zero-crossing detection, comparing the real-time phase with the phase predicted based on historical attenuation features. When a significant shift is detected and the compensation function indicates a high risk, the processor core generates dual adjustment parameters. The amplitude compensation amount is directly reflected as the analog compensation current value to be injected into the error amplifier. The phase calibration direction is converted into a control signal for the phase-shifting circuit inside the switching controller, such as a digital control word that increases or decreases the delay line.

[0044] In step 4, amplitude compensation converts the digitally calculated compensation amount into an analog current via an on-chip integrated digital-to-analog converter, which is then directly injected into the summing node of the voltage error amplifier. This instantly adjusts the output, thereby rapidly changing the threshold of the pulse width modulation comparator and adjusting the duty cycle. Phase calibration is achieved by controlling an on-chip integrated programmable delay line, which is connected in series between the pulse width modulation logic output and the driver stage. The actual timing of the drive signal's emission is dynamically adjusted according to the phase calibration parameters. The injection of analog compensation provides near-instantaneous amplitude adjustment, while the digitally controlled delay line provides precise timing control. The combination of these two ensures that compensation can be injected before or at the moment of a load change. Phase calibration precisely controls the minute offset of the switching timing, interfering with potential high-frequency oscillation loops and eliminating energy accumulation by introducing destructive interference.

[0045] In step 5, verification is primarily performed in the digital domain. At the end of each adjustment time unit, the processor core reads the final attenuation characteristic value (provided by the analog section) output by the envelope detector and compares it with the expected attenuation characteristic value predicted at the beginning of the unit based on the compensation function and input parameters. If the actual value deviates from the expected value by more than a threshold, a backtracking correction is triggered. The correction algorithm is implemented in the firmware and may involve adjusting the weighting coefficients used when digitally calculating the compensation function or adjusting the bias parameters controlling the gain of the analog exponential unit. The correction result updates the relevant registers or digital-to-analog converter settings, affecting the compensation behavior of subsequent time units. Example 3 achieves a balance between high performance and low power consumption by utilizing the speed of analog circuits in the critical path and the flexibility of digital circuits in the complex control and adaptive sections through mixed-signal design.

[0046] The beneficial effects of this invention are as follows: 1. By constructing a power compensation function triggered by load change events and combining it with the historical fluctuation attenuation rate as a correction factor, the compensation strength is significantly enhanced as the attenuation rate difference changes, thereby improving the system's transient response speed and effectively suppressing voltage fluctuation problems.

[0047] 2. By using a compensation function to predict the risk of load change, when a phase shift is detected between the waveform oscillation frequency and the historical trajectory, dual adjustment parameters of amplitude compensation and phase calibration direction are generated to achieve precise control of power output and reduce voltage deviation and oscillation amplitude.

[0048] 3. The switching device turn-on timing is adjusted in real time based on dual adjustment parameters, the compensation injection is completed in advance, and the high-frequency oscillation energy accumulation is eliminated through reverse phase calibration, so as to ensure that the power output waveform remains highly stable during load change.

[0049] 4. After the adjustment of each time unit is completed, the actual output waveform is compared with the expected trajectory of the compensation function. If the degree of agreement exceeds the preset limit, the attenuation rate weight coefficient is automatically corrected to enable the system to adapt to load changes and maintain long-term adjustment effect optimization.

[0050] 5. Employing diverse hardware platforms such as high-performance digital signal processors, field-programmable gate arrays, or custom mixed-signal application-specific integrated circuits, and combining their respective processing advantages, it efficiently adapts to different application scenarios, improving the overall reliability and efficiency of dynamic power stability adjustment.

[0051] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for dynamic adjustment of mobile power stability based on time-series modeling, characterized in that, include: Real-time acquisition of output current and voltage waveforms of mobile power supply within a continuous time unit, extraction of periodic decay characteristics of waveform oscillation frequency and instantaneous response hysteresis characteristics during load changes; A power compensation function is established based on the correlation between attenuation and hysteresis characteristics. This function takes load change events as the trigger condition, historical fluctuation attenuation rate as the correction factor, and the compensation amount increases exponentially with the increase of the difference in attenuation rate between adjacent time units. The probability of load mutation in subsequent time units is predicted by using the compensation function. When a phase shift is detected between the current waveform oscillation frequency and the historical attenuation trajectory, dual adjustment parameters containing amplitude compensation and phase calibration direction are generated. The switching device turn-on timing is adjusted in real time based on dual parameters, and compensation is injected before load changes and high-frequency oscillation energy accumulation is eliminated through reverse phase calibration; After adjustment, the actual output waveform is compared with the expected trajectory of the compensation function. If it deviates from the threshold, the attenuation rate weight coefficient is automatically corrected.

2. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The specific method for extracting periodic decay characteristics is as follows: perform frequency domain analysis on the voltage or current waveform in each time unit to identify the main oscillation frequency component, track the amplitude change of this component in continuous time units and calculate its envelope, and obtain the decay constant by fitting the envelope with an exponential function. This decay constant characterizes the periodic decay characteristics.

3. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The specific method for extracting the instantaneous response hysteresis feature is as follows: when the absolute value of the current change rate between adjacent sampling points exceeds a preset threshold, a load change event is determined. The instantaneous voltage value at the moment of the change and the steady-state voltage reference value before the change are recorded. The deviation between the two is calculated and the time required for the deviation to decay to a preset ratio is recorded. This time value is defined as the instantaneous response hysteresis feature.

4. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The construction logic of the power compensation function is as follows: based on the negative correlation between the lag characteristic value and the attenuation characteristic value of the adjacent previous time unit in the historical data, the function expression is set to the compensation amount equal to the benchmark compensation coefficient multiplied by the exponential function, and the exponential term includes the adaptive gain coefficient derived from the historical fluctuation attenuation rate. This gain coefficient is dynamically adjusted upward as the standard deviation of the historical attenuation characteristic value increases.

5. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The dual adjustment parameter generation mechanism is as follows: based on the potential disturbance intensity index output by the compensation function, combined with the phase offset and direction of the current oscillation frequency and the expected decay trajectory, the amplitude compensation amount is calculated to adjust the output voltage reference; at the same time, the phase calibration direction is determined according to the phase offset direction, and the calibration intensity is determined according to the offset magnitude. The two together constitute the dual adjustment parameter.

6. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The specific operation of adjusting the turn-on timing of the switching devices is as follows: convert the amplitude compensation amount into the reference offset of the voltage error amplifier to adjust the duty cycle; convert the phase calibration parameter into a precise time adjustment amount for the transmission time of the drive signal, so that the turn-on or turn-off action of the switching devices is advanced or delayed by a specified time, so as to realize the injection of compensation amount before the load change and the phase cancellation of high frequency oscillation.

7. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The process of automatically backtracking and correcting the attenuation rate weighting coefficient is as follows: at the end of each time unit, the actual attenuation characteristic value is extracted, and the absolute deviation between it and the expected value of the compensation function is calculated. When the deviation exceeds the preset threshold, locate the most recent weight coefficient update point and analyze the trend of subsequent adjustment effects, and use the gradient descent method to adjust the weight coefficient in reverse.

8. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, A digital signal processor is used as the core control unit, including: preprocessing the sampled waveform through a finite-length unit impulse response filter, performing fast Fourier transform and exponential envelope fitting to extract attenuation features; constructing a software algorithm compensation function containing an exponentially increasing relationship; monitoring phase shift through a digital comparator and generating dual adjustment parameters; and controlling the pulse width modulation controller to dynamically adjust the switching timing.

9. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, The core logic unit is a field-programmable gate array (FPGA), which includes: real-time calculation of the oscillation frequency through a sliding window zero-crossing detection hardware circuit; implementation of the exponential response characteristics of the compensation function using a lookup table structure, with the table contents dynamically updated according to the historical fluctuation decay rate; comparison of the zero-crossing time difference between the real-time waveform and the ideal waveform of the numerically controlled oscillator using a digital phase detector; and direct adjustment of the initial value of the pulse width modulation counter to achieve nanosecond-level phase calibration.

10. The method for dynamic adjustment of mobile power stability based on time-series modeling as described in claim 1, characterized in that, It is implemented using a custom mixed-signal application-specific integrated circuit, including: outputting the attenuation characteristic voltage through an on-chip analog envelope detector; measuring the response lag time using a time-to-digital converter module; realizing the exponential characteristic of the compensation function by combining digital calculation with analog transconductance units; injecting compensation current into the error amplifier through a digital-to-analog converter, while controlling the programmable delay line to adjust the timing of the drive signal.

Images