A method for reducing bus commands by an improved cache
By optimizing bus arbitration in the SOC system through improved cache and command merging modules, the problem of insufficient bandwidth contention on the Axi-Lite bus under full load was solved, thereby improving bus efficiency and optimizing bandwidth, and reducing device costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-09
- Publication Date
- 2026-05-29
AI Technical Summary
In a SoC system, the axi-lite bus has insufficient bandwidth acquisition capability under full load, resulting in low bus efficiency and difficulty in meeting the requirements for efficient data transmission.
By improving the cache to reduce bus commands, configuring bit width parameters, cache size parameters, and address offset parameters, merging Axi-Lite bus requests to generate Axi-Full bus requests, and optimizing bus arbitration using the improved cache and command merging module, the number of bus commands and bandwidth consumption are reduced.
It improves the bus's bandwidth acquisition capability under full load scenarios, enhances the operating efficiency of the SOC system, reduces bus load and redundant data transmission, and reduces device cost and logic complexity.
Smart Images
Figure CN122111914A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of bus interface conversion and cache control technology in SOC systems, specifically involving AXI series bus command optimization technology based on improved cache. Background Technology
[0002] In a System-on-a-Chip (SoC), various AXI interfaces connect to the storage medium via arbitration mechanisms, making bandwidth a critical resource. Bus efficiency and bandwidth contention capabilities directly impact overall device performance. Bus arbitration allocates data channels by recognizing commands. This mechanism means that buses with shorter command lengths have a significantly lower bandwidth contention capability under full load compared to buses with longer command lengths.
[0003] Unbuffered devices mostly use Axi-Lite as their bus interface, and multiple such devices are connected to the Axi-Full bus after arbitration. Since the command length of Axi-Lite is fixed at 1, its data transmission efficiency will decrease significantly when the bus is busy, making it difficult to effectively compete for bandwidth resources and failing to meet the system's requirements for efficient data transmission.
[0004] Some devices, such as deformity correction devices, require smaller data units to improve data hit rate and reduce redundant data transmission, resulting in shorter bus command lengths. These devices also face insufficient bandwidth acquisition capabilities under full load, limiting their performance in complex systems and impacting the overall operating efficiency of the SOC system. Summary of the Invention
[0005] The purpose of this invention is to provide a method for reducing bus commands through an improved cache, which is used in multi-AXI device SOC systems to solve the problems of insufficient bandwidth contention and low bus efficiency when the bus with short command lengths, such as axi-lite, is fully loaded, thereby reducing bus commands and bandwidth consumption and improving bus operating efficiency.
[0006] To achieve the above objectives, the present invention provides the following technical solution:
[0007] A method for reducing bus commands through an improved cache includes the following steps:
[0008] Configure the bit width parameters, cache size parameters, and address offset parameters of the internal and external buses;
[0009] Receive the access command from the axi-lite bus, process the access command using the bit width parameter and address offset related parameters, and obtain addr_offset;
[0010] Input the addr_offset into the improved cache, and query the hit status and corresponding flag status of the improved cache. The flags include cmd_flag, save_flag, and bus_flag.
[0011] Based on the hit status and flag status, the valid requests in the improved cache are merged by the command merging module to generate an access request for the AXI-full bus, which includes the request address and the request length.
[0012] The access request for the axi-full bus is sent to the external storage medium, the data returned by the external storage medium is received, the data is stored in the corresponding position of the improved cache according to the request address, and the flag bit status is updated.
[0013] The effective data module extracts the valid data corresponding to the addr_offset from the improved cache and returns the valid data to the axi-lite bus, thereby reducing the number of bus commands.
[0014] In one possible implementation, the steps for configuring the bit width parameter, cache size parameter, and address offset related parameters include:
[0015] Set the data width of the axi-lite bus to LITE_DW, and the corresponding bit width identifier is LITE_DM, where LITE_DM is log2(LITE_DW);
[0016] Set the data width of the improved cache to FULL_DW, the corresponding bit width identifier to FULL_DM, FULL_DM is log2(FULL_DW), and FULL_DW is not less than LITE_DW;
[0017] Set the address offset bit width OFST_AW to the difference between FULL_DM and LITE_DM, and configure the device cache size to the range of values corresponding to BUF_AW, in units of the data bit width of the axi-lite bus.
[0018] In one possible implementation, the step of processing the access command to obtain the addr_offset includes:
[0019] Calculate the difference between the address in the access command and the device base address to obtain addr_src;
[0020] Extract the bits of the preset interval in addr_src as addr_offset, where the preset interval is determined by the values of BUF_AW and LITE_DM;
[0021] The addr_offset is decomposed into addr_req, way_index, and offset, where offset is the location identifier of the data in the improved cache, way_index is the location identifier of the data in the cache line, and addr_req is the cache matching update information.
[0022] In one possible implementation, the steps of querying the hit status and corresponding flag status of the improved cache include:
[0023] The improved cache is queried using addr_req and way_index to determine whether the target cacheline is hit.
[0024] If a hit is found and the save_flag of the target cache line is 1, then the valid data extraction step is triggered directly.
[0025] If a hit is found and the bus_flag of the target cache line is 1, then update the request count req_cnt, adjust the LRU priority, and wait for save_flag to be set to 1.
[0026] If a cache hit occurs and the target cache line's cmd_flag is 0, then set the cmd_flag, update req_cnt and LRU priority, and wait for save_flag to be set to 1.
[0027] If a cache miss occurs, wait for an available cache line. If an empty cache line is selected, update addr_info, set cmd_flag, clear save_flag, and update req_cnt and LRU priority.
[0028] In one possible implementation, the step of adjusting the LRU priority includes:
[0029] Set the LRU_code of the cache line that was hit to the total number of cache lines, set_num.
[0030] For other cache lines that are not cached and whose LRU_code is greater than or equal to the LRU_code of the cache line that is cached, decrement their LRU_code by 1.
[0031] The improved cache prioritizes command transmission according to the LRU mechanism, with cache lines whose LRU_code is 0 and cmd_flag is not 0 receiving external bus commands first.
[0032] In one possible implementation, the step of merging valid requests to generate an access request for the axi-full bus includes:
[0033] Iterate through the cmd_flag of the target cache line, and determine the minimum and maximum way_index where cmd_flag is 1, denoted as min and max respectively.
[0034] Shift the addr_info of the target cache line to the left by FULL_DM bits to obtain the request address of the axi-full bus;
[0035] Calculate the difference between the max and min values to obtain the request length of the axi-full bus;
[0036] Determine whether the request length meets the preset minimum length, or whether the LRU_code of the target cache line is 0, or whether there is an external triggering requirement. If any of these conditions are met, an access request for the axi-full bus is generated.
[0037] In one possible implementation, the steps of storing data and updating the flag state include:
[0038] The set_index of the target cache line is used as the request ID of the AXI-full bus to identify the cache line location of the data storage.
[0039] Receive data returned from external storage medium, initialize data count cnt to 0, and determine the data storage start position min based on the least significant bit of bus_flag;
[0040] Each time data is received, the save_flag is set, the corresponding bus_flag is cleared, cnt is incremented by 1, and the data is stored in the improved cache at the position min+cnt.
[0041] When the last data signal (last) from the external bus is received, the cnt value is cleared, and data storage is completed.
[0042] In one possible implementation, the step of extracting the valid data includes:
[0043] When the save_flag of the improved cache is 1, the offset in addr_offset is used to determine the bit range of the data required by the internal bus.
[0044] Extract the valid data within the bit range, which is from offset×LITE_DW to (offset+1)×LITE_DW-1, and return the valid data to the axi-lite bus.
[0045] In one possible implementation, the step of determining the free cache line includes:
[0046] The bus_flag status of the cache line is checked. If the bus_flag is 0, the cache line is determined to be in an idle state.
[0047] Only when a free cache line exists, a missed access request is received, and the relevant information of the free cache line is updated.
[0048] In one possible implementation, after generating the access request for the axi-full bus, the following steps are also included:
[0049] Clear the cmd_flag of the target cache line and set the corresponding bus_flag to indicate that valid data is being transmitted on the external bus.
[0050] The effective range of bus_flag is consistent with the range of way_index from min to max in cmd_flag, ensuring the continuity of data transmission.
[0051] Compared with the prior art, the advantages of this invention are as follows:
[0052] This invention utilizes the interaction between an improved cache and a command merging module, its principle originating from AXI bus arbitration. This arbitration determines command priority based on a specific algorithm, and then determines data order according to command order. Increasing command length and decreasing the number of commands effectively reduces the number of arbitrations, thereby enhancing bandwidth preemption capabilities under the same priority algorithm rules and significantly reducing the number of bus commands and bandwidth consumption. The improved cache can store consecutive requests from the internal bus; when a subsequent request hits the cache, there is no need to initiate a duplicate request to the external bus, and data is directly retrieved from the cache. The command merging module merges multiple low-width internal requests into a high-width external request, significantly reducing the number of commands required for a single data transmission. Compared to the existing technology's frequent request initiation mode of short-command buses, this significantly reduces redundant data in bus transmission and alleviates bus load.
[0053] Increasing command length directly improves the bus's bandwidth contention capability under full load scenarios. Existing Axi-Lite devices offer advantages such as simple logical structure and no need for large-area storage, but their bandwidth contention capability is weak when sharing the Axi bus with other Axi-Full devices. They struggle to compete for bandwidth with long-command buses during bus arbitration, leading to efficiency degradation. This invention merges short commands into long commands, making bus requests more aligned with the arbitration mechanism's preference for command length. Simultaneously, LRU priority scheduling ensures efficient utilization of cache resources, allowing devices to fully utilize the fixed burst resources of external storage such as DDR even when the bus is busy, improving storage utilization, stably competing for bandwidth resources, and ultimately enhancing the overall operating efficiency of the SOC system.
[0054] The improved cache's flag design and data storage optimization further reduce device cost and logical complexity. Flags such as cmd_flag, bus_flag, and save_flag accurately identify request status and data location, avoiding invalid logical judgments and data storage. Sending set_index as the command ID to the bus reduces the need for transmitting and storing additional identification information. Therefore, while reducing commands and optimizing bandwidth, it eliminates the need for significantly increased storage media, balancing performance improvement and cost control, making it suitable for various device scenarios relying on short-command buses. Attached Figure Description
[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0056] Figure 1 This is an overall architecture diagram of the bus conversion scenario according to an embodiment of the present invention;
[0057] Figure 2 This is a schematic diagram of the internal modules and bus connections of the device according to an embodiment of the present invention;
[0058] Figure 3 This is a schematic diagram of the improved cache workflow according to an embodiment of the present invention;
[0059] Figure 4 This is a schematic diagram of address offset decomposition and cache structure according to an embodiment of the present invention;
[0060] Figure 5 This is a schematic diagram illustrating the correspondence between cmd_flag and bus_flag and the data counting in an embodiment of the present invention;
[0061] Figure 6 Embodiments of the present invention Figure 5 This is a flowchart illustrating an embodiment of the present invention. Detailed Implementation
[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0063] Example:
[0064] It should be noted that the terms "comprising" and "having" and any variations thereof in the embodiments of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products, or devices.
[0065] An embodiment of the present invention provides a method for reducing bus commands through an improved cache, characterized by comprising the following steps:
[0066] Step 1: Configure the bit width parameters, cache size parameters, and address offset parameters of the internal bus and external bus.
[0067] Specifically, the bit width parameter can be the data width of the internal bus and the external bus; the cache size parameter can be the numerical range of the device cache; and the address offset related parameter can be the address offset bit width.
[0068] The steps for configuring the bit width parameter, cache size parameter, and address offset related parameters include:
[0069] Set the data width of the axi-lite bus to LITE_DW, and the corresponding bit width identifier is LITE_DM, where LITE_DM is log2(LITE_DW);
[0070] Set the data width of the improved cache to FULL_DW, the corresponding bit width identifier to FULL_DM, FULL_DM is log2(FULL_DW), and FULL_DW is not less than LITE_DW;
[0071] Set the address offset bit width OFST_AW to the difference between FULL_DM and LITE_DM, and configure the device cache size to the range of values corresponding to BUF_AW, in units of the data bit width of the axi-lite bus.
[0072] Specifically, LITE_DW can be the width of a single data transfer on the axi-lite bus; LITE_DM can be the bit identifier corresponding to LITE_DW; FULL_DW can be the width of a single data storage on the improved cache; FULL_DM can be the bit identifier corresponding to FULL_DW; OFST_AW can be the bit width of the address offset; BUF_AW can be the bit identifier of the device cache size.
[0073] Step 2: Receive the access command from the axi-lite bus, process the access command using the bit width parameter and address offset related parameters, and obtain addr_offset.
[0074] Specifically, addr_offset can be the address offset information obtained after processing the access command; for a single device, its access range is much smaller than the bus range, and calculating addr_offset can reduce the number of flag bits, thereby reducing the cost of this device.
[0075] The step of processing the access command to obtain the addr_offset includes:
[0076] Calculate the difference between the address in the access command and the device base address to obtain addr_src, in bytes;
[0077] Extract the bits of the preset interval in addr_src as addr_offset, where the preset interval is determined by the values of BUF_AW and LITE_DM;
[0078] The addr_offset is decomposed into addr_req, way_index, and offset, where offset is the location identifier of the data in the improved cache, way_index is the location identifier of the data in the cache line, and addr_req is the cache matching update information.
[0079] Specifically, the address in the access command can be the read / write address initiated by the axi-lite bus; the device base address can be the starting address of the device in the system; addr_src can be the address difference; the preset range can be the bits from BUF_AW+LITE_DM-1 to LITE_DM in addr_src; addr_offset can be the extracted address offset; addr_req can be the cache matching update information; way_index can be the position identifier in the cache line; and offset can be the position identifier in the cache.
[0080] Step 3: Input the addr_offset into the improved cache, and query the hit status and corresponding flag status of the improved cache. The flags include cmd_flag, save_flag, and bus_flag.
[0081] Specifically, the improved cache can be a cache structure with multiple flags and an LRU mechanism; cmd_flag can be a flag to identify internal requests, with 1 indicating a request and 0 indicating no request; save_flag can be a flag to indicate that cached data is valid, with 1 indicating valid and 0 indicating invalid; bus_flag can be a flag to indicate that data is being transmitted on the external bus, with 1 indicating transmission and 0 indicating no transmission.
[0082] The steps for querying the hit status and corresponding flag status of the improved cache include:
[0083] The improved cache is queried using addr_req and way_index to determine whether the target cacheline is hit.
[0084] If a hit is found and the save_flag of the target cache line is 1, then the valid data extraction step is triggered directly.
[0085] If a hit is found and the bus_flag of the target cache line is 1, then update the request count req_cnt, adjust the LRU priority, and wait for save_flag to be set to 1.
[0086] If a cache hit occurs and the target cache line's cmd_flag is 0, then set the cmd_flag, update req_cnt and LRU priority, and wait for save_flag to be set to 1.
[0087] If a cache miss occurs, wait for an available cache line. If an empty cache line is selected, update addr_info, set cmd_flag, clear save_flag, and update req_cnt and LRU priority.
[0088] Specifically, the target cache line can be a cache storage unit that matches addr_req; req_cnt can be the count of incomplete requests for the current cache line; LRU priority can be the access priority identifier of the cache line; free cache line can be a cache line with bus_flag set to 0; and addr_info can be the address information of the cache line.
[0089] Furthermore, the step of adjusting the LRU priority includes:
[0090] Set the LRU_code of the cache line that was hit to the total number of cache lines, set_num.
[0091] For other cache lines whose LRU_code is greater than or equal to the LRU_code of the cache line that was hit, decrement their LRU_code by 1.
[0092] The improved cache prioritizes command transmission according to the LRU mechanism, with cache lines whose LRU_code is 0 and cmd_flag is not 0 receiving external bus commands first.
[0093] Specifically, set_num can be the total number of cache lines in the improved cache; LRU_code can be a value that identifies the LRU priority; and command sending priority can be the order in which cache lines initiate external bus requests.
[0094] Further, the step of determining the free cache line includes:
[0095] The bus_flag status of the cache line is checked. If the bus_flag is 0, the cache line is determined to be in an idle state.
[0096] Only when a free cache line exists, a missed access request is received, and the relevant information of the free cache line is updated.
[0097] Specifically, a bus_flag value of 0 can indicate that the cache line has no data being transmitted on the external bus; an idle state can indicate that the cache line is ready to receive new requests; related information can include addr_info, cmd_flag, etc.
[0098] Step 4: Based on the hit status and flag status, merge the valid requests in the improved cache through the command merging module to generate an access request for the axi-full bus. The access request includes the request address and the request length.
[0099] The step of merging valid requests to generate the access request for the axi-full bus includes:
[0100] Iterate through the cmd_flag of the target cache line, and determine the minimum and maximum way_index where cmd_flag is 1, denoted as min and max respectively.
[0101] Shift the addr_info of the target cache line to the left by FULL_DM bits to obtain the request address of the axi-full bus;
[0102] Calculate the difference between the max and min values to obtain the request length of the axi-full bus;
[0103] Determine whether the request length meets the preset minimum length, or whether the LRU_code of the target cache line is 0, or whether there is an external triggering requirement. If any of these conditions are met, an access request for the axi-full bus is generated.
[0104] Specifically, the preset minimum length can be the minimum length of an axi-full bus request; external triggering requirements can be situations such as the external buffer reaching a preset depth or external input being completed.
[0105] Furthermore, the steps of storing data and updating the flag state include:
[0106] The set_index of the target cache line is used as the request ID of the AXI-full bus to identify the cache line location of the data storage.
[0107] Receive data returned from external storage medium, initialize data count cnt to 0, and determine the data storage start position min based on the least significant bit of bus_flag;
[0108] Each time data is received, the save_flag is set, the corresponding bus_flag is cleared, cnt is incremented by 1, and the data is stored in the improved cache at the position min+cnt.
[0109] When the last data signal (last) from the external bus is received, the cnt value is cleared, and data storage is completed.
[0110] Specifically, set_index can be the index of the cache line; request ID can be the number that identifies the data's ownership; cnt can be the count of data received in one transaction; min can be the starting way_index of data storage; and the last signal can be the signal from the external bus that indicates the end of data transmission.
[0111] Furthermore, after generating the access request for the axi-full bus, the process also includes the following steps:
[0112] Clear the cmd_flag of the target cache line and set the corresponding bus_flag to indicate that valid data is being transmitted on the external bus.
[0113] The effective range of bus_flag is consistent with the range of way_index from min to max in cmd_flag, ensuring the continuity of data transmission.
[0114] Specifically, the effective range can be the range of way_index where bus_flag is set to 1; the continuity of data transmission can be the characteristic that data is transmitted sequentially according to way_index.
[0115] Step 5: Send the access request of the axi-full bus to the external storage medium, receive the data returned by the external storage medium, store the data in the corresponding position of the improved cache according to the request address, and update the save_flag flag status.
[0116] Specifically, the external storage medium can be DDR memory;
[0117] Step 6: Extract the valid data corresponding to the addr_offset from the improved cache through the valid data module, and return the valid data to the axi-lite bus to reduce bus commands.
[0118] The steps for extracting the valid data include:
[0119] When the save_flag of the improved cache is 1, the offset in addr_offset is used to determine the bit range of the data required by the internal bus.
[0120] Extract the valid data within the bit range, which is from offset×LITE_DW to (offset+1)×LITE_DW-1, and return the valid data to the axi-lite bus.
[0121] Specifically, the bit range can be the bit range of the corresponding internal bus data in the cache data; the valid data can be 32-bit business data.
[0122] For example, the following is in conjunction with the appendix Figure 1 To be continued Figure 5 The preferred embodiments of the method for reducing bus commands by means of an improved cache according to the present invention will be described in detail.
[0123] This invention converts the device's Axi-Lite bus into an Axi-Full bus, which is then connected to the storage medium after arbitration. This conversion process achieves both bus protocol adaptation and increases command length by merging bus commands, while reducing duplicate command initiation when the cache is hit. This results in a reduction of the number of bus commands, lower bandwidth consumption, and enhanced bandwidth acquisition capabilities of the device.
[0124] The device of the present invention mainly consists of a data processing module 201, an improved cache 202, a command merging module 203, and a valid data module 204. The data processing module 201 first processes the received axi-lite command into a more logically concise addr_offset, then obtains the valid data through the improved cache 202, and finally returns the valid data to the axi-lite bus.
[0125] The data processing module 201 processes addr_offset as follows: The data width of the axi-lite bus is set to LITE_DW, and the value corresponding to log2(LITE_DW) is LITE_DM. This LITE_DM corresponds to the attached... Figure 4 The 404 error occurs in the code. The data width of the improved cache202 is used as the data width of the Axi-full bus, set to FULL_DW. The value corresponding to log2(FULL_DW) is FULL_DM, and the data width of the improved cache202 is not less than the data width of the Axi-lite bus. The value of OFST_AW is the difference between FULL_DM and LITE_DM. This OFST_AW corresponds to... Figure 4 403 in the middle.
[0126] The device's buffer size range is set to a value corresponding to a left shift of BUF_AW bits from 0 to 1, in units of the Axi-Lite bus data bit width. This BUF_AW value corresponds to... Figure 4 Error 405 occurs when the address in the device command is compared to the device base address to obtain `addr_src`, in bytes. This `addr_src` corresponds to the attached... Figure 4 The 406 in the value is then extracted. The bit segment from LITE_DM to the sum of BUF_AW and LITE_DM minus 1 in addr_src is then extracted. This bit segment is addr_offset.
[0127] Set the size of the way to the value corresponding to 1 left-shifted by WAY_AW bits. This WAY_AW corresponds to the attached... Figure 4 In step 402, the size of the set is set to the value corresponding to 1 left-shifted by SET_WAY bits. The number of bits in this set is denoted as set_num, and SET_WAY corresponds to the appended... Figure 4In step 401, the length of addr_info recorded in set, INFO_AW, is the result of subtracting WAY_AW, OFST_AW, and LITE_DM from BUF_AW. This INFO_AW also corresponds to the attached... Figure 4 401. The `addr_offset` is decomposed into three parts: `addr_req`, `way_index`, and `offset`. `offset` is the bit segment from bit 0 to bit OFST_AW minus 1 in `addr_offset`, used to identify the position of the device data in the improved cache202, with the device data size as the smallest unit. `way_index` is the bit segment from bit OFST_AW to bit 1 (the sum of WAY_AW and OFST_AW), used to identify the position of the data in the cache line. `addr_req` is the bit segment from bit 1 (the sum of WAY_AW and OFST_AW) to bit 1 (BUF_AW minus 1) in `addr_offset`, used as information for updating `addr_info` after a mismatch.
[0128] The improved cache202 initiates a request via addr_req. When save_flag is 1, the improved cache202 returns data and updates the relevant flags. If the request misses the improved cache202, it needs to wait for an idle cacheline to receive the request. The condition for determining whether a cacheline is idle is that bus_flag equals 0. If the request successfully hits the improved cache202, it directly retrieves the valid data from the corresponding valid cache using the offset in the request and returns it. At the same time, the improved cache202 will determine whether the request is a valid hit. If it is a valid hit, it sends the retrieved valid data to the valid data module 204; if it is a invalid hit, it sends addr_offset to the valid data module 204.
[0129] The command merging module 203 obtains the request information of the current cache line by checking the cmd_flag in the improved cache 202. The specific process is as follows: First, calculate the way_index corresponding to the least significant bit of cmd_flag in the current cache line that is 1, denoted as min. Then, left-shift the addr_info of this cache line by WAY_AW bits to obtain the request address of the cache line. Subsequently, left-shift the request address of this cache line by FULL_DM bits to finally obtain the request address of the Axi-full bus. Next, calculate the way_index corresponding to the most significant bit of cmd_flag in the current cache line that is 1, denoted as max. Subtract min from max to obtain the cache request length, which is the request length of the Axi-full bus.
[0130] First, it checks if the current cache line's LRU_code is 0 and if a request exists. If so, an Axi-full bus request is issued. Then, it checks if the request length exceeds the configured minimum length. If so, an Axi-full bus request is issued. Finally, when there is an external demand, such as when the external buffer reaches a certain depth or all external input is completed, Axi-full bus requests with cache line requests are issued one by one. The current cache's set_index is used as the Axi-full bus request ID. This request ID identifies the storage location of the returned data in the cache line, and the Axi-full bus data size is consistent with the improved cache202 data size.
[0131] The valid data module 204 first checks whether the request has a valid hit on the improved cache 202. If so, it directly retrieves the valid data from the improved cache 202. Otherwise, it checks the status of save_flag by obtaining addr_req from the improved cache 202. When save_flag is 1, it retrieves the valid cache data from the improved cache 202, and then extracts the valid data required by the internal axi-lite bus by obtaining the offset from the improved cache 202, and returns the valid data to the device.
[0132] The improved cache202 workflow is as follows:
[0133] Step 301: First, check if the request hits the target cache line and if the save_flag corresponding to way_index is in a valid state. If so, set the lru_code of the hit cache line to the total number of cache lines set_num, and at the same time, set the lru_code of the hit cache line to be greater than or equal to the lru_code of the hit cache line minus 1. Then proceed to step 310.
[0134] If the result of the check in step 301 is negative, then proceed to step 302 to check whether the request hits the target cache line and whether the bus_flag corresponding to the way_index is in a valid state. If so, set the lru_code of the hit cache line to set_num, and decrement the lru_code of other cache lines whose lru_code is not 0 by 1, and then proceed to step 307.
[0135] If the result of the check in step 302 is negative, then step 303 is executed to check whether the request hits the target cache line and whether cmd_flag is not equal to 0. If so, the cmd_flag corresponding to way_index is set, and the lru_code of the hit cache line is set to set_num. The lru_code of other cache lines with lru_code not equal to 0 is decremented by 1. Then, the process proceeds to step 307.
[0136] If the check result of step 303 is negative, that is, the request did not hit any cache line, then step 304 is executed to wait for an idle cache line.
[0137] After step 304 finds an idle cache line, step 305 is executed to update the relevant information of the selected idle cache line, set the cmd_flag of the cache line, clear the save_flag, increment the request count req_cnt by 1, set the lru_code of the cache line to set_num, and decrement the lru_code of other cache lines whose lru_code is not 0 by 1. In step 304, the condition for determining whether a cache line is idle is that req_cnt equals 0.
[0138] In step 306, when the command merging module 203 issues the axi-full bus command, it clears the corresponding cmd_flag and sets the corresponding bus_flag.
[0139] When executing step 307, after the bus data is input, the least significant bit, `way_index`, corresponding to a high level in `bus_flag` is read and used as `min`, as shown in Figure 501. Then, the bus data count `cnt` is initialized to 0, the bus's `last` signal is cleared, and `cnt` is incremented by 1 after the bus data reception is complete. The offset in the cache line is equal to the sum of `min` and `cnt`, as shown in Figure 502. When the bus data returns, the request ID is shifted left by `OFST_AW` bits and added to the offset to obtain the data's storage location in the improved cache 202. Afterward, the bus data is updated, the corresponding `bus_flag` is cleared, and `save_flag` is set.
[0140] In step 308, based on the addr_req in the request after step 302, the save_flag of the cache waiting to be hit is set to 1.
[0141] In step 309, req_cnt is decremented by 1, and then the data that was hit in the cache is retrieved.
[0142] In step 310, the valid data required by the internal bus is calculated based on the offset in addr_req, and the valid data is returned to the internal bus.
[0143] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0144] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A method for reducing bus commands through an improved cache, characterized in that, Includes the following steps: Configure the bit width parameters, cache size parameters, and address offset parameters of the internal and external buses; Receive the access command from the axi-lite bus, process the access command using the bit width parameter and address offset related parameters, and obtain addr_offset; Input the addr_offset into the improved cache, and query the hit status and corresponding flag status of the improved cache. The flags include cmd_flag, save_flag, and bus_flag. Based on the hit status and flag status, the valid requests in the improved cache are merged by the command merging module to generate an access request for the AXI-full bus, which includes the request address and the request length. The access request for the axi-full bus is sent to the external storage medium, the data returned by the external storage medium is received, the data is stored in the corresponding position of the improved cache according to the request address, and the flag bit status is updated. The effective data module extracts the valid data corresponding to the addr_offset from the improved cache and returns the valid data to the axi-lite bus, thereby reducing the number of bus commands.
2. The method for reducing bus commands through an improved cache according to claim 1, characterized in that, The steps for configuring the bit width parameter, cache size parameter, and address offset related parameters include: Set the data width of the axi-lite bus to LITE_DW, and the corresponding bit width identifier is LITE_DM, where LITE_DM is log2(LITE_DW); Set the data width of the improved cache to FULL_DW, the corresponding bit width identifier to FULL_DM, FULL_DM is log2(FULL_DW), and FULL_DW is not less than LITE_DW; Set the address offset bit width OFST_AW to the difference between FULL_DM and LITE_DM, and configure the device cache size to the range of values corresponding to BUF_AW, in units of the data bit width of the axi-lite bus.
3. The method for reducing bus commands through an improved cache according to claim 2, characterized in that, The steps for processing the access command to obtain the addr_offset include: Calculate the difference between the address in the access command and the device base address to obtain addr_src; Extract the bits of the preset interval in addr_src as addr_offset, where the preset interval is determined by the values of BUF_AW and LITE_DM; The addr_offset is decomposed into addr_req, way_index, and offset, where offset is the location identifier of the data in the improved cache, way_index is the location identifier of the data in the cache line, and addr_req is the cache matching update information.
4. The method for reducing bus commands through an improved cache according to claim 1, characterized in that, The steps for querying the hit status and corresponding flag status of the improved cache include: The improved cache is queried using addr_req and way_index to determine whether the target cacheline is hit. If a hit is found and the save_flag of the target cache line is 1, then the valid data extraction step is triggered directly. If a hit is found and the bus_flag of the target cache line is 1, then update the request count req_cnt, adjust the LRU priority, and wait for save_flag to be set to 1. If a cache hit occurs and the target cache line's cmd_flag is 0, then set the cmd_flag, update req_cnt and LRU priority, and wait for save_flag to be set to 1. If a cache miss occurs, wait for an available cache line. If an empty cache line is selected, update addr_info, set cmd_flag, clear save_flag, and update req_cnt and LRU priority.
5. The method for reducing bus commands through an improved cache according to claim 4, characterized in that, The steps for adjusting the LRU priority include: Set the LRU_code of the cache line that was hit to the total number of cache lines, set_num. For other cache lines whose LRU_code is greater than or equal to the LRU_code of the cache line that was hit, decrement their LRU_code by 1. The improved cache prioritizes command transmission according to the LRU mechanism, with cache lines whose LRU_code is 0 and cmd_flag is not 0 receiving external bus commands first.
6. The method for reducing bus commands through an improved cache according to claim 1, characterized in that, The steps for merging valid requests to generate the access request for the axi-full bus include: Iterate through the cmd_flag of the target cache line, and determine the minimum and maximum way_index where cmd_flag is 1, denoted as min and max respectively. Shift the addr_info of the target cache line to the left by FULL_DM bits to obtain the request address of the axi-full bus; Calculate the difference between the max and min values to obtain the request length of the axi-full bus; Determine whether the request length meets the preset minimum length, or whether the LRU_code of the target cache line is 0, or whether there is an external triggering requirement. If any of these conditions are met, an access request for the axi-full bus is generated.
7. The method for reducing bus commands through an improved cache according to claim 6, characterized in that, The steps for storing data and updating the flag state include: The set_index of the target cache line is used as the request ID of the AXI-full bus to identify the cache line location of the data storage. Receive data returned from external storage medium, initialize data count cnt to 0, and determine the data storage start position min based on the least significant bit of bus_flag; Each time data is received, the save_flag is set, the corresponding bus_flag is cleared, cnt is incremented by 1, and the data is stored in the improved cache at the position min+cnt. When the last data signal (last) from the external bus is received, the cnt value is cleared, and data storage is completed.
8. The method for reducing bus commands through an improved cache according to claim 1, characterized in that, The steps for extracting the valid data include: When the save_flag of the improved cache is 1, the offset in addr_offset is used to determine the bit range of the data required by the internal bus. Extract the valid data within the bit range, which is from offset×LITE_DW to (offset+1)×LITE_DW-1, and return the valid data to the axi-lite bus.
9. The method for reducing bus commands through an improved cache according to claim 4, characterized in that, The steps for determining the free cache line include: The bus_flag status of the cache line is checked. If the bus_flag is 0, the cache line is determined to be in an idle state. Only when a free cache line exists, a missed access request is received, and the relevant information of the free cache line is updated.
10. The method for reducing bus commands through an improved cache according to claim 6, characterized in that, After generating the access request for the axi-full bus, the process further includes the following steps: Clear the cmd_flag of the target cache line and set the corresponding bus_flag to indicate that valid data is being transmitted on the external bus. The effective range of bus_flag is consistent with the range of way_index from min to max in cmd_flag, ensuring the continuity of data transmission.