Circuit board assembly and electronic device

Abstract

The application relates to a circuit board assembly and an electronic device, the circuit board assembly comprising a circuit board, a first electronic component and a second electronic component arranged on the circuit board, the circuit board being provided with a first pad for connecting a first pin, a second pad for connecting a second pin, and a line for connecting the first pad and the second pad; the line comprising a first wire and a second wire, one end of the first wire being connected to the first pad, the other end of the first wire being connected to one end of the second wire, the other end of the second wire being connected to the second pad, the second wire winding around a part of the second pad, and the second wire comprising a first wire segment with a first width and a second wire segment with a second width. The circuit wiring of the application adopts a segmented winding design when accessing the pad, and can solve the problems of impedance mismatch, excessive crosstalk and excessive signal transmission loss of high-speed signal transmission, and improve the transmission quality of high-speed signals.

Description

Circuit board assemblies and electronic devices Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a circuit board assembly and an electronic device. Background Art

[0002] The circuit boards in existing electronic devices (e.g., mobile phones, computers, etc.) typically require high-speed signal transmission. During the PCB routing process, to improve the quality of high-speed signal transmission, it is necessary to consider issues that affect signal transmission quality, such as impedance mismatch and excessive insertion loss.

[0003] Summary of the Invention

[0004] In view of this, it is necessary to provide a circuit board assembly and an electronic device that can solve the problems of impedance mismatch and excessive insertion loss that occur in high-speed signal transmission.

[0005] An embodiment of the present application discloses a circuit board assembly, including a circuit board and a first electronic component and a second electronic component arranged on the circuit board, the first electronic component including a first pin, the second electronic component including a second pin, the circuit board being provided with a first soldering pad for connecting the first pin, a second soldering pad for connecting the second pin, and a circuit for connecting the first soldering pad and the second soldering pad; the circuit including a first trace and a second trace, one end of the first trace being connected to the first soldering pad, the other end of the first trace being connected to one end of the second trace, the other end of the second trace being connected to the second soldering pad, the second trace surrounding a portion of the second soldering pad, and the second trace including a first trace segment having a first width and a second trace segment having a second width.

[0006] In a possible implementation, the second trace surrounds the second pad at an angle of 180°.

[0007] In one possible implementation, the second trace has a surrounding angle of 270° around the second pad.

[0008] In one possible implementation, the second routing includes a first connecting segment, a surrounding segment and a second connecting segment, the surrounding segment is connected between the first connecting segment and the second connecting segment, the first connecting segment is also connected to the first routing, the second connecting segment is also connected to the second pad, and the spacing between the surrounding segment and the second pad is 4 mil.

[0009] In one possible implementation, a ground plane is also provided on the circuit board, and the ground plane is arranged around the second solder pad. The spacing between the surrounding segment and the ground plane is 4 mil, and the spacing between the portion of the second solder pad not surrounded by the surrounding segment and the ground plane is 5 mil.

[0010] In one possible implementation, the first electronic component is a central processing unit (CPU), and the second electronic component is a memory.

[0011] In one possible implementation, the memory is mounted on the circuit board via a dual in-line package (DIP) connector.

[0012] In a possible implementation, the first routing segments and the second routing segments in the second routing are alternately arranged.

[0013] In one possible implementation, the first width is 3.5 mil, and the second width is 4 mil.

[0014] An embodiment of the present application further discloses an electronic device, which includes the above-mentioned circuit board assembly.

[0015] The above-mentioned circuit board components and electronic equipment use a segmented winding design when the wiring is connected to the pads, which can solve the problems of impedance mismatch, excessive crosstalk, and excessive signal transmission loss in high-speed signal transmission, and improve the transmission quality of high-speed signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a wiring diagram of a circuit board assembly according to an embodiment of the present application.

[0017] FIG. 2 a is a schematic diagram of wiring for performing 180-degree L inductance compensation on wiring in a circuit board assembly according to an embodiment of the present application.

[0018] FIG2 b is a schematic diagram of wiring for performing 270-degree L inductance compensation in a circuit board assembly according to an embodiment of the present application.

[0019] FIG. 2 c is a schematic diagram of wiring in a circuit board assembly according to an embodiment of the present application without L inductance compensation.

[0020] FIG3 is a schematic structural diagram of 180-degree L inductance compensation for wiring in a circuit board assembly according to an embodiment of the present application.

[0021] FIG. 4 is a schematic diagram of impedance simulation of a circuit between a first electronic component and a second electronic component using three different L inductance compensation methods according to an embodiment of the present application.

[0022] FIG5 is a schematic diagram showing simulations of insertion loss of a circuit between a first electronic component and a second electronic component using three different L inductance compensation methods according to an embodiment of the present application.

[0023] FIG6 is a schematic diagram showing the test results of insertion loss of a circuit between a first electronic component and a second electronic component using three different L inductance compensation methods according to one embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly described below in conjunction with the drawings in the embodiments of the present application.

[0025] It is understood that the connection relationships described in this application refer to direct or indirect connections. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B via one or more other electrical components. For example, A and C can be directly connected, and C can be directly connected to B, so that A and B are connected through C. It is also understood that the description of "A connecting to B" in this application can be a direct connection between A and B or an indirect connection between A and B via one or more other electrical components.

[0026] In the description of this application, unless otherwise specified, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0027] In the description of this application, words such as "first" and "second" are used only to distinguish different objects and do not limit the quantity or execution order. In addition, words such as "first" and "second" do not necessarily mean different. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0028] The technical solution of the present application is further described in detail below with reference to the accompanying drawings.

[0029] Please refer to Figure 1. One embodiment of the present application provides a circuit board assembly 10. The circuit board assembly 10 can be integrated into an electronic device. The electronic device can be a mobile phone, a desktop computer host, a server, a television, a laptop computer, etc. The embodiment of the present application does not limit the type of electronic device.

[0030] The circuit board assembly 10 includes a circuit board 11, a first electronic component 12, and a second electronic component 13. The first electronic component 12 includes a first pin 121, and the second electronic component 13 includes a second pin 131. The first pin 121 and the second pin 131 can be data pins for data transmission between the two electronic components.

[0031] High-speed signals can be transmitted between the first electronic component 12 and the second electronic component 13 . For example, the high-speed signal may refer to a signal with a transmission rate of GB / s or MT / s.

[0032] Taking the first electronic component 12 as a central processing unit and the second electronic component 13 as a memory as an example, for the DDR5 series memory (fifth-generation DDRSDRAM, i.e., fifth-generation double data rate synchronous dynamic random access memory), the first electronic component 12 and the second electronic component 13 can transmit signals up to 5600MT / s.

[0033] The present embodiment does not limit the chip types of the first electronic component 12 and the second electronic component 13. These chips can be chips that require high-speed (GB / s or MT / s-level) single-ended signal transmission between them. For example, the first electronic component 12 can be a central processing unit or memory, and the second electronic component 13 can be a south bridge chip.

[0034] As shown in FIG1 , it is assumed that the signal transmitted between the first pin 121 of the first electronic component 12 and the second pin 131 of the second electronic component 13 is a high-speed single-ended signal. A first solder pad 110 for connecting to the first pin 121, a second solder pad 111 for connecting to the second pin 131, and a trace 112 for connecting the first solder pad 110 and the second solder pad 111 are provided on the circuit board 11. The trace 112 may be a copper foil trace.

[0035] Circuit 112 may include a first trace 1121 and a second trace 1122. One end of first trace 1121 is connected to first pad 110, and the other end of first trace 1121 is connected to one end of second trace 1122. The other end of second trace 1122 is connected to second pad 111. Second trace 1122 surrounds a portion of second pad 111 and includes a first trace segment having a first width w1 and a second trace segment having a second width w2. The first width w1 and the second width w2 are not equal.

[0036] FIG2a illustrates an example in which the second trace 1122 surrounds the second pad 111 at an angle of 180° (angle α is 180°), i.e., 180° of L inductive compensation is performed. FIG2b illustrates an example in which the second trace 1122 surrounds the second pad 111 at an angle of 270° (angle α is 270°), i.e., 270° of L inductive compensation is performed. In other embodiments, the angle at which the second trace 1122 surrounds the second pad 111 may be set according to actual impedance matching requirements, and this embodiment of the present application is not limited thereto.

[0037] FIG2 c takes the case where L inductance compensation is not performed as an example. That is, compared with FIG2 a or FIG2 b , the second trace 1122 does not surround the second pad 111 . This wiring method is a common wiring method in the prior art.

[0038] In some embodiments, the impedance of a circuit can generally be calculated using the following formula: Z = sqrt(L / C), where Z is the impedance of the circuit, L is the parasitic inductance of the circuit, C is the parasitic capacitance of the circuit, and sqrt() is the square root function. By configuring second trace 1122 to surround a portion of second pad 111, the impedance of circuit 112 can be adjusted.

[0039] In some embodiments, since the 45° outgoing angle can make the charge at the edge of the trace more uniform and the electron flow smoother, thereby effectively reducing electromagnetic interference and improving circuit conductivity and reliability, the incoming angle of the second trace 1122 connected to the second pad 111 can be set to 45°, as shown in Figure 2a, the angle γ is 45°.

[0040] Figures 1, 2a, and 2b illustrate that a routing line surrounding a portion of the second pad 111 is arranged around the periphery of the second pad 111. In other embodiments, a routing line surrounding a portion of the first pad 110 may also be arranged around the periphery of the first pad 110, or a routing line surrounding a portion of the first pad 110 may be arranged around the periphery of the first pad 110, and a routing line surrounding a portion of the second pad 111 may be arranged around the periphery of the second pad 111.

[0041] As shown in FIG3 , taking the example of a case where the angle of second trace 1122 around second pad 111 is 180° (angle α is 180°), second trace 1122 includes a first connecting segment 1123, a surrounding segment 1124, and a second connecting segment 1125. Surrounding segment 1124 is connected between first connecting segment 1123 and second connecting segment 1125. First connecting segment 1123 is also connected to first trace 1121, and second connecting segment 1125 is also connected to second pad 111.

[0042] In some embodiments, circuit board 11 further includes a ground plane 14 and a clearance area 15 (an area where copper foil has been hollowed out or removed). Ground plane 14 can be disposed around pads on circuit board 11, for example, around second pad 111. Ground plane 14 can be a copper foil surface. The spacing s2 between surrounding segment 1124 and second pad 111 can be 4 mils, the spacing s1 between surrounding segment 1124 and ground plane 14 can be 4 mils, and the spacing s3 between the portion of second pad 111 not surrounded by surrounding segment 1124 and ground plane 14 can be 5 mils.

[0043] In some embodiments, the spacings s1, s2, and s3 can be set and adjusted according to the actual circuit wiring requirements and the welding accuracy of the welding equipment (wave soldering equipment or reflow soldering equipment). For example, in order to avoid welding short circuits, existing welding equipment generally requires a minimum spacing between wirings of 3.5 mil to 4 mil. With the improvement of welding technology, the values ​​of the spacings s1, s2, and s3 can be set to smaller values.

[0044] In some embodiments, the surrounding segment 1124 can include a first routing segment 1126 having a first width w1 and a second routing segment 1127 having a second width w2. The first routing segments 1126 and the second routing segments 1127 can be arranged alternately to enhance the L inductance compensation effect and reduce signal transmission loss. The lengths of the first routing segments 1126 and the second routing segments 1127 can be equal or unequal.

[0045] In some embodiments, the first width w1 can be equal to the overall width of the line 112, and the second width w2 can be slightly larger than the first width w1 (e.g., larger than 0.5 mil to 1 mil). For example, if the width of the line between the first electronic component 12 and the second electronic component 13 is 3.5 mil, the first width w1 can be 3.5 mil, and the second width w2 can be 4 mil. The specific values ​​of the first width w1 and the second width w2 can also be adjusted according to actual impedance matching requirements, and this application does not limit this.

[0046] In related products, in order to improve the impedance matching effect of the circuit, for electronic components that need to be installed on the circuit board with the help of connectors, surface mounted technology (SMT) connectors are generally selected instead of dual in-line package (DIP) connectors. The circuit of the embodiment of the present application adopts a segmented routing design with a preset angle around the pad before being connected to the pad, which can make up for the impedance mismatch of the circuit and the transmission loss of the signal, and improve the maximum error allowed for the signal transmission of the connector, so that the circuit board can use cheaper DIP parts to replace expensive SMT parts. For example, the second electronic component 13 is a memory, and the memory can be installed on the circuit board not through an expensive SMT connector, but through a cheaper DIP connector.

[0047] As shown in Figure 4, taking a target impedance of 50 ohms as an example, a three-dimensional circuit board simulation model was established to perform impedance simulations for three wiring scenarios: no L inductance compensation (the wiring method shown in Figure 2c), 180-degree L inductance compensation (the wiring method shown in Figure 2a), and 270-degree L inductance compensation (the wiring method shown in Figure 2b). In Figure 4, simulation curve L1 shows the impedance simulation result without L inductance compensation, simulation curve L2 shows the impedance simulation result with 180-degree L inductance compensation, and simulation curve L3 shows the impedance simulation result with 270-degree L inductance compensation. As can be seen from the simulation results shown in Figure 4, the impedance of simulation curve L2 is closer to 50 ohms than the impedance of simulation curve L1.

[0048] Lower insertion loss generally means less signal transmission loss and interference. As shown in Figure 5, simulation curve L11 shows the insertion loss simulation results without L inductance compensation, simulation curve L12 shows the insertion loss simulation results with 180-degree L inductance compensation, and simulation curve L13 shows the insertion loss simulation results with 270-degree L inductance compensation. As shown in Figure 5, simulation curve L12 has the lowest insertion loss, simulation curve L13 has the second lowest insertion loss, and simulation curve L11 has the highest insertion loss.

[0049] As shown in Figure 6, taking the first electronic component 12 as a central processing unit and the second electronic component 13 as a DDR5 series memory as an example, for a DDR5 signal with a speed of up to 5600MT / s, the operating frequency of the central processing unit is 2.8GHz and 5.6GHz. It can also be seen from Figure 6 that the insertion loss of the simulation curve L12 at 2.8GHz and 5.6GHz is the smallest, the insertion loss of the simulation curve L13 at 2.8GHz and 5.6GHz is the second largest, and the insertion loss of the simulation curve L11 at 2.8GHz and 5.6GHz is the largest.

[0050] Taking the first electronic component 12 as a central processing unit and the second electronic component 13 as a DDR5 series memory as an example, the following Table 1 illustrates the test results of the actual measurement and simulation test of the insertion loss of an embodiment of the present application.

[0051] Table 1

[0052] As can be seen from Table 1, whether in actual measurement or simulation test, the insertion loss is the smallest when 180 degrees of L inductive compensation is performed, the insertion loss is the second smallest when 270 degrees of L inductive compensation is performed, and the insertion loss is the largest when no L inductive compensation is performed.

[0053] The present application also provides an electronic device, comprising the circuit board assembly 10 according to any one of the above embodiments.

[0054] The detailed structure of the circuit board assembly 10 can be referred to the above embodiment and will not be repeated here. It can be understood that since the above circuit board assembly 10 is used in the electronic device of the present application, the embodiment of the electronic device of the present application includes all technical solutions of all embodiments of the above circuit board assembly 10, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0055] The above-mentioned circuit board components and electronic devices use a segmented winding design when the wiring is connected to the pads, which can solve the problems of impedance mismatch, excessive crosstalk, and excessive signal transmission loss in high-speed signal transmission, and improve the transmission quality of high-speed signals.

[0056] For those skilled in the art, other corresponding changes or adjustments can be made according to the application scheme and application concept of this application in combination with the actual needs of production, and these changes and adjustments should fall within the scope disclosed in this application.

Claims

1. A circuit board assembly, comprising a circuit board and a first electronic component and a second electronic component disposed on the circuit board, the first electronic component including a first pin, and the second electronic component including a second pin, wherein, a first pad for connecting the first pin, a second pad for connecting the second pin, and a circuit for connecting the first pad and the second pad are provided on the circuit board; the circuit includes a first trace and a second trace, one end of the first trace is connected to the first pad, the other end of the first trace is connected to one end of the second trace, the other end of the second trace is connected to the second pad, the second trace surrounds a part of the second pad, and the second trace includes a first trace segment having a first width and a second trace segment having a second width.

2. The circuit board assembly according to claim 1, wherein, the surrounding angle of the second trace around the second pad is 180°.

3. The circuit board assembly according to claim 1, wherein, the surrounding angle of the second trace around the second pad is 270°.

4. The circuit board assembly according to claim 2 or 3, wherein, the second trace includes a first connection segment, a surrounding segment, and a second connection segment, the surrounding segment is connected between the first connection segment and the second connection segment, the first connection segment is further connected to the first trace, the second connection segment is further connected to the second pad, and the distance between the surrounding segment and the second pad is 4 mil.

5. The circuit board assembly according to claim 4, wherein, a ground plane is further provided on the circuit board, the ground plane is disposed around the second pad, the distance between the surrounding segment and the ground plane is 4 mil, and the distance between the part of the second pad not surrounded by the surrounding segment and the ground plane is 5 mil.

6. The circuit board assembly according to claim 1, wherein, the first electronic component is a central processing unit CPU, and the second electronic component is a memory.

7. The circuit board assembly according to claim 6, wherein, the memory is mounted on the circuit board through a dual in-line package DIP connector.

8. The circuit board assembly according to claim 1, wherein, the first trace segment and the second trace segment in the second trace are alternately arranged.

9. The circuit board assembly according to claim 1, wherein, the first width is 3.5 mil, and the second width is 4 mil.

10. An electronic device, wherein, it includes the circuit board assembly according to any one of claims 1 to 9.

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