Hardware breakpoint implementation apparatus and method

Abstract

The application discloses a hardware breakpoint implementation device and method, belongs to the microprocessor debugging technical field, solves the technical problem that the traditional hardware breakpoint is limited by the hardware resource and cannot realize large-area address monitoring, and the software breakpoint cannot be used in the read-only storage body such as ROM / FLASH. The application realizes the setting and monitoring of 4*32 accurate hardware breakpoints and 4 range hardware breakpoints under the premise of only increasing a small amount of register hardware resources through the combination configuration mode of a main breakpoint address register+sub-address register, and the range breakpoint register. Meanwhile, the application designs a breakpoint flag and address recording mechanism to realize the accurate identification and feedback of the breakpoint triggering. The application greatly improves the number and monitoring coverage range of the hardware breakpoint, has low hardware resource consumption, is suitable for the debugging requirements of various storage bodies such as ROM, FLASH and RAM, and can be widely applied to the program debugging scenes of microprocessors and single-chip microcomputers.

Description

Technical Field

[0001] This invention relates to the field of microprocessor debugging technology, specifically to a hardware breakpoint implementation device and method, applicable to program debugging of various microprocessors and microcontrollers. It can realize the setting, monitoring and triggering of a large number of precise hardware breakpoints and range hardware breakpoints in various storage media such as ROM, FLASH, and RAM, thereby improving the efficiency and coverage of program debugging. Background Technology

[0002] Hardware breakpoints are a core mechanism for debugging microprocessor and microcontroller programs. Together with software breakpoints and data breakpoints, they constitute the core functionality of debugging tools. Their primary function is to precisely pause program execution, facilitating debugging by allowing personnel to check the program's running status and locate errors. The implementation principles and applicable scenarios of different breakpoint types differ significantly.

[0003] Software breakpoints: These are implemented by replacing the original instruction at the target address with an interrupt instruction. When the program executes to that address, an interrupt is triggered and the program is paused. They are suitable for RAM memory that can be freely read and written, and a large number of breakpoints can be set. However, because the instruction data at the target address needs to be modified, they cannot be used in read-only memory such as ROM and FLASH, which limits their application scenarios.

[0004] Traditional hardware breakpoints: The target breakpoint address is set through the debug register inside the microprocessor. The CPU monitors the access address of the program bus in real time. When the address matches, an exception is triggered and the program is paused. This method is suitable for read-only memory such as ROM and FLASH, and it makes up for the shortcomings of software breakpoints. However, the implementation of hardware breakpoints requires a lot of hardware register resources. Traditional solutions can usually only set no more than 10 hardware breakpoints. The limited number makes it impossible to monitor a large area of ​​addresses, which is difficult to meet the needs of debugging complex programs.

[0005] Data breakpoints: As a subset of traditional hardware breakpoints, they are specifically designed to monitor memory read, write, and execution operations. Their implementation also relies on debug registers, and therefore, they also suffer from a limited number of breakpoints.

[0006] In actual microprocessor program debugging, especially in scenarios such as industrial control and embedded development, programs are usually stored in read-only memory such as ROM / FLASH, and complex programs need to monitor multiple addresses or address ranges. At this time, software breakpoints are completely ineffective, while traditional hardware breakpoints cannot achieve large-area monitoring due to their limited number, resulting in low debugging efficiency and even the inability to locate some program errors.

[0007] In existing technologies, some solutions attempt to increase the number of hardware breakpoints by increasing the number of debug registers. However, this approach significantly increases hardware resource consumption, raises the design and manufacturing costs of microprocessors, and increases the number of registers, which complicates address comparison logic and reduces the response speed of breakpoint triggering. Another approach attempts to monitor addresses by partitioning them using software algorithms. However, this approach introduces software latency, makes it impossible to trigger breakpoints in real time, and loses the core advantage of hardware breakpoints. Summary of the Invention

[0008] This invention addresses the shortcomings of existing technologies, such as the inability of software breakpoints to adapt to read-only memory and the limited number and lack of range monitoring capabilities of traditional hardware breakpoints. It provides a hardware breakpoint implementation device and method. This invention utilizes a combination of a main breakpoint address register and a sub-address register to generate multiple precise hardware breakpoints from a single set of registers. Simultaneously, it employs a range breakpoint register to monitor address ranges. With only a small increase in register hardware resources, it achieves the setting of 4×32 precise hardware breakpoints and 4 range hardware breakpoints. Furthermore, it designs an efficient address comparison and breakpoint recording mechanism to ensure the real-time and accurate triggering of breakpoints. This invention features low hardware resource consumption, a large number of breakpoints, and support for range monitoring, adapting to the debugging needs of various memory types and significantly improving the efficiency and coverage of microprocessor program debugging.

[0009] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0010] A hardware breakpoint implementation device includes a breakpoint register group, an address comparison module, a breakpoint status recording module, and an external interaction module. Each module interacts with data and signals through an internal bus. The address comparison module is connected to the breakpoint register group, the microprocessor kernel program bus, and the breakpoint status recording module, respectively. The breakpoint status recording module is connected to the external interaction module.

[0011] The breakpoint register group includes four 32-bit breakpoint address registers, four 32-bit sub-address registers, four 32-bit breakpoint range registers, and one 4-bit enable register. Each bit of the enable register corresponds to enabling / disabling one breakpoint address register, and each bit of the sub-address register corresponds to one offset address bit, which is used to combine with the corresponding breakpoint address register to generate a precise breakpoint address.

[0012] The address comparison module is used to monitor the current access address of the microprocessor kernel program bus in real time, and compare it with the 4×32 precise breakpoint addresses and 4 range breakpoint address intervals configured in the breakpoint register group. When the addresses match, a breakpoint trigger signal is output.

[0013] The breakpoint status recording module includes a breakpoint occurrence flag register, a range breakpoint occurrence flag register, and a breakpoint occurrence address register, which are used to receive breakpoint trigger signals, record breakpoint trigger types, and store the trigger address of precise breakpoints.

[0014] The external interaction module is used to realize bidirectional data interaction between the device and the external simulator, and supports the simulator to configure the breakpoint register group and read the breakpoint status recording module data.

[0015] As a further technical solution of the present invention: the 32 bits of the sub-address register correspond to offset addresses 0 to 31 respectively. When a bit in a sub-address register is set to 1, the base address of the corresponding breakpoint address register is added to the offset address of that bit to generate a precise hardware breakpoint address. A single breakpoint address register and the corresponding sub-address register can be combined to generate 1 to 32 precise hardware breakpoint addresses.

[0016] As a further technical solution of the present invention: the range of breakpoint addresses is determined by the base address of the breakpoint address register and the offset value of the breakpoint range register. When the program bus access address falls into this range, it is determined that the range of breakpoint addresses match.

[0017] As a further technical solution of the present invention: the breakpoint occurrence flag register is a 1-bit register, which is set to 1 only when a precise hardware breakpoint is triggered; the range breakpoint occurrence flag register is a 4-bit register, with each bit corresponding to a range breakpoint address interval, and the bit is set to 1 when the corresponding interval triggers a range breakpoint; the breakpoint occurrence address register is a 32-bit register, which stores the actual trigger address of the breakpoint only when a precise hardware breakpoint is triggered.

[0018] A hardware breakpoint implementation method based on the above-mentioned device includes a breakpoint configuration stage, an address monitoring and comparison stage, a breakpoint trigger recording stage, and a breakpoint feedback processing stage. The specific steps are as follows:

[0019] Step 1, Breakpoint Configuration Stage: The external simulator configures the breakpoint register group through the external interaction module, including: selecting the enabled breakpoint address register according to debugging needs and setting the corresponding bit of the enable register to 1; writing the base address to the target breakpoint address register and writing the offset bit configuration value to the corresponding sub-address register to generate a precise hardware breakpoint address; if a range hardware breakpoint needs to be set, writing the range start address to the target breakpoint address register and writing the range offset value to the corresponding breakpoint range register to determine the range breakpoint address range;

[0020] Step 2, Address Monitoring and Comparison Stage: The address comparison module monitors the current access address of the microprocessor kernel program bus in real time, and simultaneously enables precise address comparison and range address comparison: precise address comparison compares the current access address with one by one the precise hardware breakpoint addresses generated by combining 4×32; range address comparison compares the current access address with one by one the four range breakpoint address intervals.

[0021] Step 3, Breakpoint Trigger Recording Stage: When the address comparison module detects an address match, it outputs the corresponding breakpoint trigger signal to the breakpoint status recording module. The breakpoint status recording module then performs a recording operation based on the breakpoint type.

[0022] If it is a precise hardware breakpoint trigger: set the breakpoint occurrence flag to 1, and write the current trigger address to the breakpoint occurrence address register;

[0023] If the breakpoint is triggered by a range hardware breakpoint: set the corresponding breakpoint bit in the range breakpoint occurrence flag register to 1, and do not write data to the breakpoint occurrence address register;

[0024] Step 4, Breakpoint Feedback Processing Stage: The external simulator reads the register data of the breakpoint status recording module in real time through the external interaction module, and performs debugging operations according to the flag status:

[0025] If the breakpoint occurrence flag is 1: the simulator pauses the microprocessor and locates the trigger address stored in the breakpoint occurrence address register for debugging;

[0026] If a certain bit of the flag is set to 1 when a breakpoint occurs in the range: the simulator pauses the microprocessor and locates the starting address of the address range corresponding to the breakpoint for debugging.

[0027] After debugging, the simulator clears the flag bit of the breakpoint status recording module through the external interaction module, resumes microprocessor operation, and continues monitoring.

[0028] As a further technical solution of the present invention: In step 1, the breakpoint register group is allocated a global address in the microprocessor bus. The simulator completes the configuration of the breakpoint register group by reading and writing the global address range. The configuration data can be erased when power is off and supports multiple reconfigurations.

[0029] As a further technical solution of the present invention: In step 2, the precise address comparison and the range address comparison are executed in parallel, and the address comparison module compares the program bus address in real time without delay, and the matching determination only requires 1 clock cycle.

[0030] As a further technical solution of the present invention: In step 3, when multiple precise hardware breakpoints or multiple range breakpoints are triggered simultaneously, the breakpoint status recording module sets all trigger flag bits simultaneously, and the breakpoint occurrence address register stores the address of the first triggered precise breakpoint.

[0031] As a further technical solution of the present invention: In step 4, after the emulator resumes the operation of the microprocessor, the address comparison module continues to perform address monitoring and comparison, and the configuration of the breakpoint register group remains unchanged until the emulator is reconfigured or cleared.

[0032] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0033] 1. Significantly increased number of breakpoints and support for range monitoring: Through the combination configuration mode of "breakpoint address register + sub-address register", 4×32 precise hardware breakpoints can be generated with only 4 main breakpoint address registers set. At the same time, 4 range breakpoint registers are used to realize range monitoring of 4 address intervals, which solves the problem of limited number of traditional hardware breakpoints and inability to monitor a large area, and meets the multi-address debugging needs of complex programs.

[0034] 2. Low hardware resource consumption and easy integration: This invention only adds a small number of registers (sub-address registers, range breakpoint registers) to the traditional hardware breakpoint, without complex calculation modules. The hardware cost of the microprocessor increases by ≤5%, and all modules are implemented by hard-wired hardware. There is no need to modify the core architecture of the microprocessor. It can be directly integrated into the design flow of existing 32-bit / 64-bit microprocessors and microcontrollers.

[0035] 3. Adaptable to all storage devices, overcoming the limitations of software breakpoints: This invention is a pure hardware breakpoint implementation solution. The setting, monitoring and triggering of breakpoints do not require any read or write operations on the target storage device. It can be perfectly implemented in read-only storage devices such as ROM and FLASH, and is also applicable to RAM storage devices. It completely solves the scenario limitations of software breakpoints and realizes breakpoint debugging for all storage devices.

[0036] 4. Real-time and accurate breakpoint triggering with fast response: The comparison logic of the address comparison module is implemented in hardware. The precise address comparison and the range address comparison are executed in parallel. The matching judgment only requires one clock cycle and there is no software delay. At the same time, the breakpoint status recording module can accurately record the trigger address and breakpoint type. The external simulator can quickly locate the debugging position and greatly improve the debugging efficiency.

[0037] 5. Flexible configuration and strong compatibility: The breakpoint register group supports on-demand configuration, allowing users to freely select the number and address of precise breakpoints / range breakpoints, and supports multiple reconfigurations; the external interaction module adopts the standard debug bus protocol, which is fully compatible with existing mainstream emulators, eliminating the need for additional debug software development and reducing the cost of using debug tools. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the module connections for the hardware breakpoint implementation device of the present invention;

[0039] Figure 2 This is a flowchart illustrating the hardware breakpoint implementation method of the present invention;

[0040] Figure 3 This is a schematic diagram illustrating the generation and comparison of precise hardware breakpoint addresses in this invention. Detailed Implementation

[0041] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0042] like Figures 1-3 As shown, the present invention proposes a technical solution from two aspects: hardware device design and method implementation. The device serves as the hardware carrier of the method, and the method achieves full-process management of hardware breakpoints through the collaborative work of various modules of the device.

[0043] I. Hardware Breakpoint Implementation Device

[0044] The hardware breakpoint implementation device of this invention is a pure hardware architecture, integrated inside the microprocessor and seamlessly interfaced with the microprocessor core program bus. It includes four core modules: a breakpoint register group, an address comparison module, a breakpoint status recording module, and an external interaction module. Each module achieves real-time data and signal interaction through an internal high-speed bus. The overall hardware resource consumption is low, adding only a small number of registers to the traditional hardware breakpoint. The specific module design and functions are as follows:

[0045] Breakpoint register set

[0046] As the core of this device's configuration, all registers are 32-bit wide (adapted to the 32-bit microprocessor address bus, expandable to 64-bit), including 4 breakpoint address registers, 4 32-bit sub-address registers, 4 32-bit breakpoint range registers, and 1 4-bit enable register. The functions and relationships of each register are as follows:

[0047] Breakpoint Address Register: Used to write the base address, which is the address reference for precise hardware breakpoints and range hardware breakpoints. The four registers correspond to four groups of precise breakpoints / range breakpoints respectively.

[0048] Sub-address register: Corresponds one-to-one with the breakpoint address register. Its 32 bits correspond to offset addresses 0 to 31 respectively, with each bit being an offset bit. When an offset bit is set to 1, the base address is added to the offset address corresponding to that bit to generate a precise hardware breakpoint address. A single sub-address register can be configured with 1 to 32 offset bits to generate 1 to 32 precise breakpoint addresses.

[0049] Breakpoint Range Register: Corresponds one-to-one with the Breakpoint Address Register. It is used to write the range offset value, which, combined with the base address, determines the address range of the breakpoint. The range is [base address, base address + offset value).

[0050] Enable register: 4 bits correspond to 4 breakpoint address registers. When a bit is set to 1, the corresponding breakpoint address register is enabled, and when it is set to 0, it is disabled. It supports enabling breakpoint groups as needed, reducing the amount of computation for address comparison.

[0051] The breakpoint register group is allocated an independent global address range in the microprocessor's system bus. External emulators can complete register configuration by reading and writing this address range. The configuration data can be erased when power is off and supports multiple reconfigurations.

[0052] Address comparison module

[0053] This is the core computing module of the device, electrically connected to the microprocessor kernel program bus, breakpoint register group, and breakpoint status recording module. Its core function is real-time address monitoring and comparison.

[0054] Real-time monitoring of the current access address of the microprocessor core program bus, which is the address of the instruction / data currently being executed / accessed by the microprocessor, with no latency in data acquisition;

[0055] Simultaneously, precise address comparison and range address comparison are performed, and the two are executed in parallel without interference: precise address comparison compares the current access address with one by one the precise hardware breakpoint addresses generated by combining 4×32; range address comparison compares the current access address with one by one the four range breakpoint address intervals.

[0056] The comparison logic is implemented with hardware hard-wired, and the matching determination only requires one clock cycle, ensuring the real-time triggering of breakpoints; when an address match is detected, the corresponding breakpoint trigger signal (precise breakpoint trigger signal / range breakpoint trigger signal) is immediately output to the breakpoint status recording module.

[0057] Breakpoint status recording module

[0058] This is the core of the device's status recording, including a breakpoint occurrence flag register, a range breakpoint occurrence flag register, and a breakpoint occurrence address register. It receives breakpoint trigger signals from the address comparison module, records breakpoint types, and stores trigger addresses. The functions of each register are as follows:

[0059] Breakpoint occurrence flag register: 1-bit register, set to 1 only when a precise hardware breakpoint is triggered, used to provide feedback on the triggering status of the precise breakpoint to the external simulator;

[0060] Range breakpoint occurrence flag register: a 4-bit register that corresponds one-to-one with the address ranges of the 4 range breakpoints. When a range breakpoint is triggered in the corresponding range, this bit is set to 1. It can record the triggering status of multiple range breakpoints at the same time.

[0061] Breakpoint Address Register: A 32-bit register that is only active when a precise hardware breakpoint is triggered. It stores the actual trigger address of the breakpoint, which helps the simulator to accurately locate the debugging position. If multiple precise breakpoints are triggered simultaneously, it stores the address of the first breakpoint to be triggered.

[0062] All flag registers are set to 1 and held in place. They need to be manually cleared by the external emulator to ensure that the breakpoint state is not lost.

[0063] External interaction module

[0064] This serves as a bidirectional data interaction interface between the device and external simulators, implementing two core functions:

[0065] Configuration data delivery: Receive configuration commands and data from the external simulator, forward them to the breakpoint register group, and complete the breakpoint setting;

[0066] Status data upload: The register data (flag bits, trigger address) of the breakpoint status recording module is forwarded to the external simulator in real time for the simulator to handle breakpoints;

[0067] The external interaction module adopts the standard debug bus protocol, which is fully compatible with existing mainstream simulators and requires no additional debugging software development.

[0068] All modules of this device are implemented in hardware, with no software running delay. It can realize real-time address monitoring and instant breakpoint triggering, and only adds a small amount of register hardware resources. The hardware cost of the microprocessor increases by ≤5%, and it is easy to integrate into the existing microprocessor design flow.

[0069] II. Hardware Breakpoint Implementation Methods

[0070] Based on the aforementioned hardware device, this invention provides a hardware breakpoint implementation method, comprising four major stages: breakpoint configuration, address monitoring and comparison, breakpoint trigger recording, and breakpoint feedback processing. This achieves full automation of the hardware breakpoint "setting-monitoring-triggering-feedback" process, while simultaneously supporting parallel monitoring of precise breakpoints and range breakpoints. The specific steps are as follows:

[0071] Breakpoint configuration phase

[0072] The external emulator establishes a connection with the device's external interaction module through a standard debugging interface. Breakpoint configuration is completed by reading and writing the global address of the breakpoint register group. During the configuration process, precise breakpoints and range breakpoints can be selected as needed. The specific operations are as follows:

[0073] The simulator determines the breakpoint address registers that need to be enabled based on the debugging requirements, sets the corresponding bit in the enable register to 1, and disables the breakpoint groups that do not need to be used.

[0074] To set precise hardware breakpoints: write the base address to the target breakpoint address register, write the offset configuration value to the corresponding sub-address register (set the offset to be used to generate the breakpoint to 1, and set the rest to 0), add the base address to the offset address corresponding to the offset bit set to 1, and generate several precise hardware breakpoint addresses; a single breakpoint address register can be combined to generate 1 to 32 precise breakpoints, and 4 registers can achieve a maximum of 4×32 precise breakpoints;

[0075] To set a range hardware breakpoint: write the range start address (base address) to the target breakpoint address register, and write the range offset value to the corresponding breakpoint range register to determine the address range of the range breakpoint [base address, base address + offset value). A maximum of 4 range breakpoint address ranges can be implemented using 4 registers.

[0076] If you need to set both precise breakpoints and range breakpoints at the same time: Configure different breakpoint address registers as precise breakpoint groups and range breakpoint groups respectively, so that they can work independently and be monitored in parallel.

[0077] Address monitoring and comparison phase

[0078] After the breakpoint configuration is completed, the device automatically enters the monitoring state. The address comparison module collects the current access address of the microprocessor kernel program bus in real time, and simultaneously starts precise address comparison and range address comparison, which are executed in parallel.

[0079] Precise address comparison: The current access address is compared one by one with the precise hardware breakpoint addresses generated by 4×32 combinations to determine whether the addresses match completely.

[0080] Range address comparison: The current access address is compared with the four range breakpoint address intervals one by one to determine whether the address falls within the corresponding interval;

[0081] The address comparison module performs real-time, zero-delay operations, completing a full comparison every clock cycle to ensure that no access address is missed.

[0082] Breakpoint Trigger Recording Phase

[0083] When the address comparison module detects an address match, it immediately outputs the corresponding breakpoint trigger signal to the breakpoint status recording module. The breakpoint status recording module performs the corresponding recording operation according to the breakpoint type (precise breakpoint / range breakpoint). The operation is executed immediately at the hardware level with no delay.

[0084] If it is a precise hardware breakpoint trigger (the current access address completely matches a precise breakpoint address): set the breakpoint occurrence flag to 1, and write the actual trigger address of the breakpoint to the breakpoint occurrence address register to achieve precise recording of the breakpoint trigger address;

[0085] If the hardware breakpoint is triggered by a range (the current access address falls within a certain range of breakpoint addresses): Set the bit corresponding to the breakpoint in the range breakpoint occurrence flag register to 1, without writing data to the breakpoint occurrence address register;

[0086] If multiple breakpoints are triggered simultaneously (multiple precise breakpoints / multiple range breakpoints / precise + range breakpoints): the breakpoint status recording module sets all corresponding flag bits simultaneously, and the breakpoint occurrence address register stores the address of the first precise breakpoint to be triggered.

[0087] Breakpoint feedback handling stage

[0088] The external simulator reads the register data of the breakpoint status recording module in real time through the external interaction module, determines the breakpoint trigger type based on the status of the flag bits, and executes the corresponding debugging operation. The specific process is as follows:

[0089] When the simulator detects that the breakpoint occurrence flag is 1, it immediately sends a pause command to the microprocessor to stop the microprocessor from running; at the same time, it reads the trigger address in the breakpoint occurrence address register and positions the debugging interface at that address, so that the debugging personnel can perform status checks, error location and other operations.

[0090] When the simulator detects that a certain bit of the range breakpoint flag is set to 1, it immediately sends a pause command to the microprocessor to stop the microprocessor from running; at the same time, it determines the corresponding range breakpoint address range based on the bit set to 1, and positions the debugging interface to the starting address of the range, so that the debugging personnel can monitor and debug the range.

[0091] After debugging is completed, the debugging personnel send a resume operation command through the simulator. The simulator clears all the flag bits of the breakpoint status recording module through the external interaction module and sends a resume operation command to the microprocessor at the same time.

[0092] After the microprocessor resumes operation, the device's address comparison module continues to perform address monitoring and comparison. The configuration of the breakpoint register group remains unchanged until the emulator reconfigures the breakpoints or clears the registers, thus achieving continuous breakpoint monitoring.

[0093] In the first stage of the configuration process, the breakpoint register has been assigned a global address on the bus, and the breakpoint register group can be configured by reading and writing this address range;

[0094] The second stage uses 4*32 addresses (breakpoint address registers 1~4 + n), where n is an integer from 0 to 31, corresponding to 32-bit sub-address registers 1~4. For example, if breakpoint address register 1 is configured as 0x0000_8000 and the sub-address register is configured as 0x0000_1010 (bits 4 and 12 are configured as 1), then there are two hardware breakpoints: (0x8000 + 4) and (0x8000 + 12). For the four range hardware breakpoints, a range breakpoint is successfully detected when the program address falls within the address range [address registers 1~4, address registers 1~4 + range registers). For example, if address register 1 is configured as 0x8000 and the range register is 0x800, then a range breakpoint is successfully detected when the program address is in [0x8000, 0x8000 + 0x800). Each breakpoint address register is controlled by 1 enable bit, for a total of 4 enable registers.

[0095] The third stage writes the program address that generates the breakpoint into the breakpoint occurrence address register. This only takes effect when a non-range hardware breakpoint is triggered. In this case, the program address that triggers the breakpoint is written into the breakpoint occurrence address register, and the breakpoint occurrence flag is set to 1. When a range breakpoint is generated, only the range hardware breakpoint occurrence flag is set.

[0096] In the fourth stage, the external simulation software accesses the breakpoint occurrence flag and the breakpoint occurrence address register through the global address. When the breakpoint occurrence flag is 1, the simulation software stops at the address pointed to by the breakpoint occurrence address register; when the range hardware breakpoint occurrence flag is 1, the simulation software stops at the starting point of the corresponding range address.

[0097] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0098] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment have been appropriately combined to form other embodiments that are easy for those skilled in the art to understand.

Claims

1. A hardware breakpoint implementation device, characterized in that, It includes a breakpoint register group, an address comparison module, a breakpoint status recording module, and an external interaction module. Each module interacts with data and signals through an internal bus. The address comparison module is connected to the breakpoint register group, the microprocessor kernel program bus, and the breakpoint status recording module, respectively. The breakpoint status recording module is connected to the external interaction module. The breakpoint register group includes four 32-bit breakpoint address registers, four 32-bit sub-address registers, four 32-bit breakpoint range registers, and one 4-bit enable register. Each bit of the enable register corresponds to enabling / disabling one breakpoint address register, and each bit of the sub-address register corresponds to one offset address bit, which is used to combine with the corresponding breakpoint address register to generate a precise breakpoint address. The address comparison module is used to monitor the current access address of the microprocessor kernel program bus in real time, and compare it with the 4×32 precise breakpoint addresses and 4 range breakpoint address intervals configured in the breakpoint register group. When the addresses match, a breakpoint trigger signal is output. The breakpoint status recording module includes a breakpoint occurrence flag register, a range breakpoint occurrence flag register, and a breakpoint occurrence address register, which are used to receive breakpoint trigger signals, record breakpoint trigger types, and store the trigger address of precise breakpoints. The external interaction module is used to realize bidirectional data interaction between the device and the external simulator, and supports the simulator to configure the breakpoint register group and read the breakpoint status recording module data.

2. The hardware breakpoint implementation device according to claim 1, characterized in that, The 32 bits of the sub-address register correspond to offset addresses 0 to 31 respectively. When a bit in a sub-address register is set to 1, the base address of the corresponding breakpoint address register is added to the offset address of that bit to generate a precise hardware breakpoint address. A single breakpoint address register and the corresponding sub-address register can be combined to generate 1 to 32 precise hardware breakpoint addresses.

3. The hardware breakpoint implementation device according to claim 1, characterized in that, The range of breakpoint addresses is determined by the base address of the breakpoint address register and the offset value of the breakpoint range register. When the program bus access address falls into this range, it is determined that the range of breakpoint addresses match.

4. The hardware breakpoint implementation device according to claim 1, characterized in that, The breakpoint occurrence flag register is a 1-bit register, which is set to 1 only when a precise hardware breakpoint is triggered; the range breakpoint occurrence flag register is a 4-bit register, with each bit corresponding to a range breakpoint address interval, and the bit is set to 1 when a range breakpoint is triggered in the corresponding interval; the breakpoint occurrence address register is a 32-bit register, which stores the actual trigger address of the breakpoint only when a precise hardware breakpoint is triggered.

5. A method for implementing hardware breakpoints based on the device according to any one of claims 1-4, characterized in that, The process includes the breakpoint configuration phase, address monitoring and comparison phase, breakpoint trigger recording phase, and breakpoint feedback processing phase. The specific steps are as follows: Step 1, Breakpoint Configuration Stage: The external simulator configures the breakpoint register group through the external interaction module, including: selecting the enabled breakpoint address register according to debugging needs and setting the corresponding bit of the enable register to 1; writing the base address to the target breakpoint address register and writing the offset bit configuration value to the corresponding sub-address register to generate a precise hardware breakpoint address; if a range hardware breakpoint needs to be set, writing the range start address to the target breakpoint address register and writing the range offset value to the corresponding breakpoint range register to determine the range breakpoint address range; Step 2, Address Monitoring and Comparison Stage: The address comparison module monitors the current access address of the microprocessor kernel program bus in real time, and simultaneously enables precise address comparison and range address comparison: precise address comparison compares the current access address with one by one the precise hardware breakpoint addresses generated by combining 4×32; range address comparison compares the current access address with one by one the four range breakpoint address intervals. Step 3, Breakpoint Trigger Recording Stage: When the address comparison module detects an address match, it outputs the corresponding breakpoint trigger signal to the breakpoint status recording module. The breakpoint status recording module then performs a recording operation based on the breakpoint type. If it is a precise hardware breakpoint trigger: set the breakpoint occurrence flag to 1, and write the current trigger address to the breakpoint occurrence address register; If the breakpoint is triggered by a range hardware breakpoint: set the corresponding breakpoint bit in the range breakpoint occurrence flag register to 1, and do not write data to the breakpoint occurrence address register; Step 4, Breakpoint Feedback Processing Stage: The external simulator reads the register data of the breakpoint status recording module in real time through the external interaction module, and performs debugging operations according to the flag status: If the breakpoint occurrence flag is 1: the simulator pauses the microprocessor and locates the trigger address stored in the breakpoint occurrence address register for debugging; If a certain bit of the flag is set to 1 when a breakpoint occurs in the range: the simulator pauses the microprocessor and locates the starting address of the address range corresponding to the breakpoint for debugging. After debugging, the simulator clears the flag bit of the breakpoint status recording module through the external interaction module, resumes microprocessor operation, and continues monitoring.

6. The hardware breakpoint implementation method according to claim 5, characterized in that, In step 1, the breakpoint register group is allocated a global address in the microprocessor bus. The simulator completes the configuration of the breakpoint register group by reading and writing the global address range. The configuration data can be erased when power is off and supports multiple reconfigurations.

7. The hardware breakpoint implementation method according to claim 5, characterized in that, In step 2, the precise address comparison and the range address comparison are executed in parallel. The address comparison module compares the program bus address in real time with no delay, and the matching determination only requires one clock cycle.

8. The hardware breakpoint implementation method according to claim 5, characterized in that, In step 3, when multiple precise hardware breakpoints or multiple range breakpoints are triggered simultaneously, the breakpoint status recording module sets all trigger flag bits at the same time, and the breakpoint occurrence address register stores the address of the first triggered precise breakpoint.

9. The hardware breakpoint implementation method according to claim 5, characterized in that, In step 4, after the emulator resumes microprocessor operation, the address comparison module continues to perform address monitoring and comparison, and the configuration of the breakpoint register group remains unchanged until the emulator is reconfigured or cleared.

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