Method and device for obtaining interrupt vector table data, electronic equipment and storage medium

Abstract

The application relates to an acquisition method and device of interrupt vector table data, electronic equipment and a storage medium. The method is applied to a memory control module in a system, the system comprising a memory, a central processing unit and the memory control module. The method comprises the following steps: receiving an address instruction sent by the central processing unit, the address instruction comprising a storage address of an interrupt vector table stored in the memory before a preset event occurs; in the case that the storage address belongs to a first storage area, acquiring an address offset between the first storage area and a second storage area, and updating the storage address according to the address offset to obtain a target storage address; and sending the target storage address to the memory to acquire interrupt vector table data stored by the interrupt vector table, and sending the interrupt vector table data to the central processing unit. Therefore, the rate and efficiency of the interrupt processing process are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and storage medium for acquiring interrupt vector table data. Background Technology

[0002] Online chip upgrades (FOTA (Firmware Over-The-Air)) have become a core and essential function of MCUs (Microcontroller Units).

[0003] During the online chip upgrade process, the interrupt vector table will be migrated to a new storage area of ​​the memory along with the system code. However, the address access logic of the CPU (Central Processing Unit) is fixed, and it will still issue address instructions pointing to the original interrupt vector table. This makes it impossible to accurately obtain the interrupt vector table stored in the new location after the upgrade, which in turn affects the normal execution of interrupt handling.

[0004] In response, related technologies have addressed this by storing the secondary jump instruction at address zero, which is directly accessed by the CPU, thereby changing the jump address of the secondary jump instruction and flexibly jumping to the address where the interrupt handling instruction is actually stored, thus achieving the acquisition of the interrupt vector table. However, this method requires the system program to add additional programs, and the processing requires two program executions, resulting in a relatively slow and inefficient interrupt handling process. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and storage medium for obtaining interrupt vector table data, in order to solve the technical problem that the existing method of storing the instruction for a secondary jump at the zero address directly accessed by the CPU, thereby changing the jump address of the secondary jump instruction to obtain the interrupt vector table, would require the system program to add additional programs and require two program executions, resulting in a slow and inefficient interrupt handling process.

[0006] In a first aspect, this application provides a method for acquiring interrupt vector table data, applied to a memory control module in a system. The system includes a memory, a central processing unit, and the memory control module. The memory stores the interrupt vector table and, in response to a preset event, moves the storage area of ​​the interrupt vector table from a first storage area to a second storage area. The method includes: Receives an address instruction sent by the central processing unit, the address instruction including the storage address of the interrupt vector table stored in the memory before a preset event occurs; If it is determined that the storage address belongs to the first storage area, the address offset between the first storage area and the second storage area is obtained, and the storage address is updated according to the address offset to obtain the target storage address; The target memory address is sent to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and the interrupt vector table data is sent to the central processing unit.

[0007] As an optional implementation, before receiving the address instruction sent by the central processing unit, the following steps are also included: In response to the key sent by the central processing unit, the key is verified; If the key verification is successful, the first storage address of the first storage area and the second storage address of the second storage area are determined respectively, and the first storage address and the second storage address are stored in the preset area information storage module; Based on the first storage address and the second storage address, determine the address offset between the first storage area and the second storage area, and store the address offset in a preset offset storage module; The offset function is enabled. This function indicates whether, upon receiving an address instruction from the central processing unit (CPU), the storage address in the address instruction belongs to the first storage region. If the storage address belongs to the first storage region, the address offset between the first storage region and the second storage region is obtained, and the storage address is updated based on the address offset to obtain the target storage address. The target storage address is then sent to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and the interrupt vector table data is sent to the CPU.

[0008] As an optional implementation, verifying the key includes: The key is input into a preset key storage module so that the key storage module can determine whether the key is consistent with the preset key; If the key is determined to be consistent with the preset key through the key storage module, the key verification is deemed successful. If the key storage module determines that the key is inconsistent with the preset key, the key verification fails.

[0009] As an optional implementation, if it is determined that the key verification fails, the method further includes: Upon receiving an address instruction from the central processing unit, the storage address included in the address instruction is sent to the memory to obtain the data stored at the storage address, and the data is then sent to the central processing unit.

[0010] As an optional implementation, the first storage address includes the first start address and the first end address of the first storage area, and the second storage address includes the second start address and the second end address of the second storage area; Determining the address offset between the first storage region and the second storage region based on the first storage address and the second storage address includes: Subtracting the first starting address from the second starting address yields the address offset between the first storage region and the second storage region. or, Subtracting the first terminal address from the second terminal address yields the address offset between the first storage area and the second storage area.

[0011] As an optional implementation, the first storage address includes the first start address and the first end address of the first storage region; The step of determining that the storage address belongs to the first storage region includes Determine whether the storage address is greater than or equal to the first starting address and less than or equal to the first ending address; If the storage address is determined to be greater than or equal to the first starting address and less than or equal to the first ending address, then the storage address is determined to belong to the first storage region.

[0012] As an optional implementation, obtaining the address offset between the first storage region and the second storage region includes: Obtain the address offset between the first storage area and the second storage area from the offset storage module.

[0013] As an optional implementation, the memory includes multiple different second storage areas, and the offset storage module is used to store multiple preset address offsets, each address offset corresponding to a second storage area; The step of obtaining the address offset between the first storage region and the second storage region includes: Determine the target second storage area based on preset rules or received area selection instructions; Determine the target address offset corresponding to the target second storage area from the offset storage module; The target address offset is determined as the address offset between the first storage area and the second storage area.

[0014] As an optional implementation, updating the storage address based on the address offset to obtain the target storage address includes: The target storage address is obtained by adding the storage address to the address offset.

[0015] As an optional implementation, if it is determined that the storage address does not belong to the first storage region, the method further includes: The storage address is sent to the memory to obtain the data stored at the storage address, and the data is then sent to the central processing unit.

[0016] Secondly, this application provides an interrupt vector table data acquisition device, applied to a memory control module in a system. The system includes a memory, a central processing unit, and the memory control module. The memory is used to store the interrupt vector table, and in response to a preset event, moves the storage area of ​​the interrupt vector table from a first storage area to a second storage area. The device includes: The instruction receiving module is used to receive address instructions sent by the central processing unit. The address instructions include the storage address of the interrupt vector table stored in the memory before a preset event occurs. The offset acquisition module is used to acquire the address offset between the first storage area and the second storage area when it is determined that the storage address belongs to the first storage area, and update the storage address according to the address offset to obtain the target storage address; The data acquisition module is used to send the target storage address to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and send the interrupt vector table data to the central processing unit.

[0017] Thirdly, this application provides an electronic device, including: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store a computer program; and the processor is used to implement the interrupt vector table data acquisition method described in any one of the first aspects when executing the computer program.

[0018] Fourthly, this application provides a storage medium storing a computer program thereon, which, when executed by a processor, implements the method for obtaining interrupt vector table data as described in any of the first aspects.

[0019] Compared with the prior art, the technical solution provided in this application has the following advantages: The method provided in this application implements hardware-level address remapping within the memory control module, enabling accesses issued by the central processing unit (CPU) pointing to the original interrupt vector table address to be intercepted, judged, and automatically added with a preset offset in real time, thereby transparently redirecting to the migrated actual storage address. This mechanism can complete address translation at the hardware level in real time without requiring the CPU to execute any additional jump instructions. It enables the CPU using a fixed interrupt address access mechanism to seamlessly and safely adapt to the migration of the interrupt vector table region caused by system upgrades or backup recovery, while ensuring the real-time nature of interrupt response (no software delay). This fundamentally solves the performance loss and complexity problems of traditional software jump schemes, thereby improving the speed and efficiency of interrupt handling, enabling interrupt response to reach hardware speeds close to the theoretical limit, and providing stable and reliable underlying hardware support for the system, significantly enhancing the success rate of the upgrade process and the overall robustness of the system. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0023] Figure 1 A schematic diagram of the structure of an interrupt vector table data acquisition system provided in this application embodiment; Figure 2 A flowchart illustrating an embodiment of a method for obtaining interrupt vector table data provided in this application; Figure 3 A flowchart illustrating an embodiment of another method for obtaining interrupt vector table data provided in this application; Figure 4 A flowchart illustrating an embodiment of another method for obtaining interrupt vector table data provided in this application; Figure 5This application provides a schematic diagram of the spatial structure of a memory. Figure 6 A block diagram illustrating an embodiment of an interrupt vector table data acquisition device provided in this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0026] To address the problem that existing methods of storing secondary jump instructions at the CPU's directly accessed zero address, thereby altering the jump address of these instructions to obtain the interrupt vector table, necessitate adding extra code to the system program and requiring two separate program executions, resulting in slow and inefficient interrupt handling, this application provides a method for obtaining interrupt vector table data. This method achieves hardware-level address remapping within the memory control module, enabling real-time interception, judgment, and automatic addition of a preset offset to accesses from the CPU pointing to the original interrupt vector table address. This transparently redirects the accesses to the migrated actual memory address. Address translation can be completed in real time at the hardware level without the need for the central processing unit to execute any additional jump instructions. This enables the central processing unit with a fixed interrupt address access mechanism to seamlessly and safely adapt to the migration of the interrupt vector table region caused by system upgrades or backup recovery, while ensuring real-time interrupt response (no software delay). This fundamentally solves the performance loss and complexity problems of traditional software jump schemes, thereby improving the speed and efficiency of interrupt handling, enabling interrupt response to reach hardware speeds close to the theoretical limit, while providing stable and reliable underlying hardware support for the system, significantly enhancing the success rate of the upgrade process and the overall robustness of the system.

[0027] To facilitate understanding of the method for obtaining interrupt vector table data provided in this application, the following example illustrates the system corresponding to this method: See Figure 1 This is a schematic diagram of the structure of an interrupt vector table data acquisition system provided in an embodiment of this application. Figure 1 As shown, the system 10 may include: a central processing unit 11, a memory control module 12, and a memory 13.

[0028] The aforementioned central processing unit 11 refers to a hardware computing and control unit, such as a CPU, that executes instructions according to fixed program logic and automatically accesses a fixed address to obtain the interrupt vector table when an interrupt occurs.

[0029] The aforementioned memory control module 12 refers to a dedicated hardware unit located between the central processing unit and the memory, which implements address remapping and access control through hardware circuitry. It is used to transparently intercept and redirect access to specific address regions (such as interrupt vector tables).

[0030] The aforementioned memory 13 refers to a hardware device used to store program instructions and data, which can be accessed by a central processing unit or memory controller according to an address signal. It may include, but is not limited to, non-volatile memory chips such as Flash memory, ROM read-only memory or EEPROM electrically erasable memory.

[0031] In this embodiment, the central processing unit 11, the memory control module 12, and the memory 13 are connected in series via a system bus. Specifically, the address bus and data bus of the central processing unit 11 are first connected to the memory control module 12, and then connected to the memory 13 by the module. The memory control module 12 is physically and logically located between the central processing unit 11 and the memory 13, serving as the essential hub and control node for all access and interaction between the two.

[0032] In practical applications, Figure 1 The system shown can be an embedded system, and its typical application scenario is online secure firmware upgrades. In this scenario, to ensure the reliability of the upgrade process, the system needs to completely copy the interrupt vector table from the first storage area of ​​the memory to the second storage area as a backup.

[0033] In this case, in the prior art, the hardware design of the central processing unit 11 is fixed. When an interrupt occurs, it will still directly access the memory 13 at the fixed address of the first memory area, which will prevent it from directly obtaining the correct interrupt vector table after migration, thus leading to performance loss or implementation obstacles.

[0034] In this embodiment, a memory control module 12 can be added between the central processing unit 11 and the memory 13. The memory control module 12 can use the interrupt vector table data acquisition method provided in this application to intercept, judge and redirect the CPU's access address in real time at the hardware level, so that the CPU can seamlessly and transparently access the interrupt vector table of the new area and send the interrupt vector table data corresponding to the interrupt vector table to the central processing unit 11.

[0035] This ensures real-time and deterministic interrupt response without modifying the CPU or increasing software latency, thereby maintaining high performance, high reliability, and high compatibility of the system during critical processes such as firmware upgrades or backup switching.

[0036] The method for obtaining interrupt vector table data provided in this application will be further explained below with reference to the accompanying drawings and specific embodiments. The embodiments do not constitute a limitation on the embodiments of this application.

[0037] See Figure 2 This is a flowchart illustrating an embodiment of a method for obtaining interrupt vector table data provided in this application. As one embodiment, Figure 2 The illustrated process can be applied to a memory control module in a system that may include a memory, a central processing unit, and a memory control module. The memory can be used to store an interrupt vector table, and in response to a preset event, the storage area of ​​the interrupt vector table is moved from a first storage area to a second storage area. The system can be described as follows: Figure 1 System 10 is shown. (e.g.) Figure 2 As shown, the process may include the following steps: Step 201: Receive the address instruction sent by the central processing unit. The address instruction includes the storage address of the interrupt vector table stored in memory before the occurrence of the preset event.

[0038] The aforementioned central processing unit refers to the main control chip in the system that executes program instructions and generates memory access requests. Its key feature is that when an interrupt occurs, its hardware logic will automatically and consistently initiate a read request to a preset memory address (i.e., the traditional interrupt vector table address).

[0039] The aforementioned address instruction refers to a set of electrical signals sent by the central processing unit through the address bus to uniquely identify the memory location it wants to access. It is not a software "instruction" but a hardware-level access request.

[0040] The aforementioned preset events refer to operational events initiated or pre-planned by the system software that cause the interrupt vector table to be copied entirely from its original storage location in memory or moved to another backup area, such as firmware online upgrades, security backups, or the initiation of system recovery processes.

[0041] The aforementioned storage address refers to the specific access address contained in the address instruction. In this step, it specifically refers to the storage address in memory where the interrupt vector table is stored before the preset event occurs, i.e., the old address, fixed address, or logical address of the interrupt vector table before migration.

[0042] In this step, when the system is running an application and an interrupt is triggered (e.g., an external hardware timer overflow causes an interrupt), the CPU can generate an address instruction to read the interrupt vector table. This address instruction may include the memory address where the interrupt vector table is stored before a preset event occurs. This address instruction can then be sent to the memory control module, which can receive the address instruction. In one embodiment, the interrupt controller of the central processing unit can automatically point the program counter to a fixed interrupt entry address (e.g., 0x00000000) and issue a read instruction, i.e., an address instruction, through the address bus.

[0043] At this point, the memory control module is physically located downstream of the central processing unit's address bus. The central processing unit's address bus pins are directly connected to, or connected via the system bus to, the address input interface of the memory control module.

[0044] In this scenario, when the central processing unit initiates a read operation, a valid address signal appears on its address bus. The input buffer or address latch inside the memory control module, under the control of the system clock, captures and stabilizes this address signal, providing it as an address instruction to the internal logic for processing.

[0045] Step 202: If it is determined that the above storage address belongs to the first storage area, obtain the address offset between the first storage area and the second storage area, and update the storage address according to the address offset to obtain the target storage address.

[0046] The aforementioned first storage region refers to a configurable, contiguous range of physical addresses. It is defined as the original region where the interrupt vector table is stored before a preset event (such as firmware upgrade or security backup) occurs. For example, the starting address is 0x0000 and the ending address is 0x03FF.

[0047] The aforementioned second storage area refers to a configurable, contiguous range of physical addresses. It is defined as the original area where the interrupt vector table is stored after a preset event (such as firmware upgrade or security backup). For example, it might start at address 0x0400 and end at address 0x04FF.

[0048] The aforementioned address offset refers to a pre-calculated and stored value, representing the arithmetic difference between the starting address of the second storage area and the starting address of the first storage area (usually the starting address of the second area minus the starting address of the first area).

[0049] The aforementioned target storage address refers to the new address obtained after remapping the original "storage address" in the address instruction.

[0050] In this step, during the system initialization or upgrade process, the software calculates the offset between the new and old interrupt vector table regions (for example, if the starting address of the new region is 0x8000 and the starting address of the old region is 0x0000, then the offset is 0x8000) and writes it into the "offset register" of the memory control module.

[0051] In this step, after receiving the address instruction sent by the central processing unit, the memory control module can parse the memory address included in the address instruction and determine whether the memory address is in the first memory area before the interrupt vector table offset.

[0052] In one embodiment, a "region range comparator" circuit may be provided inside the memory control module. This circuit compares the latched "memory address" with the values ​​in the "first memory region start address register" and the "first memory region end address register" simultaneously.

[0053] Optionally, when the storage address is greater than or equal to the start address of the first storage area and the storage address is less than or equal to the end address of the first storage area, the comparator can output a "hit" signal, which means that the storage address belongs to the first storage area.

[0054] Optionally, when the storage address is less than the start address of the first storage area, or when the storage address is greater than the end address of the first storage area, the comparator can output a "miss" signal, which means that the storage address does not belong to the first storage area.

[0055] Based on this, in one embodiment, if it is determined that the storage address belongs to the first storage area, the address offset between the first storage area and the second storage area can be obtained, and the storage address can be updated according to the address offset to obtain the target storage address.

[0056] As an optional implementation, the memory control module can internally maintain a "first region start address register" and a "second region start address register". Based on this, when determining the address offset, the memory control module can read the values ​​from these two registers in real time and subtract them to obtain the aforementioned address offset.

[0057] As an alternative implementation, the memory control module can obtain the target memory address by adding the memory address to the address offset.

[0058] Furthermore, in one embodiment, if it is determined that the aforementioned storage address does not belong to the first storage region, the storage address corresponding to the aforementioned address instruction can be sent to the memory to obtain the data stored at the storage address in the address instruction, and then the data can be sent to the central processing unit. This data can be interrupt vector table data stored in an interrupt vector table stored in another region, or ordinary program code, etc.

[0059] Step 203: Send the target memory address to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and send the interrupt vector table data to the central processing unit.

[0060] The aforementioned memory refers to the physical chip that stores data, such as Flash or ROM. Internally, it also has a secondary storage area, which is the new or backup area where the interrupt vector table is actually located after migration.

[0061] The interrupt vector table data mentioned above refers to the specific data content read from the memory location corresponding to the "target memory address". This is usually the entry address of an interrupt service routine. For example, if 0x12345678 is read, this value is the starting address of the code segment that handles the specific interrupt.

[0062] In this step, the memory control module can send the obtained target memory address to the memory, and the memory can read and send the interrupt vector table data corresponding to the target memory address. The memory control module can then send the interrupt vector table data read from the memory to the central processing unit.

[0063] In one embodiment, the memory control module can transmit the acquired interrupt vector table data back to the central processing unit via the data bus, according to the system protocol.

[0064] For example, suppose the address instruction sent by the CPU has a memory address of 0x0100 (located in the first region). Continuing to assume the address offset is 0x8000, then after calculation in step 202, the target address becomes 0x8100 (0x0100 + 0x8000). The memory control module requests data from the memory at address 0x8100 and returns the read interrupt vector entry address (e.g., 0x20001000) to the CPU. The CPU then jumps to 0x20001000 to execute the actual interrupt service routine.

[0065] As an optional implementation, the memory control module can store the interrupt vector data returned from memory into an internal "data buffer." The memory control module ensures that this interrupt vector data is associated with the initial access request issued by the CPU, then drives the data bus and sends the interrupt vector data back to the CPU. The entire process is completely transparent to the CPU; it believes it has read the correct data from address 0x0100, when in fact the data comes from 0x8100.

[0066] Continuing the assumption, the CPU accesses address 0x4000 (not in the first region). The region comparator misses, and the address is not offset. The memory control module directly accesses memory address 0x4000 and returns the data (which could be ordinary program code or data) from that location to the CPU.

[0067] The technical solution provided in this application embodiment receives an address instruction sent by a central processing unit. The address instruction includes, before a preset event occurs, storing the address of the interrupt vector table in the memory. If it is determined that the storage address belongs to a first storage area, the address offset between the first storage area and the second storage area is obtained, and the storage address is updated according to the address offset to obtain a target storage address. The target storage address is then sent to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and the interrupt vector table data is then sent to the central processing unit. This technical solution, through hardware-level address remapping within the memory control module, enables accesses from the central processing unit (CPU) pointing to the original interrupt vector table address to be intercepted, judged, and automatically redirected to the migrated actual memory address in real time by adding a preset offset. This mechanism can complete address translation instantly at the hardware level without requiring the CPU to execute any additional jump instructions. It enables the CPU using a fixed interrupt address access mechanism to seamlessly and safely adapt to the migration of the interrupt vector table region caused by system upgrades or backups while ensuring real-time interrupt response (no software delay). This fundamentally solves the performance loss and complexity problems of traditional software jump schemes, thereby improving the speed and efficiency of interrupt handling, enabling interrupt response to reach near-theoretical hardware speeds, and providing stable and reliable underlying hardware support for the system, significantly enhancing the success rate of upgrades and the overall robustness of the system.

[0068] See Figure 3 This is a flowchart illustrating an embodiment of another method for obtaining interrupt vector table data provided in this application. Figure 3 The process shown is in Figure 2 Based on the illustrated process, this section describes how the memory control module stores the address offset between the first and second memory regions before receiving address instructions from the central processing unit, and how it enables the offset function. For example... Figure 3 As shown, the process may include the following steps: Step 301: In response to the key sent by the central processing unit, verify the key.

[0069] The aforementioned key refers to a specific set of data provided by software running on the central processing unit. Its function is to serve as an access credential or security token. It does not contain configuration information itself and is only used to unlock subsequent configuration permissions.

[0070] In this step, during Figure 2Before the address remapping function in the illustrated process, the address remapping function directly determines whether the CPU can correctly access the interrupt vector table, which is a critical low-level hardware configuration of the system. If this configuration is incorrectly modified or tampered with by malicious software (such as pointing interrupt vectors to malicious code areas), it will lead to system crashes or complete control. Therefore, a high-threshold hardware security lock must be established for configuration permissions.

[0071] Therefore, to implement hardware-level access control for the configuration interface, and to ensure that only legitimate software (usually a system bootloader or security monitoring program) with the correct key can unlock configuration permissions, thereby fundamentally preventing unauthorized configuration and guaranteeing the reliable initialization of the remapping function, the memory control module can have a key verification mechanism. Before the central processing unit (CPU) obtains interrupt vector table data, it can send a key to the memory control module, which can then verify the key received from the CPU.

[0072] In one embodiment, after the system powers on, the first-stage bootloader (BootROM) needs to configure a remapping to jump to the second-stage bootloader before transferring control. It reads a preset key from its secure storage area and sends it to the memory control module.

[0073] In another embodiment, before formally activating the new firmware, the upgrade manager must first remap the interrupt vector table to the new region. Before performing this operation, it needs to verify its legitimacy as part of the upgrade process through key verification. Therefore, a preset key can be obtained and sent to the memory control module first.

[0074] In one embodiment, when verifying a received key, the memory control module can input the key into a preset key storage module, which then determines whether the key matches a preset key. The key storage module refers to a read-only memory unit within the memory control module, such as a KEY register, used to securely store a preset verification key. It loads a fixed value upon hardware power-on and compares the received software key with this value during runtime to determine whether to unlock configuration permissions.

[0075] Optionally, if the received key is confirmed to be consistent with the preset key through the key storage module, the key verification can be considered successful.

[0076] Optionally, if the received key is determined by the key storage module to be inconsistent with the preset key, the key verification can be deemed unsuccessful.

[0077] Furthermore, if key verification fails, it indicates that configuration permissions are not available. If an address instruction is received from the central processing unit (CPU), the memory address included in the instruction can be directly sent to the memory to retrieve the data stored at that address, and then this data can be sent to the CPU. This data can be interrupt vector table data stored in another region, or ordinary program code, etc.

[0078] Step 302: If the key verification is successful, determine the first storage address of the first storage area and the second storage address of the second storage area respectively, and store the first storage address and the second storage address in the preset area information storage module.

[0079] The aforementioned first storage address and second storage address refer to the boundary information of the first storage region and the second storage region, respectively. These may include, but are not limited to, the start and end addresses of the regions.

[0080] The aforementioned area information storage module refers to a hardware register used to store area information of the first storage area and the second storage area. It can store the aforementioned first storage address and second storage address, such as an area partitioning register, to store the area addresses of the first storage area and the second storage area.

[0081] In this step, in order to determine the respective ranges of the first and second storage regions, the memory control module can determine the first storage address of the first storage region and the second storage address of the second storage region, respectively, after the key verification is passed.

[0082] In one embodiment, a first start address and a first end address of a first storage region can be obtained, and these first start addresses and first end addresses can be used as the first storage address of the first storage region. Simultaneously, a second start address and a second end address of a second storage region can be obtained, and these second start addresses and second end addresses can be determined as the second storage address of the second storage region.

[0083] Subsequently, the aforementioned first and second storage addresses can be stored in a preset area information storage module. The aforementioned area information storage module refers to a programmable register within the memory control module, protected by key verification, used to configure and store the physical address boundaries (such as start and end addresses) between the first and second storage areas.

[0084] As an optional implementation, the first storage address may include a first start address and a first end address of the first storage region, and the second storage address may include a second start address and a second end address of the second storage region. Based on this, the first start address and the first end address can be stored as a set of address information in the region's information storage module, and the second start address and the second end address can be stored as a set of address information in the region's information storage module.

[0085] For example, suppose the interrupt vector table is backed up from the first memory region 0x0000-0x03FF to the second memory region 0x8000-0x83FF. Based on this, after confirming that the verification key has passed, the memory control module can obtain the first start address of the first memory region as 0x0000 and the first end address as 0x03FF, and the second start address of the second memory region as 0x8000 and the second end address as 0x83FF.

[0086] Then, the following can be written sequentially into the area information storage module: first starting address (0x0000), first ending address (0x03FF), second starting address (0x8000), and second ending address (0x83FF).

[0087] Step 303: Determine the address offset between the first storage area and the second storage area based on the first storage address and the second storage address, and store the address offset in a preset offset storage module.

[0088] The aforementioned offset storage module refers to a dedicated hardware register, such as an offset register, pre-set within the memory control module. This offset register can be used to store the offset between the first and second storage areas after calculation.

[0089] In this step, after obtaining the first storage address of the first storage area and the second storage address of the second storage area, the address offset between the first storage area and the second storage area can be determined based on the first storage address and the second storage address, and the address offset can be stored in a preset offset storage module.

[0090] In one embodiment, the controller storage module can directly obtain the first storage address of the first storage area and the second storage address of the second storage area.

[0091] In another embodiment, as can be seen from step 302, after obtaining the first storage address of the first storage area and the second storage address of the second storage area, the controller storage module can store the first storage address and the second storage address into a preset area information storage module. Based on this, the controller storage module can obtain the aforementioned first storage address and second storage address from the area information storage module.

[0092] In one embodiment, the first storage address may include a first start address and a first end address of the first storage region, and the second storage address may include a second start address and a second end address of the second storage region. Since the first and second storage regions correspond to the same interrupt vector table and have the same storage length, as an implementation, when the controller storage module determines the address offset between the first and second storage regions based on the first and second storage addresses, it can subtract the first start address from the second start address to obtain the address offset between the first and second storage regions.

[0093] As another implementation, the controller storage module can subtract the first terminal address from the second terminal address to obtain the address offset between the first storage area and the second storage area.

[0094] Furthermore, based on the fact that the first storage address includes the first start address and the second end address of the first storage area, when the memory control module determines whether the storage address in the address instruction in step 202 belongs to the first storage area, it can determine whether the storage address is greater than or equal to the first start address and less than or equal to the first end address.

[0095] Optionally, if it is determined that the storage address is greater than or equal to the first starting address and less than or equal to the first ending address, the storage address can be determined to belong to the first storage area.

[0096] Optionally, if it is determined that the storage address is less than the first starting address, it can be determined that the storage address does not belong to the first storage area.

[0097] Optionally, if it is determined that the storage address is greater than the first terminal address, it can be determined that the storage address does not belong to the first storage area.

[0098] Furthermore, based on the above-mentioned storage of the address offset between the first storage area and the second storage area to the offset storage module, in step 202, when the controller storage module obtains the address offset between the first storage area and the second storage area, it can directly obtain the address offset between the first storage area and the second storage area from the offset storage module.

[0099] Step 304: Enable the offset function. The offset function is used to determine whether the storage address in the address instruction sent by the receiving central processing unit belongs to the first storage area.

[0100] The aforementioned offset function is used to characterize the entire hardware address remapping logic, and it can be used for... Figure 2 The execution logic in the process shown.

[0101] In this step, in order to make Figure 2 When the offset function of the process shown is activated, the controller storage module can enable the offset function after the key is verified and the first storage address, the second storage address, and the address offset between the first storage area and the second storage area are stored.

[0102] In one embodiment, the memory control module may include an offset function module, such as an offset enable register. Based on this, the memory control module can enable the offset function by writing a first preset identifier to a specific enable bit within the offset function module. The first preset identifier refers to a pre-set identifier for enabling the offset function, such as "1" or "FF".

[0103] In addition, if the memory control module determines that the key verification fails, it can determine whether the offset function is enabled. If so, it can disable the offset function.

[0104] In addition, the memory control module completes the execution Figure 2 After completing the process shown, the offset function described above can be turned off.

[0105] Optionally, the offset function can be disabled by writing a second preset identifier into the offset function module. The second preset identifier refers to a pre-set identifier for disabling the offset function, such as "0".

[0106] The technical solution provided in this application achieves secure and reliable management of the entire lifecycle of critical address mapping behavior through a progressive hardware control process from security verification and parameter solidification to function activation. It not only eliminates the risk of illegal tampering during the configuration stage through hardware key verification, but also ensures the accuracy and efficient execution of the mapping relationship through programmable region definition and pre-calculated offset. The atomic enabling mechanism it provides at the end ensures that the system can achieve deterministic and uninterrupted instantaneous switching between different operating modes. As a whole, the system obtains a secure, controllable, flexible, efficient, stable and seamless underlying address remapping capability, which completely solves the access continuity and system reliability problems caused by interrupt vector table migration in scenarios such as firmware upgrades. Thus, it can ensure that the central processing unit can still obtain the correct interrupt vector seamlessly and with zero latency after the interrupt vector table migration caused by system upgrades or backups, ensuring the real-time performance of interrupt response and the reliability of system upgrades.

[0107] See Figure 4 This is a flowchart of an embodiment of another method for obtaining interrupt vector table data provided in this application. Figure 4 The process shown is in Figure 3Based on the illustrated process, this paper describes how, in a scenario where the memory includes multiple different second storage regions, and the aforementioned offset storage module is used to store multiple preset address offsets, each address offset corresponding to a second storage region, the storage address is updated according to the address offset to obtain the target storage address. For example... Figure 4 As shown, the process may include the following steps: Step 401: Determine the target second storage area according to the preset rules or the received area selection instructions.

[0108] The aforementioned preset rules refer to a set of automatic selection logic predefined by hardware or software, which can be based on the system's current security status, operating mode, version number, error count, and other status information.

[0109] The aforementioned region selection instruction refers to a command issued by software running on the central processing unit through methods such as writing to registers, used to explicitly specify the target backup region.

[0110] The aforementioned target second storage area refers to a specific area selected from multiple backup areas (such as backup area A, backup area B, etc.) in the memory according to rules or instructions, which serves as the target destination for this address remapping.

[0111] In this step, in complex systems that support multi-version backups or hierarchical storage, the interrupt vector table may have multiple copies (e.g., stable version, test version, security version) at different points in time, i.e., multiple secondary storage areas. When it is necessary to remap the storage address in the address instruction, the memory control module can dynamically and accurately select the most suitable copy as the source of the interrupt service routine based on the current context (such as system health status, upgrade stage, security policy).

[0112] Based on this, when the memory control module obtains the address offset between the first memory region and the second memory region, it can first determine the target second memory region from multiple second memory regions of the memory according to preset rules or received region selection instructions.

[0113] In one embodiment, the memory control module can automatically select a second storage region that meets preset conditions as the target second storage region according to preset rules.

[0114] As an optional implementation, the second storage region with the highest current security status can be selected as the target second storage region.

[0115] As an alternative implementation, the second storage area where the version number of the stored interrupt vector table is the latest version number can be selected as the target second storage area.

[0116] In another embodiment, after the firmware upgrade manager verifies the new version, it can send a region selection instruction to the memory control module. After receiving the region selection instruction, the memory control module can determine the second storage area corresponding to the region selection instruction, which stores the interrupt vector table of the new version, as the target second storage area.

[0117] In another embodiment, the memory control module can verify the integrity of the interrupt vector table data stored in each second memory region and determine the second memory region with the best integrity as the target second memory region.

[0118] Step 402: Determine the target address offset corresponding to the target second storage area from the above offset storage module.

[0119] Step 403: Determine the target address offset as the address offset between the first storage area and the second storage area.

[0120] The following provides a unified explanation of steps 402 and 403: The aforementioned offset storage module refers to a hardware storage unit capable of storing multiple offsets, such as a register file or a small SRAM array. Each storage unit (entry) corresponds to a second storage region, storing the starting address offset of that region relative to the first storage region.

[0121] The aforementioned target address offset refers to a specific address offset value that has been pre-calculated and stored, corresponding to the "target second storage area" determined in step 401.

[0122] In this step, because the different backup regions have different physical locations in the memory, their address offsets relative to the original first memory region are also different. Therefore, after selecting the target second memory region, the memory control module needs to obtain the matching offset in order to perform the correct address calculation.

[0123] In order to achieve nanosecond-level fast reading and meet the stringent requirements of extremely low latency for interrupt response, the address offset can be pre-stored in the offset storage module, and the correspondence between the address offset and the second storage area can be set.

[0124] Based on this, after determining the target second storage area, the memory control module can determine the target address offset corresponding to the target second storage area from the offset storage module, and determine the target address offset as the address offset between the first storage area and the second storage area.

[0125] As an optional implementation, the offset storage module can consist of multiple registers, each corresponding to a second storage area, used to store the address offset corresponding to the second storage area. Then, the target register corresponding to the target second storage area determined in step 401 can be determined, and the address offset stored in the target register can be read as the target address offset.

[0126] For example, the offset storage module consists of eight 32-bit registers, numbered 0 to 7. If the target region number determined in step 401 is 2, then the memory control module reads the address offset 0x8000 stored in register 2.

[0127] As an alternative implementation, all address offsets can be stored in a read-only offset table. This offset table can store the storage address of the second storage region, the address offset, and the relationship between the two. Based on this, after determining the target second storage region, the memory control module can obtain the storage address of the target second storage region and look up the aforementioned offset table based on the storage address to obtain the target address offset corresponding to the target second storage region.

[0128] The technical solution provided in this application determines a target second storage region based on preset rules or received region selection instructions, determines the target address offset corresponding to the target second storage region from the aforementioned offset storage module, and defines the target address offset as the address offset between the first and second storage regions. This technical solution, by introducing a dynamic region selection mechanism based on preset rules or software instructions, combined with a hardware module storing multiple sets of offsets, achieves intelligent, flexible, and highly reliable hardware-level redirection of interrupt vector table access under a multi-backup storage architecture. The memory control module can automatically and in real-time select the optimal backup region as the interrupt service source based on the operating status, security policy, or management instructions, and instantly complete address remapping through the pre-stored corresponding offset. This significantly improves the system's adaptability and robustness in handling complex scenarios such as multi-version coexistence, fault recovery, and security isolation without sacrificing interrupt response real-time performance, making critical operations such as firmware upgrades and system rollbacks safer, more flexible, and more reliable.

[0129] To facilitate understanding of the method for obtaining interrupt vector table data provided in this application, the following example illustrates the spatial structure of the memory.

[0130] See Figure 5 This is a schematic diagram of the spatial structure of a memory provided in an embodiment of this application. Figure 5As shown, the spatial structure of this memory may include an offset region and a post-offset region. The offset region is the address region corresponding to the address command issued by the CPU, and the post-offset region is the address region corresponding to the address instruction issued by the CPU after offsetting.

[0131] Based on this, Figure 5 The example also illustrates four registers: the KEY register, the offset enable register, the offset register, and the region partitioning register. When the correct KEY is configured in the register, the configuration enable is unlocked, allowing configuration of the offset enable register and enabling the offset function. When the configured KEY is inconsistent with the set value, the configuration enable is disabled, thus disabling the offset function, and the offset enable register cannot be configured. The offset enable register can be used to enable or disable the offset function. The offset register configures the address offset amount. The region partitioning register stores the start and end addresses of the offset region; its functions are as follows: Configure the start address and end address in the region partitioning register to divide the offset region. When the KEY register is configured and the offset function is enabled, the memory control module determines that the address instruction issued by the CPU is located in the offset region (start address <= storage address of the address instruction <= end address), and then offsets the address instruction issued by the CPU.

[0132] The offset address is the memory address in the address instruction issued by the CPU plus the offset (e.g., if the CPU issues a memory address of 0x100 and an offset of 0x7000, then the offset address is 0x100 + 0x7000 = 0x7100). At this time, the memory controller will send the offset address to the memory, and after obtaining the interrupt vector table data corresponding to the offset address, it will return the interrupt vector table data to the CPU.

[0133] The above method enables secondary address mapping. The CPU still sends the same address corresponding to the interrupt instruction, but the memory controller can return the data of the new interrupt instruction to the CPU. This allows the CPU to receive the new interrupt instruction even after a program upgrade, when the new interrupt instruction is stored in a different region. The CPU still sends the previous address but can still receive the new interrupt instruction. If the address instruction issued by the CPU is not located in the offset region, the memory controller continues to send the CPU's address instruction to the memory, reads the data at the corresponding address, and returns it to the CPU.

[0134] The technical solution provided in this application provides a method for address jumping by modifying the memory control logic that accesses the storage corresponding to the CPU's zero address, thereby solving the problem that some CPUs cannot properly access the interrupt instructions of the upgraded program. This allows for flexible jumping to the address corresponding to the interrupt instruction to obtain a new interrupt instruction for the CPU.

[0135] See Figure 6 This is a block diagram illustrating an embodiment of an interrupt vector table data acquisition device provided in this application. As one embodiment, this device can be applied to a memory control module in a system. The system includes a memory, a central processing unit, and a memory control module. The memory stores the interrupt vector table and, in response to a preset event, moves the storage area of ​​the interrupt vector table from a first storage area to a second storage area. Figure 6 As shown, the device may include: The instruction receiving module 61 is used to receive the address instruction sent by the central processing unit. The address instruction includes the storage address of the interrupt vector table stored in the memory before a preset event occurs. Offset acquisition module 62 is used to acquire the address offset between the first storage area and the second storage area when it is determined that the storage address belongs to the first storage area, and update the storage address according to the address offset to obtain the target storage address; The data acquisition module 63 is used to send the target storage address to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and send the interrupt vector table data to the central processing unit.

[0136] like Figure 7 The diagram shown is a structural schematic of an electronic device according to an embodiment of this application, including a processor 71, a communication interface 72, a memory 73, and a communication bus 74. The processor 71, communication interface 72, and memory 73 communicate with each other via the communication bus 74. Memory 73 is used to store computer programs; In one embodiment of this application, when the processor 71 executes a program stored in the memory 73, it implements the interrupt vector table data acquisition method provided in any of the foregoing method embodiments, including: Receives an address instruction sent by the central processing unit, the address instruction including the storage address of the interrupt vector table stored in the memory before a preset event occurs; If it is determined that the storage address belongs to the first storage area, the address offset between the first storage area and the second storage area is obtained, and the storage address is updated according to the address offset to obtain the target storage address; The target memory address is sent to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and the interrupt vector table data is sent to the central processing unit.

[0137] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the interrupt vector table data acquisition method provided in any of the foregoing method embodiments.

[0138] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0140] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0141] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for obtaining interrupt vector table data, characterized in that, A memory control module is applied in a system, the system including a memory, a central processing unit, and the memory control module, the memory being used to store an interrupt vector table, and in response to a preset event, moving the storage area of ​​the interrupt vector table from a first storage area to a second storage area; the method includes: Receives an address instruction sent by the central processing unit, the address instruction including the storage address of the interrupt vector table stored in the memory before a preset event occurs; If it is determined that the storage address belongs to the first storage area, the address offset between the first storage area and the second storage area is obtained, and the storage address is updated according to the address offset to obtain the target storage address; The target memory address is sent to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and the interrupt vector table data is sent to the central processing unit.

2. The method according to claim 1, characterized in that, Before receiving the address instruction sent by the central processing unit, the method further includes: In response to the key sent by the central processing unit, the key is verified; If the key verification is successful, the first storage address of the first storage area and the second storage address of the second storage area are determined respectively, and the first storage address and the second storage address are stored in the preset area information storage module; Based on the first storage address and the second storage address, determine the address offset between the first storage area and the second storage area, and store the address offset in a preset offset storage module; The offset function is enabled. This function indicates whether, upon receiving an address instruction from the central processing unit (CPU), the storage address in the address instruction belongs to the first storage region. If the storage address belongs to the first storage region, the address offset between the first storage region and the second storage region is obtained, and the storage address is updated based on the address offset to obtain the target storage address. The target storage address is then sent to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and the interrupt vector table data is sent to the CPU.

3. The method according to claim 2, characterized in that, The verification of the key includes: The key is input into a preset key storage module so that the key storage module can determine whether the key is consistent with the preset key; If the key is determined to be consistent with the preset key through the key storage module, the key verification is deemed successful. If the key storage module determines that the key is inconsistent with the preset key, the key verification fails.

4. The method according to claim 2, characterized in that, If it is determined that the key verification fails, the method further includes: Upon receiving an address instruction from the central processing unit, the storage address included in the address instruction is sent to the memory to obtain the data stored at the storage address, and the data is then sent to the central processing unit.

5. The method according to claim 2, characterized in that, The first storage address includes the first start address and the first end address of the first storage area, and the second storage address includes the second start address and the second end address of the second storage area; Determining the address offset between the first storage region and the second storage region based on the first storage address and the second storage address includes: Subtracting the first starting address from the second starting address yields the address offset between the first storage region and the second storage region. or, Subtracting the first terminal address from the second terminal address yields the address offset between the first storage area and the second storage area.

6. The method according to claim 2, characterized in that, The first storage address includes the first start address and the first end address of the first storage region; The step of determining that the storage address belongs to the first storage region includes Determine whether the storage address is greater than or equal to the first starting address and less than or equal to the first ending address; If the storage address is determined to be greater than or equal to the first starting address and less than or equal to the first ending address, then the storage address is determined to belong to the first storage region.

7. The method according to claim 2, characterized in that, The step of obtaining the address offset between the first storage region and the second storage region includes: Obtain the address offset between the first storage area and the second storage area from the offset storage module.

8. The method according to claim 2, characterized in that, The memory includes multiple different second storage areas, and the offset storage module is used to store multiple preset address offsets, each address offset corresponding to a second storage area; The step of obtaining the address offset between the first storage region and the second storage region includes: Determine the target second storage area based on preset rules or received area selection instructions; Determine the target address offset corresponding to the target second storage area from the offset storage module; The target address offset is determined as the address offset between the first storage area and the second storage area.

9. The method according to claim 1, characterized in that, The step of updating the storage address based on the address offset to obtain the target storage address includes: The target storage address is obtained by adding the storage address to the address offset.

10. The method according to claim 1, characterized in that, If it is determined that the storage address does not belong to the first storage region, the method further includes: The storage address is sent to the memory to obtain the data stored at the storage address, and the data is then sent to the central processing unit.

11. A device for acquiring interrupt vector table data, characterized in that, A memory control module is applied in a system, the system including a memory, a central processing unit, and the memory control module, the memory being used to store an interrupt vector table, and responding to a preset event to move the storage area of ​​the interrupt vector table from a first storage area to a second storage area; the device includes: The instruction receiving module is used to receive address instructions sent by the central processing unit. The address instructions include the storage address of the interrupt vector table stored in the memory before a preset event occurs. The offset acquisition module is used to acquire the address offset between the first storage area and the second storage area when it is determined that the storage address belongs to the first storage area, and update the storage address according to the address offset to obtain the target storage address; The data acquisition module is used to send the target storage address to the memory to obtain the interrupt vector table data stored in the interrupt vector table, and send the interrupt vector table data to the central processing unit.

12. An electronic device, characterized in that, include: The system includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory is used to store computer programs; and the processor, when executing the computer program, implements the method for obtaining interrupt vector table data as described in any one of claims 1-10.

13. A storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the method for obtaining interrupt vector table data as described in any one of claims 1-10.

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