A reconfigurable baseband processing SoC architecture based on a RISC-V extended instruction set and an instruction control method thereof

The reconfigurable baseband processing SoC architecture using the RISC-V extended instruction set solves the problems of traditional architectures being unable to adapt to new communication protocols and having low data transfer efficiency, achieving efficient and flexible baseband signal processing to meet the energy efficiency and real-time requirements of 5G communication systems.

CN122152759APending Publication Date: 2026-06-05GUANGDONG COMM & NETWORKS INST +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
GUANGDONG COMM & NETWORKS INST
Filing Date
2025-12-09
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

Existing technologies in 5G communication systems suffer from several problems: traditional fixed instruction set architectures cannot adapt to the rapid evolution of new communication protocols; data transfer efficiency is low in heterogeneous computing systems; and dynamic reconfigurability and high energy efficiency are difficult to balance.

Method used

It adopts a reconfigurable baseband processing SoC architecture based on the RISC-V extended instruction set. Through modular design, it integrates scalar processing, vector computing and dedicated acceleration. Combined with a dynamic voltage and frequency adjustment system, it realizes instruction set expansion and heterogeneous computing, and supports flexible processing of multiple communication protocols.

Benefits of technology

It improves protocol adaptability and processing efficiency, reduces data transmission time overhead, optimizes power consumption, meets the real-time requirements of communication systems, and provides high performance and good energy efficiency.

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Abstract

The present application relates to a kind of reconfigurable baseband processing SoC architecture based on RISC-V extension instruction set and its instruction control method, belong to communication chip and processor design technical field.For the instruction set flexibility insufficient, data handling inefficiency and dynamic reconfiguration and high energy efficiency difficult to consider of existing 5G / 6G baseband processor, the present application proposes a kind of heterogeneous computing architecture, including the RISC-V processor core cluster of supporting RV64IMAFDCV instruction set, extension instruction execution unit, vector coprocessor and reconfigurable hardware acceleration module group.By adding special instructions such as complex matrix multiplication, optimizing data path design, using double buffering mechanism and hierarchical reconfigurable technology, efficient execution of baseband processing is realized.At the same time, dynamic voltage frequency regulation system can adjust power supply parameters in real time according to work load.The scheme significantly improves the performance and energy efficiency of baseband processing, and is suitable for physical layer signal processing of 5G / 6G communication system.
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