Multifunctional integrated interposer and optoelectronic co-package module

Abstract

The application discloses a multifunctional integrated interposer and a photoelectricity collaborative packaging module, and belongs to the technical field of integrated circuits.The multifunctional integrated interposer is characterized in that a first embedded interconnection unit of an integrated super-high-density and super-low-loss physical wiring channel circuit and a second embedded interconnection unit with photoelectric conversion function are co-planarly embedded in a dielectric body, and the upper surfaces of the two units are flush with the upper surface of the dielectric body, thereby realizing high integration of the two functional units in structure, effectively shortening the interconnection path of high-speed electrical signals and optical signals between chips, and reducing transmission loss and delay.The embedded physical wiring channel circuit can directly provide super-high-speed physical signal direct through in the first embedded interconnection unit, and the USR super-high-speed interface protocol processing function is transferred to an acceleration computing core, thereby significantly improving signal integrity, saving external special DSP chips, and simplifying system architecture, reducing overall power consumption and packaging complexity.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to multifunctional integrated interposers and optoelectronic co-packaging modules. Background Technology

[0002] With the rapid development of AI computing power and high-speed optical communication technology, extreme requirements have been placed on the integration, transmission rate, and thermal management of chip packaging, making integrated optoelectronic computing co-packaging an inevitable trend. However, current advanced packaging technologies still have significant shortcomings: First, in terms of structural integration, existing solutions mostly adopt discrete designs such as separate embedding of silicon bridges, separate embedding of PICs, or mounting of both on the same layer, failing to achieve coplanar embedding of silicon bridges and PICs within the same interposer layer. This results in long interconnect paths, low integration, and often requires complex processes (such as two-step molding), increasing losses and costs. Second, in terms of high-speed interconnects, existing electronic integrated circuits (EICs) and accelerated computing chips (AI chips) mostly transmit data through long-distance, low-density, high-loss electrical interconnect paths on organic substrates. To compensate for signal attenuation and distortion caused by long-distance transmission, the system usually relies on an external dedicated digital signal processor (DSP) for protocol conversion, equalization, and error correction. This not only increases system complexity and power consumption but also becomes a core bottleneck for supporting ultra-high-speed transmission of 224Gbps PAM4 and above, severely restricting overall bandwidth and energy efficiency. Furthermore, in terms of system integration, the existing packaging structure makes it difficult to achieve integrated and coordinated layout of PIC, EIC, AI chips and silicon bridges. The arrangement of each component is not entirely reasonable, which can easily lead to signal crosstalk and thermal interference. Summary of the Invention

[0003] To address the problems existing in current optoelectronic co-packaging technologies, such as low integration density of silicon bridges and photonic integrated chips (PICs), reliance on external modules for high-speed interface protocol processing, limited transmission rates, and unreasonable multi-chip collaborative layout, this paper proposes a multi-functional integrated interposer and optoelectronic co-packaging module. This module aims to achieve coplanar embedding of silicon bridges and PICs, significantly shorten interconnection paths, and improve integration density. The silicon bridge serves as an ultra-high-density, ultra-low-loss physical wiring channel circuit. The ultra-high-speed interface protocol processing function of the USR is fully integrated inside the accelerated computing chip, enabling signal pass-through and efficient transmission. This module optimizes the integrated layout of electronic integrated chips (EICs), accelerated computing chips, and PICs.

[0004] This application provides a multifunctional integrated intermediary layer, including:

[0005] Dielectric body;

[0006] The first embedded interconnect unit and the second embedded interconnect unit are embedded inside the dielectric body, and their upper surfaces are flush with the upper surface of the dielectric body; wherein, the first embedded interconnect unit integrates a physical wiring channel circuit, and the second embedded interconnect unit is configured to perform the conversion between optical signals and electrical signals; the first embedded interconnect unit and the second embedded interconnect unit are staggered in the horizontal direction and isolated from each other;

[0007] A rewiring structure is formed on the dielectric body to realize electrical connection between the first embedded interconnect unit, the second embedded interconnect unit and the external chip disposed on the surface of the dielectric body.

[0008] Optionally, the first embedded interconnect unit is a silicon bridge, and the second embedded interconnect unit is a photonic integrated chip.

[0009] Optionally, the dielectric body is an organic material interlayer or a glass interlayer; when the dielectric body is an organic material interlayer, its material is modified epoxy resin; when the dielectric body is a glass interlayer, its material is glass.

[0010] Optionally, the redistribution structure includes multiple layers of metal traces with a line width and spacing of less than or equal to 10 μm, and the interlayer dielectric material of the redistribution structure includes polyimide or benzocyclobutene.

[0011] Optionally, the horizontal spacing between the silicon bridge and the photonic integrated chip is 50 μm to 500 μm; the thickness of the silicon bridge is 30 μm to 150 μm, and the thickness of the photonic integrated chip is 100 μm to 300 μm.

[0012] Optionally, the physical wiring channel circuit supports physical signal pass-through transmission in PAM4 modulation format with a rate greater than or equal to 224Gbps.

[0013] This application also provides an optoelectronic co-packaging module, including:

[0014] The aforementioned multi-functional integrated intermediary layer;

[0015] An electronic integrated chip and an accelerated computing chip are disposed on the upper surface of the multifunctional integrated interposer layer. The accelerated computing chip is electrically connected to the first embedded interconnect unit through the rewiring structure, and the accelerated computing chip integrates an interface protocol processing circuit. The electronic integrated chip is electrically connected to the first embedded interconnect unit and the second embedded interconnect unit through the rewiring structure.

[0016] The fiber array unit (FAU) is optically coupled to the second embedded interconnect unit;

[0017] The lower surface of the multifunctional integrated interposer layer has interconnect bumps for connecting to an external substrate.

[0018] Optionally, the electronic integrated chip overlaps with the photonic integrated chip, which serves as the second embedded interconnect unit, in the vertical projection, with an overlap area width of 0.5 mm to 3 mm; the accelerated computing chip overlaps with the silicon bridge portion, which serves as the first embedded interconnect unit, in the vertical projection, with an overlap area width of 0.8 mm to 3 mm.

[0019] Optionally, the width of the electronic integrated chip is 2 mm to 6 mm and the thickness is 50 μm to 150 μm; the gap between the electronic integrated chip and the photonic integrated chip is filled with underfill adhesive.

[0020] Optionally, the interconnect bumps are solder bumps; the fiber array unit is disposed on the side or above the second embedded interconnect unit and coupled to the optical port of the second embedded interconnect unit.

[0021] The beneficial effects of the above technical solution are as follows:

[0022] The multifunctional integrated interposer of this application achieves a high degree of structural integration of the two functional units by coplanarly embedding a first embedded interconnect unit with integrated physical wiring channel circuitry and a second embedded interconnect unit with photoelectric conversion function inside the dielectric body, with their upper surfaces flush with the upper surface of the dielectric body. This effectively shortens the interconnection path of high-speed electrical and optical signals between chips, reducing transmission loss and delay. The staggered distribution and mutual isolation of the two units in the horizontal direction effectively constructs a physical barrier for heat and electricity, significantly reducing the impact of heat generated by silicon-based wiring units and high-speed electrical signals on temperature- and interference-sensitive optoelectronic devices, ensuring the performance stability of photonic integrated chips and the integrity of system signals. The embedded ultra-high density, ultra-low loss physical wiring channels provide excellent electrical performance for data transmission between chips, significantly reducing signal transmission loss and delay. The rewiring structure formed on the dielectric body provides high-density, high-precision electrical interconnection between embedded units and various surface-mount functional chips, enhancing the flexibility and reliability of the packaging structure. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 This is a cross-sectional schematic diagram of one embodiment of the multifunctional integrated intermediary layer described in this application;

[0025] Figure 2 This is a cross-sectional schematic diagram of one embodiment of the optoelectronic co-packaging module described in this application. Detailed Implementation

[0026] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0028] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0030] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0031] The following terms are used in this document:

[0032] Silicon bridge: A silicon-based bare chip with an embedded high-density interconnect structure, used to achieve short-distance, high-speed, high-bandwidth connections between two or more chips;

[0033] PIC (phonic integrated circuit): a photonic integrated chip;

[0034] Interposer: In advanced packaging, it is an intermediate intermediary layer placed between the die and the substrate to achieve high-density, short-distance, high-speed interconnection between multiple chips;

[0035] EIC (Electronic Integrated Circuit): Electronic integrated chip;

[0036] FAU (Fiber Array Unit): A fiber array unit is a precision passive optical device that arranges multiple single-mode / multimode optical fibers with micron-level precision and fixes them on a V-groove or grating substrate to achieve high-density, low-loss optical coupling between the PIC and the external fiber optic link.

[0037] PSPI (Photosensitive Polyimide): Photosensitive polyimide;

[0038] BCB (Benzocyclobutene): Benzocyclobutene;

[0039] PI (Polyimide): Polyimide;

[0040] USR (Ultra Short Reach) is a physical layer interface standard developed by the Optical Interconnect Networking Forum (OIF) for ultra-short-distance (typically between chips or within boards) ultra-high-speed electrical signal interconnection, designed to support data transmission rates of 224 Gbps and above.

[0041] DSP (Digital Signal Processor): A microprocessor specifically designed for the rapid processing of digital signals (such as audio, video, and communication data).

[0042] FOWLP (Fan-Out Wafer Level Packaging): Fan-out wafer-level packaging;

[0043] FOPLP (Fan-Out Panel Level Packaging): Fan-out panel-level packaging;

[0044] CoPoS (Chip on Polymer on Substrate): Chip-polymer-substrate packaging.

[0045] AI Chiplet: Accelerated computing chip.

[0046] like Figure 1 As shown, this application provides a multifunctional integrated intermediary layer including:

[0047] Dielectric body 1;

[0048] The first embedded interconnect unit 2 and the second embedded interconnect unit 3 are embedded inside the dielectric body 1, and their upper surfaces are flush with the upper surface of the dielectric body 1; wherein, the first embedded interconnect unit 2 integrates an ultra-high density, ultra-low loss physical wiring channel circuit, and the second embedded interconnect unit 3 is configured to perform the conversion between optical signals and electrical signals; the first embedded interconnect unit 2 and the second embedded interconnect unit 3 are staggered in the horizontal direction and are effectively thermally and electrically isolated from each other;

[0049] A rewiring structure 4 is formed on the dielectric body 1 to realize electrical connection between the first embedded interconnect unit 2, the second embedded interconnect unit 3 and the external chip disposed on the surface of the dielectric body 1.

[0050] In this embodiment, the multifunctional integrated interposer layer achieves a high degree of structural integration of the two functional units by coplanarly embedding the first embedded interconnect unit 2, which integrates ultra-high density and ultra-low loss physical wiring channels, and the second embedded interconnect unit 3, which has photoelectric conversion function, inside the dielectric body 1, with their upper surfaces flush with the upper surface of the dielectric body 1. This effectively shortens the interconnection path of high-speed electrical and optical signals between chips, reducing transmission loss and delay. The staggered distribution and mutual isolation of the two units in the horizontal direction effectively constructs a physical barrier for heat and electricity, significantly reducing the impact of heat generated by silicon-based wiring units and high-speed electrical signals on temperature- and interference-sensitive optoelectronic devices, ensuring the performance stability of photonic integrated chips and the integrity of system signals. The embedded ultra-high density and ultra-low loss physical wiring channels provide excellent electrical performance for data transmission between chips, greatly reducing signal transmission loss and delay. The rewiring structure 4 formed on the dielectric body 1 provides high-density and high-precision electrical interconnection between embedded units and various surface-mounted functional chips, enhancing the flexibility and reliability of the packaging structure. This interposer provides a highly integrated and high-performance core foundation for optoelectronic computing integrated packaging that supports ultra-high-speed transmission of 224Gbps PAM4 and above.

[0051] In an optional embodiment, the first embedded interconnect unit 2 is a silicon bridge, and the second embedded interconnect unit 3 is a photonic integrated chip.

[0052] In this embodiment, the silicon bridge and the photonic integrated chip adopt a horizontally staggered and mutually isolated layout structure. This physical isolation creates an effective thermal buffer between the heat generated by the silicon bridge during operation and the working area of ​​the photonic integrated chip, significantly reducing the direct thermal interference caused by the high-temperature computing unit to the temperature-sensitive optical components, thereby ensuring the wavelength stability and photoelectric conversion efficiency of the photonic integrated chip. Simultaneously, the staggered isolation avoids the close spatial arrangement of the high-speed digital signals of the silicon bridge and the sensitive analog optoelectronic devices of the photonic integrated chip, reducing potential electromagnetic coupling and signal crosstalk between them from a physical structure perspective, and improving the signal integrity of the overall system. Furthermore, this layout provides independent and ample vertical interconnect and fan-out space for the redistribution layers above each other, simplifying the complexity of high-density wiring and facilitating better stress management in the packaging process.

[0053] In an optional embodiment, the dielectric body 1 is an organic material interlayer or a glass interlayer; when the dielectric body 1 is an organic material interlayer, its material is modified epoxy resin; when the dielectric body 1 is a glass interlayer, its material is glass. The thickness of the dielectric body 1 is 150~500μm.

[0054] In this embodiment, the dielectric body 1 is an organic material interlayer or a glass interlayer, which possesses excellent insulation, thermal conductivity, and moldability, providing a reliable physical support and electrical isolation foundation for the entire multifunctional integrated interlayer. When a modified epoxy resin organic material is selected, its good process compatibility and mechanical toughness make it more feasible to fabricate complex multilayer high-density redistribution structures 4 on its surface. At the same time, by adjusting the material formulation, its coefficient of thermal expansion can be optimized, thereby significantly enhancing the thermomechanical matching between the interlayer and the embedded silicon bridge, photonic integrated chip, and surface mount chip, improving the long-term reliability of the package under temperature changes. When a glass material is selected, its inherent excellent surface flatness and extremely low dimensional thermal expansion rate provide a near-ideal substrate for fabricating ultra-fine redistribution lines with a linewidth / spacing of less than or equal to 10 micrometers, ensuring extremely high-precision patterning and interconnect alignment. Meanwhile, the moderate thermal conductivity and excellent insulation properties of the glass material itself not only help to dissipate the heat generated by the embedded units more evenly, but also further enhance the electrical isolation between high-speed signal lines, effectively suppressing signal crosstalk. These two material systems provide a practical technical approach to balancing packaging performance, manufacturing cost, and process difficulty.

[0055] In this embodiment, the thickness of the dielectric body 1 is between 150 μm and 500 μm. This thickness ensures sufficient mechanical strength to support the embedded cells and surface-mount chips while effectively controlling the overall package thickness, meeting the requirements for thinner and lighter designs. This thickness provides a stable embedding depth and lateral support for the embedded silicon bridge and photonic integrated chip, ensuring that their upper surfaces are reliably flush with the upper surface of the dielectric body 1, laying the foundation for subsequent fabrication of a high-flatness redistribution layer and chip mounting. Furthermore, this moderate thickness facilitates the formation of a controllable dielectric environment, allowing adjustment of high-frequency signal transmission characteristics (such as characteristic impedance), and serves as one of the main heat conduction paths, effectively guiding heat from the embedded cells to the external substrate without excessively increasing thermal resistance. This thickness parameter is well-matched with the processing characteristics of the selected organic or glass material, ensuring high yield rates for critical processes such as grinding and polishing during mass production.

[0056] In an optional embodiment, the redistribution structure 4 includes multilayer metal traces 41 with a line width and spacing of less than or equal to 10 μm, and the interlayer dielectric material of the redistribution structure 4 includes polyimide or benzocyclobutene.

[0057] In this embodiment, the redistribution structure 4 achieves ultra-high density interconnection capabilities by employing multilayer metal traces with linewidth and spacing both less than or equal to 10 micrometers. This significantly increases the number of wiring channels per unit area, meeting the growing demand for high-speed, high-bandwidth interconnections between electronic integrated chips, accelerator computing chips 5, silicon bridges, and photonic integrated chips, and providing a foundation for achieving more compact package sizes. The interlayer dielectric is selected from polyimide (PI) or benzocyclobutene (BCB) materials. These two polymer materials possess excellent dielectric properties, good mechanical flexibility, and high adhesion to metal conductors. They effectively reduce parasitic capacitance and signal crosstalk between wirings, improving the integrity of high-frequency signal transmission. Simultaneously, their planarization characteristics and thermal stability ensure the reliability of the multilayer redistribution structure 4 during manufacturing and long-term use.

[0058] In an optional embodiment, the horizontal spacing between the silicon bridge and the photonic integrated chip is 50 μm to 500 μm; the thickness of the silicon bridge is 30 μm to 150 μm, and the thickness of the photonic integrated chip is 100 μm to 300 μm.

[0059] In this embodiment, the spacing between the silicon bridge and the photonic integrated chip is limited to the range of 50μm to 500μm. This spacing ensures electrical and thermal isolation between the two while providing ample space for fan-out routing of the redistribution layer, avoiding congestion and short-circuit risks associated with high-density wiring in narrow areas, thereby ensuring interconnect reliability. The silicon bridge thickness is 30μm to 150μm, and the photonic integrated chip thickness is 100μm to 300μm. This thickness range allows for stable coplanar embedding with the dielectric body 1, and the flush upper surface facilitates subsequent wafer-level or panel-level processing. This thickness matching helps control the overall thickness and warpage of the package module, optimizes thermal stress distribution, and ensures robust microbump or hybrid bonding connections with the surface-mount electronic integrated chip.

[0060] In an optional embodiment, the physical wiring channel circuit supports physical signal pass-through transmission in PAM4 modulation format with a rate greater than or equal to 224Gbps.

[0061] In this embodiment, the physical wiring channel circuit embedded in the silicon bridge is configured to provide direct physical signal transmission in PAM4 modulation format at a rate greater than or equal to 224Gbps. This capability directly meets the core requirements of next-generation data centers and high-performance computing for ultra-high-speed electrical interconnects, significantly increases the upper limit of bandwidth for data interaction between electronic integration chips and accelerated computing chips, and ensures signal integrity at extremely high data rates.

[0062] In a preferred embodiment, the integrated interface protocol processing circuit embedded within the accelerated computing chip is specifically used to implement and process the USR ultra-high-speed interface protocol. This achieves front-end and localized signal processing, eliminating the reliance on external independent DSP chips. This not only significantly reduces system power consumption and transmission latency but also effectively suppresses signal attenuation and reflection by shortening the high-speed signal path. The USR-based ultra-high-speed physical interface has the advantages of higher bandwidth, lower latency, and lower bit error rate, and can adapt to the optical interconnect requirements of 224Gbps, 800G / 1.6T, and above, meeting the core requirements of AI computing power for high bandwidth and low latency. The USR protocol is embedded in the accelerated computing chip, and the silicon bridge physical signal direct transmission design, combined with the high-density rewiring of the interposer layer, forms a dual guarantee of "protocol unification" and "precise wiring," further amplifying the advantages of high-speed transmission, effectively reducing transmission loss and interference, and comprehensively improving the interconnection efficiency and reliability of the package structure.

[0063] like Figure 2 As shown, this application provides an optoelectronic co-packaging module, including:

[0064] The aforementioned multi-functional integrated intermediary layer;

[0065] The electronic integrated chip 6 and the accelerated computing chip 5 are disposed on the upper surface of the multifunctional integrated interposer layer. The accelerated computing chip 5 is electrically connected to the first embedded interconnect unit 2 through the rewiring structure 4, and the accelerated computing chip 5 integrates a complete USR ultra-high-speed interface protocol processing circuit. The electronic integrated chip 6 is electrically connected to the first embedded interconnect unit 2 and the second embedded interconnect unit 3 through the rewiring structure 4 to undertake analog signal driving and amplification functions. The electronic integrated chip 6 and the accelerated computing chip 5 are responsible for some or all of the data interaction between them through the physical wiring channel circuit.

[0066] Fiber optic array unit 7 is optically coupled to the second embedded interconnect unit 3;

[0067] The lower surface of the multifunctional integrated interposer layer is formed with interconnect bumps 8 for connecting to an external substrate.

[0068] In this embodiment, the optoelectronic co-packaging module achieves three-dimensional tight integration of computing, electrical interconnection, and optical interconnection functions through a multi-functional integrated intermediary layer. Specifically, the physical wiring channel circuit embedded in the silicon bridge enables direct physical signal transmission between the electronic integrated chip 6 and the accelerated computing chip 5; the accelerated computing chip 5 embeds a USR ultra-high-speed interface protocol circuit, directly processing all high-speed protocol interactions generated by the electronic integrated chip 6. This localizes key high-speed signal processing functions within the accelerated computing chip 5, and through the ultra-high density, ultra-low loss physical signal direct transmission of the silicon bridge, not only significantly reduces data transmission latency and power consumption, but also eliminates the need for the electronic integrated chip 6 and the accelerated computing chip 5 to integrate complex protocol physical layers, effectively simplifying their internal architecture. The electronic integrated chip 6 connects the silicon bridge and the photonic integrated chip simultaneously through the rewiring structure 4, collaboratively managing the computing data flow and optoelectronic conversion. The optical coupling between the fiber array unit 7 and the photonic integrated chip provides high-bandwidth optical I / O for the module, while the solder bumps on the lower surface constitute a standard, reliable external electrical interconnect interface. This module ultimately constructs a highly collaborative and efficient optoelectronic computing fusion system within a single package.

[0069] In this embodiment, the metal bonding gap between the electronic integrated chip 6 and the photonic integrated chip is filled with a modified thermally insulating underfill adhesive. This adhesive material, while possessing excellent adhesive strength and stress buffering capabilities, has significantly improved thermal resistance characteristics through formulation modification. This characteristic effectively prevents the heat generated by the electronic integrated chip 6 during operation from being directly conducted to the temperature-sensitive photonic integrated chip, thereby maintaining the operating temperature of the photonic integrated chip in a more stable and lower range, ensuring the stability of its key optical performance characteristics such as laser wavelength and modulator efficiency. Simultaneously, the adhesive can still reliably bond the two chips and absorb mechanical stress caused by thermal mismatch, protecting interconnect structures such as microbumps from fatigue damage and ensuring the long-term reliability of the electrical interconnects. This solution synergistically achieves both thermal isolation and mechanical protection functions in a single material, which is a key measure to improve the overall performance and lifespan of the optoelectronic co-packaging module.

[0070] In an optional embodiment, the electronic integrated chip 6 overlaps with the photonic integrated chip portion serving as the second embedded interconnect unit 3 in vertical projection, with an overlap area width of 0.5 mm to 3 mm; the accelerated computing chip 5 overlaps with the silicon bridge portion serving as the first embedded interconnect unit 2 in vertical projection, with an overlap area width of 0.8 mm to 3 mm.

[0071] In this embodiment, the electronic integrated chip 6 overlaps with the photonic integrated chip in vertical projection by 0.5mm to 3mm. This layout allows for a high-speed electrical interconnection between the two through the shortest path vertical connection via the rewiring structure 4 within the overlapping area, significantly shortening the signal transmission distance and effectively reducing interconnect parasitic parameters and signal transmission delay. The accelerated computing chip 5 overlaps with the silicon bridge in vertical projection by 0.8mm to 3mm, ensuring the most direct and compact key data path between the computing unit and the protocol processing unit. High-speed physical signal pass-through is achieved through the physical wiring channel circuit integrated within the silicon bridge, significantly improving data exchange efficiency and reducing power consumption. This optimized overlapping layout not only enhances the electrical performance and thermal coupling efficiency between functional units but also makes the overall packaging structure more compact, improving system integration and reliability.

[0072] In an optional embodiment, the electronic integrated chip 6 has a width of 2 mm to 6 mm and a thickness of 50 μm to 150 μm; the gap between the electronic integrated chip 6 and the photonic integrated chip is filled with underfill adhesive.

[0073] In this embodiment, the electronic integrated chip 6 has a width of 2mm to 6mm and a thickness of 50μm to 150μm. This size range allows for efficient spatial arrangement within the package, forming a compact layout together with the photonic integrated chip and the accelerator computing chip 5, which is beneficial for controlling the overall size of the packaged module. The smaller chip thickness significantly reduces the vertical stacking height of the module, providing greater flexibility for system integration. An underfill adhesive is filled in the gap between the electronic integrated chip 6 and the photonic integrated chip. This adhesive material firmly bonds the two chips and the underlying interposer surface. This filling structure effectively disperses and absorbs stress caused by the mismatch in thermal expansion coefficients between materials, significantly enhancing the mechanical reliability of the interconnect microbumps 8 or hybrid bonding points, and preventing cracking failure due to thermal cycling fatigue. Simultaneously, the underfill adhesive also forms an additional heat dissipation path, helping to more evenly dissipate the heat generated during chip operation, improving the heat dissipation performance of local hot spots, thereby enhancing the long-term operational stability and lifespan of the packaged module.

[0074] In an optional embodiment, the interconnect bump 8 is a solder bump; the fiber array unit 7 is disposed on the side or above the second embedded interconnect unit 3 and coupled to the optical port of the second embedded interconnect unit 3.

[0075] In this embodiment, the interconnect bumps 8 are solder bumps, which possess excellent manufacturability, electrical connectivity, and mechanical compliance. They can effectively adapt to and absorb the stress caused by the difference in thermal expansion coefficients between the multifunctional integrated interposer and the external PCB substrate, ensuring the long-term connection reliability of the package module under temperature cycling and providing a standardized external electrical interface. The fiber array unit 7 is disposed on the side or top surface of the photonic integrated chip and is directly optically aligned and coupled to the optical ports on the chip. This arrangement provides the shortest and most direct physical path for optical signal input / output, minimizing the complexity of optical path alignment and the transmission loss of optical signals in free space or waveguides. Simultaneously, its non-embedded structure avoids interference with the photonic integrated chip's own process and performance, enhancing the modularity and maintainability of the optical interconnect. These two features together improve the engineering practicality and environmental adaptability of the entire optoelectronic co-packaging module.

[0076] The optoelectronic co-packaging module of this embodiment solves the problems of large thermal interference between silicon bridges and photonic integrated chips, complex interfaces of each computing chip, insufficient interconnect performance of the interposer layer, and low high-speed signal transmission efficiency in the prior art. It achieves physical isolation and collaborative management of thermal, electrical, and optical signals by embedding a silicon bridge with ultra-high density, ultra-low loss physical wiring channel circuitry coplanarly with the photonic integrated chip in the same dielectric body 1 and adopting an optimized three-dimensional stacking layout. This structure concentrates high-speed protocol interaction functions on the accelerated computing chip 5, significantly improving data transmission efficiency and energy efficiency. The module uses single-sided bonding and solder bump interconnects, featuring high integration and high bandwidth characteristics, adapting to the advanced board-level packaging requirements of AI computing chips. It can be widely used in advanced packaging scenarios such as FOWLP, FOPLP, and CoPoS, ultimately achieving a synergistic improvement in packaging integration, interconnect efficiency, thermal management, and ultra-high-speed transmission capabilities.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A multifunctional integrated intermediary layer, characterized in that, include: Dielectric body; The first embedded interconnect unit and the second embedded interconnect unit are embedded inside the dielectric body, and their upper surfaces are flush with the upper surface of the dielectric body; wherein, the first embedded interconnect unit integrates a physical wiring channel circuit, and the second embedded interconnect unit is configured to perform the conversion between optical signals and electrical signals; the first embedded interconnect unit and the second embedded interconnect unit are staggered in the horizontal direction and isolated from each other; A rewiring structure is formed on the dielectric body to realize electrical connection between the first embedded interconnect unit, the second embedded interconnect unit and the external chip disposed on the surface of the dielectric body.

2. The multifunctional integrated intermediary layer according to claim 1, characterized in that, The first embedded interconnect unit is a silicon bridge, and the second embedded interconnect unit is a photonic integrated chip.

3. The multifunctional integrated intermediary layer according to claim 1, characterized in that, The dielectric body is an organic material interlayer or a glass interlayer; when the dielectric body is an organic material interlayer, its material is modified epoxy resin; when the dielectric body is a glass interlayer, its material is glass.

4. The multifunctional integrated intermediary layer according to claim 1, characterized in that, The rewiring structure includes multiple layers of metal traces, with a line width and line spacing of less than or equal to 10 μm. The interlayer dielectric material of the rewiring structure includes polyimide or benzocyclobutene.

5. The multifunctional integrated intermediary layer according to claim 2, characterized in that, The horizontal spacing between the silicon bridge and the photonic integrated chip is 50 μm to 500 μm; the thickness of the silicon bridge is 30 μm to 150 μm, and the thickness of the photonic integrated chip is 100 μm to 300 μm.

6. The multifunctional integrated intermediary layer according to any one of claims 1-5, characterized in that, The physical wiring channel circuit supports direct transmission of physical signals in PAM4 modulation format with a rate greater than or equal to 224Gbps.

7. A photoelectric co-packaging module, characterized in that, include: A multi-functional integrated intermediary layer as described in any one of claims 1-6; An electronic integrated chip and an accelerated computing chip are disposed on the upper surface of the multifunctional integrated interposer layer. The accelerated computing chip is electrically connected to the first embedded interconnect unit through the rewiring structure, and the accelerated computing chip integrates an interface protocol processing circuit. The electronic integrated chip is electrically connected to the first embedded interconnect unit and the second embedded interconnect unit through the rewiring structure. The fiber optic array unit is optically coupled to the second embedded interconnect unit; The lower surface of the multifunctional integrated interposer layer has interconnect bumps for connecting to an external substrate.

8. The optoelectronic co-packaging module according to claim 7, characterized in that, The electronic integrated chip overlaps with the photonic integrated chip, which serves as the second embedded interconnect unit, in the vertical projection, with an overlap area width of 0.5 mm to 3 mm; the accelerated computing chip overlaps with the silicon bridge portion, which serves as the first embedded interconnect unit, in the vertical projection, with an overlap area width of 0.8 mm to 3 mm.

9. The optoelectronic co-packaging module according to claim 8, characterized in that, The width of the electronic integrated chip is 2mm to 6mm and the thickness is 50μm to 150μm; the gap between the electronic integrated chip and the photonic integrated chip is filled with bottom filler adhesive.

10. The optoelectronic co-packaging module according to claim 7, characterized in that, The interconnect bumps are solder bumps; the fiber array unit is disposed on the side or above the second embedded interconnect unit and coupled to the optical port of the second embedded interconnect unit.

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