N-type lateral double-diffused mos field effect transistor and method for manufacturing the same

Abstract

The present invention provides an N-type lateral double-diffused MOS field-effect transistor and its fabrication method. By setting a second heavily doped region and a third heavily doped region within the substrate, located in the second well region and connected to the cathode, a bidirectional N-P-N-P-N structure is formed. This achieves bidirectional ESD protection through a simple structure without the need for additional ESD protection devices. Thus, it balances ESD protection effectiveness with improved integration density. Furthermore, by setting an N-type first well region and a first heavily doped region, with the first heavily doped region located within the first well region and extending into the second well region, a shallow junction of N-type doped / P-type well is formed, significantly reducing the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to an N-type lateral double-diffused MOS field-effect transistor and its fabrication method. Background Technology

[0002] The Bipolar-CMOS-DMOS (BCD) process integrates three different manufacturing technologies on a single chip: bipolar transistors for high-precision analog signal processing, CMOS for designing digital control circuits, and Discrete Metal Oxide Semiconductor (DMOS) devices for developing power supplies and high-voltage switching devices. DMOS devices primarily include two types: Vertical Double-Diffused MOSFETs (VDMOS) and Lateral Double-Diffused MOSFETs (LDMOS).

[0003] Existing N-type lateral double-diffused MOSFETs achieve bidirectional ESD protection for a single N-type lateral double-diffused MOSFET by improving the heavily doped region within the well region connected to the cathode, without requiring additional ESD protection devices. However, in practical applications, this approach suffers from an excessively high trigger voltage, leading to protection failure for low-voltage sensitive circuits. Summary of the Invention

[0004] The technical problem solved by this invention is how to reduce the trigger voltage of the device while taking into account both ESD protection effect and improving device integration.

[0005] To solve the above-mentioned technical problems, a first aspect of the present invention provides an N-type lateral double-diffused MOS field-effect transistor, comprising: A substrate, wherein a buried layer is provided on the surface region of the substrate; A body region, a first well region, and a second well region are located on the buried layer along a direction parallel to the surface of the substrate, with the first well region located between the body region and the second well region; A first heavily doped region is located within the first well region and extends across to the second well region, wherein the doping concentration of the first heavily doped region is greater than that of the first well region and the second well region. The second and third doped regions are located within the second well region and are in close contact along a surface direction parallel to the substrate. Both the second and third doped regions are connected to the cathode. A source region and a base region, wherein the source region and the base region are adjacent and both are located within the body region, the source region is connected to the anode, and the base region is connected to the base. The second well region, the body region, and the second heavily doped region are all P-type in terms of conductivity; the first heavily doped region, the first well region, the buried layer, the source region, and the third heavily doped region are all N-type in terms of conductivity.

[0006] Optionally, the first heavily doped region is connected to a breakdown voltage terminal, and the voltage output by the breakdown voltage terminal is greater than or equal to 10V.

[0007] Optional, also includes: The drift region is located on the top surface of the buried layer and between the body region and the first well region; The drain region is located within the drift region, and both the drain region and the drift region are of the N-type conductivity.

[0008] Optionally, it further includes: a gate structure located at the interface between the body region and the drift region, wherein the source region and the drain region are located on opposite sides of the gate structure.

[0009] Optionally, it further includes: a first isolation structure located within the second well region and between the second heavily doped region and the first heavily doped region, wherein the depths of the second well region and the first well region are both greater than the depth of the first isolation structure.

[0010] Optional, also includes: The third well region is located on the top surface of the buried layer and between the drift region and the first well region; The fourth doped region is located within the third well region, and both the third well region and the fourth doped region are P-type in terms of conductivity.

[0011] Optionally, it further includes: a second isolation structure located between the first heavily doped region and the fourth heavily doped region, and between the first well region and the third well region, wherein the depth of the first well region and the depth of the third well region are both greater than the depth of the second isolation structure.

[0012] Optionally, it further includes: a third isolation structure located between the drain region and the fourth heavily doped region, and between the drift region and the third well region, wherein the depth of the drift region and the depth of the third well region are both greater than the depth of the third isolation structure.

[0013] Optionally, the N-type lateral double-diffused MOS field-effect transistor has a ring structure.

[0014] According to a second aspect of the present invention, a method for fabricating an N-type lateral double-diffused MOS field-effect transistor is provided, wherein the N-type lateral double-diffused MOS field-effect transistor as described in the first aspect and alternative embodiments of the present invention is fabricated.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the N-type lateral double-diffused MOS field-effect transistor provided by the technical solution of the present invention, the body region, the first well region, and the second well region are located on the buried layer along a surface direction parallel to the substrate, and the first well region is located between the body region and the second well region. The second heavily doped region and the third heavily doped region are located within the second well region and are in close contact along a surface direction parallel to the substrate. Since the conductivity type of the third heavily doped region, the buried layer, and the source region are all N-type, and the conductivity type of the second well region and the body region are all P-type, a PNPN structure is formed based on the second well region, the buried layer, the body region, and the source region to serve as the ESD conduction path of the base, and an NPNP structure is formed based on the third heavily doped region, the second well region, the buried layer, and the body region in parallel with the PNPN structure to serve as the ESD conduction path of the cathode. Thus, the N-type lateral double-diffused MOS field-effect transistor forms a bidirectional NPNPN structure with a simple structure, realizing bidirectional ESD protection without the need for additional ESD protection devices. Therefore, while taking into account the ESD protection effect, the integration density is improved.

[0016] Based on achieving bidirectional ESD protection for N-type lateral double-diffused MOSFETs, this invention further incorporates a first well region and a first heavily doped region. Since the first heavily doped region is located within the first well region and extends into the second well region, and its conductivity type is N-type, the conduction structure of the N-type lateral double-diffused MOSFET is replaced by an N-type doped / P-type well junction formed by the contact between the first and second well regions. Furthermore, because the doping concentration of the first heavily doped N-type region is much greater than that of the first well region, the electric field strength between the first heavily doped region and the second well region is significantly increased, reducing the breakdown voltage of the shallow junction of the N-type doped / P-type well. The low breakdown voltage of the shallow junction of the N-type doped / P-type well greatly reduces the trigger voltage of the N-type lateral double-diffused MOSFET.

[0017] In summary, the N-type lateral double-diffused MOS field-effect transistor provided by this invention significantly reduces the device's trigger voltage while maintaining ESD protection and improving device integration.

[0018] Furthermore, the first heavily doped region is connected to the breakdown voltage terminal, which outputs a voltage greater than or equal to 10V. The first well region and the first heavily doped region are electrically connected, thus placing both the first heavily doped region and the first well region under high voltage conditions. Since the electric field formed between the first and second well regions also superimposes with the electric field formed by the shallow junction of the N-type doped / P-type well, the electric field strength between the first heavily doped region and the second well region is further increased, thereby further reducing the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of an N-type lateral double-diffused MOS field-effect transistor; Figure 2 yes Figure 1 The local equivalent circuit diagram; Figure 3 This is a schematic diagram of the structure of an N-type lateral double-diffused MOS field-effect transistor according to an embodiment of the present invention; Figure 4 yes Figure 3 Equivalent circuit diagram of ESD protection circuit in China.

[0021] Figure label: 1. 11, 21-PNP structure; 2. 12, 22-NPN structure; 100, 200 - Substrate; 110, 210 - Buried layer; 120, 220 - Body region; 121, 221 - Source region; 122, 222 - Base region; 130, 230 - Drift region; 131, 231 - Drain region; 140, 150, 160 - Well region; 141, 151, 161 - Heavily doped region; 170, 270 - Gate structure; 240 - Third well region; 241 - Fourth heavily doped region; 250 - First well region; 251 - First heavily doped region; 260 - Second well region; 261 - Second heavily doped region; 262 - Third heavily doped region; 281 - First isolation structure; 282 - Second isolation structure; 283 - Third isolation structure. Detailed Implementation

[0022] As described in the background section, existing N-type lateral double-diffused MOSFETs achieve bidirectional ESD protection for a single N-type lateral double-diffused MOSFET by improving the heavily doped region within the well region connected to the cathode, without requiring additional ESD protection devices. However, in practical applications, this solution suffers from an excessively high trigger voltage, leading to protection failure for low-voltage sensitive circuits.

[0023] The following example of an N-type lateral double-diffused MOSFET illustrates the problems existing in prior art N-type lateral double-diffused MOSFETs: Figure 1 This is a schematic diagram of the structure of an N-type lateral double-diffused MOS field-effect transistor.

[0024] Please refer to Figure 1 An N-type lateral double-diffused MOS field-effect transistor may include a substrate 100 and a gate structure 170.

[0025] Specifically, the substrate 100 contains a buried layer 110, a body region 120, a source region 121, a base region 122, a drift region 130, a drain region 131, a well region 140, a heavily doped region 141, a well region 150, a heavily doped region 151, a well region 160, and a heavily doped region 161.

[0026] Among them, the substrate 100, body region 120, base region 122, well region 140, heavily doped region 141, well region 160 and heavily doped region 161 are all P-type in terms of conductivity, while the buried layer 110, source region 121, drift region 130, drain region 131, well region 150 and heavily doped region 151 are all N-type in terms of conductivity.

[0027] In this embodiment, body region 120, drift region 130, well region 140, well region 150, and well region 160 are all located on the top surface of buried layer 110. Well region 140 is located between body region 120 and well region 160, drift region 130 is located between body region 120 and well region 140, and well region 150 is located between well region 140 and well region 160. Source region 121 and base region 122 are located within body region 120, and source region 121 is connected to the anode (i.e., Figure 2 (S terminal shown), base region 122 is connected to the base (i.e. Figure 2 The B terminal is shown. Drain region 131 is located within drift region 130, and drain region 131 is connected to the drain electrode (i.e., Figure 2 (D terminal shown). Heavily doped region 141 is located within well region 140. Heavily doped region 151 is located within well region 150 and is connected to the Hvbn terminal. Heavily doped region 161 is located within well region 160 and is in close contact with it; heavily doped region 161 is connected to the cathode (i.e., Figure 2 (SPSUB terminal shown). The gate structure 170 is located on the surface of the substrate 100 between the source region 121 and the drain region 131, and the gate structure 170 is connected to the G terminal.

[0028] Please refer to Figure 2 , Figure 2 yes Figure 1 The local equivalent circuit diagram, in Figure 1 In the N-type lateral double-diffused MOS field-effect transistor, the well region 160, the buried layer 110, and the body region 120 constitute a PNP structure 1, and the buried layer 110, the body region 120, and the source region 121 constitute an NPN structure 2. The PNP structure 1 and the NPN structure 2 are connected back to back to form a PNPN structure, which serves as the ESD release path at the B end, thereby achieving ESD protection for the B end.

[0029] However, this N-type lateral double-diffused MOSFET still requires additional ESD protection devices to connect to the PSUB terminal to form an ESD release path for ESD protection. Therefore, to achieve ESD protection, the integration density of the N-type lateral double-diffused MOSFET is relatively low. Furthermore, the trigger voltage of this N-type lateral double-diffused MOSFET depends on the PN junction formed between the N-type well region 150 and the P-type well region 160. Since the doping concentrations of both the N-type and P-type well regions 150 are relatively low, the electric field strength between them is relatively low, resulting in a high breakdown voltage of the PN junction, for example, as high as 20-30V. This high trigger voltage makes the N-type lateral double-diffused MOSFET unsuitable for low-voltage sensitive applications.

[0030] In view of this, the technical solution of the present invention provides an N-type lateral double-diffused MOS field-effect transistor and its fabrication method. By setting a second heavily doped region and a third heavily doped region within the substrate, located in the second well region and connected to the cathode, a bidirectional NPNPN structure is formed, thereby achieving bidirectional ESD protection through a simple structure without the need for additional ESD protection devices. Thus, both ESD protection effectiveness and integration density are improved. Furthermore, by setting an N-type first well region and a first heavily doped region, with the first heavily doped region located within the first well region and extending into the second well region, a shallow junction of N-type doped / P-type well is formed, thereby significantly reducing the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor.

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] The terms “first,” “inner ring,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] The technical solution of the present invention will be described in detail below with reference to the embodiments in this example. These embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0034] Figure 3 This is a schematic diagram of the structure of an N-type lateral double-diffused MOS field-effect transistor according to an embodiment of the present invention.

[0035] Please refer to Figure 3 An N-type lateral double-diffused MOS field-effect transistor may include a substrate 200.

[0036] In this embodiment, the substrate 200 is a silicon substrate 200.

[0037] In other embodiments, the substrate may include at least one of the following materials: Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, the substrate 200 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc.

[0038] In this embodiment, the substrate 200 has a P-type conductivity.

[0039] The surface area of ​​the substrate 200 is provided with a buried layer 210.

[0040] In this embodiment, the conductivity type of the buried layer 210 is N-type, that is, the buried layer 210 is an N-type buried layer 210 (NBL).

[0041] In this embodiment, the substrate 200 below the buried layer 210 is connected to the cathode, that is... Figure 3 The PSUB terminal shown.

[0042] In this embodiment, the N-type lateral double-diffused MOS field-effect transistor may further include: a body region 220, a first well region 250, a second well region 260, a source region 221, a base region 222, a first heavily doped region 251, a second heavily doped region, and a third heavily doped region located on the buried layer 210.

[0043] In this embodiment, both the body region 220 and the second well region 260 are P-type.

[0044] In this embodiment, the body region 220 and the second well region 260 are in contact with each other, and both the body region 220 and the second well region 260 are located on the top surface of the buried layer 210. Through the inverted buried layer 210, the communication between the body region 220 and the second well region 260 and the substrate 200 below the buried layer 210 is blocked.

[0045] In this embodiment, both the source region 221 and the base region 222 are located within the body region 220, and the source region 221 and the base region 222 are adjacent. The source region 221 is connected to the anode, that is... Figure 3 The S-terminal is shown in the diagram. Base region 222 is connected to the base, that is... Figure 3 The B end is shown in the diagram.

[0046] In this embodiment, the source region 221 has an N-type conductivity and the base region 222 has a P-type conductivity.

[0047] In this embodiment, both the second and third heavily doped regions are located within the second well region 260 and connected to the cathode, that is, Figure 3 The PSUB terminal is shown in the diagram. The second doped region 261 and the third doped region 262 are in close contact along the surface direction of the substrate 200.

[0048] In this embodiment, the conductivity type of the second heavily doped region 261 is P-type, and the conductivity type of the third heavily doped region 262 is N-type. Therefore, by setting the second heavily doped region 261 and the third heavily doped region 262 in the second well region 260, not only can a PNPN structure be formed based on the second well region 260, the buried layer 210, the body region 220 and the source region 221 to serve as the ESD conduction path of the base, but also a parallel NPNP structure is formed based on the third heavily doped region 262, the second well region 260, the buried layer 210 and the body region 220 to serve as the ESD conduction path of the cathode. Thus, the N-type lateral double-diffused MOS field-effect transistor forms a bidirectional NPNPN structure with a simple structure, realizing bidirectional ESD protection without the need for additional ESD protection devices. Therefore, while taking into account the ESD protection effect, the integration density is improved.

[0049] Specifically, please refer to Figure 4In this embodiment of the N-type lateral double-diffused MOS field-effect transistor, the substrate 200 has a buried layer 210, and a body region 220, a second well region 260, a source region 221, a base region 222, and a second heavily doped region 261 are distributed therein. The body region 220 and the second well region 260 are in contact with each other, and both the body region 220 and the second well region 260 are located on the top surface of the buried layer 210. The source region 221 and the base region 222 are adjacent and both are located within the body region 220. The source region 221 is connected to the anode, and the base region 222 is connected to the base. The second well region 260 has a second heavily doped region. Region 261, and the substrate 200, body region 220, base region 222, second well region 260, and second heavily doped region 261 are P-type conductive, while the buried layer 210 and source region 221 are N-type conductive. Therefore, the second well region 260, buried layer 210, and body region 220 constitute a PNP structure 11, and the buried layer 110, body region 120, and source region 121 constitute an NPN structure 12. The PNP structure 11 and NPN structure 12 are connected back-to-back to form a PNPN structure. The S terminal is connected in series with a resistor R1 and connected to the base of the PNPN structure (i.e., Figure 4 The B end is shorted, thus serving as the ESD release path for the B end, thereby achieving ESD protection for the B end.

[0050] Based on this, a third heavily doped region 262 is provided within the second well region 260, and the third heavily doped region 262 is in close contact with the second heavily doped region 261 along the surface direction of the substrate 100. Therefore, the third heavily doped region 262, the second well region 260, and the buried layer 210 also constitute an NPN structure 22, and the second well region 260, the buried layer 210, and the body region 220 also constitute a PNP structure 21. The NPN structure 22 and the PNP structure 21 are connected back-to-back to form an NPNP structure. The third heavily doped region 262 is connected in series with a resistor R2 and short-circuited to the base of the NPN structure 22 (i.e., the second well region 260), thereby serving as an ESD release path for the PSUB terminal and realizing ESD protection for the cathode.

[0051] Therefore, by using multiple doped regions, second well regions, buried layers, bulk regions, and source regions, bidirectional ESD protection can be achieved, thereby improving integration density while ensuring ESD protection effectiveness.

[0052] Please continue to refer to this. Figure 3Based on the bidirectional ESD protection of the N-type lateral double-diffused MOS field-effect transistor, in this embodiment, the first well region 250 and the second well region 260 are adjacent and in contact with each other. The first heavily doped region 251 is located in the first well region 250 and extends to the second well region 260. Since the conductivity type of the first well region 250 and the first heavily doped region 251 is N-type and the conductivity type of the second well region 260 is P-type, the conduction structure of the N-type lateral double-diffused MOS field-effect transistor is replaced by the PN junction formed by the second well region 260 and the first well region 250, and replaced by a shallow junction of the N-type doped / P-type well formed by the first heavily doped region 251 and the second well region 260.

[0053] In this embodiment, the doping concentration of the first heavily doped region 251 is 10. 19 atoms / cm 3 ~10 21 atoms / cm 3 The doping concentration of the first well region 250 and the second well region 260 is only 10. 16 atoms / cm 3 ~10 18 atoms / cm 3 That is, the doping concentration of the first heavily doped region 251 is much greater than the doping concentration of the first well region 250 and the second well region 260. Therefore, the Fermi level of the heavily doped first well region 251 is close to the conduction band, while the Fermi level of the lightly doped second well region 260 is close to the valence band. After they come into contact, the depletion region is mainly concentrated in the second well region 260. Because the doping concentration of the first heavily doped region 251 is extremely high, the width of the depletion region is significantly reduced.

[0054] According to the formula for electric field strength, E=V / d, where E represents the electric field strength between the first heavily doped region 251 and the second well region 260, V represents the voltage, and d represents the width of the depletion region, the electric field strength between the first heavily doped region 251 and the second well region 260 increases significantly when the width of the depletion region decreases significantly and the voltage remains unchanged. This results in a significant reduction in the breakdown voltage of the shallow junction of the N-type doped / P-type well. In this embodiment, compared to the PN junction formed by the first well region 250 and the second well region 260, the breakdown voltage of the shallow junction of the N-type doped / P-type well decreases from 20V~30V to 8V~15V.

[0055] Furthermore, since the trigger voltage of an N-type lateral double-diffused MOS field-effect transistor is closely related to the breakdown voltage of the shallow junction of an N-type doped / P-type well, the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor is greatly reduced.

[0056] Therefore, the N-type lateral double-diffused MOS field-effect transistor provided in this embodiment, while taking into account the ESD protection effect and improving the device integration, greatly reduces the device's trigger voltage, so that the N-type lateral double-diffused MOS field-effect transistor can be applied in low-voltage sensitive scenarios, thus expanding the device's applicable scenarios.

[0057] In this embodiment, the first heavily doped region is connected to the breakdown voltage terminal, and the voltage output by the breakdown voltage terminal is greater than or equal to 10V. Since the first well region and the first heavily doped region are electrically connected, both the first heavily doped region and the first well region are under high voltage. Furthermore, because the electric field formed between the first well region and the second well region is superimposed on the electric field formed by the shallow junction of the N-type doped / P-type well, the electric field strength between the first heavily doped region and the second well region is further increased, thereby further reducing the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor.

[0058] Please continue to refer to this. Figure 3 The N-type lateral double-diffused MOS field-effect transistor may also include a drift region 230 and a drain region 231.

[0059] The drift region 230 is located on the top surface of the buried layer 210 and between the body region 220 and the second well region 260.

[0060] In this embodiment, the drain region 231 is located within the drift region 230, and the base region 222 and the drain region 231 are located on opposite sides of the source region 221.

[0061] In this embodiment, both the drift region 230 and the drain region 231 are N-type.

[0062] Furthermore, drain region 231 is a heavily doped region.

[0063] Please continue to refer to this. Figure 3 The N-type lateral double-diffused MOS field-effect transistor may also include: a first isolation structure 281.

[0064] Specifically, the first isolation structure 281 is located within the second well region 260 and between the second heavily doped region 261 and the first heavily doped region 251. Furthermore, the depths of both the second well region 260 and the first well region 250 are greater than the depth of the first isolation structure 281.

[0065] Please continue to refer to this. Figure 3 The substrate 200 also contains a third well region 240 and a fourth heavily doped region 241.

[0066] In this embodiment, the third well region 240 is located on the top surface of the buried layer 210 and is located between the drift region 230 and the first well region 250.

[0067] In this embodiment, the fourth doped region 241 is located within the third well region 240.

[0068] In this embodiment, the third well region 240 and the fourth heavily doped region 241 are both P-type in terms of conductivity.

[0069] In addition, the N-type lateral double-diffused MOS field-effect transistor may also include a second isolation structure 282.

[0070] Specifically, the second isolation structure 282 is located between the first heavily doped region 251 and the fourth heavily doped region 241, and the second isolation structure 282 is also located between the first well region 250 and the third well region 240. Furthermore, the depth of the first well region 250 and the depth of the third well region 240 are both greater than the depth of the second isolation structure 282.

[0071] In addition, the N-type lateral double-diffused MOS field-effect transistor may also include a third isolation structure 283.

[0072] Specifically, the third isolation structure 283 is located between the drain region 231 and the fourth heavily doped region 241, and the third isolation structure 283 is also located between the drift region 230 and the third well region 240. Furthermore, the depth of the drift region 230 and the depth of the third well region 240 are both greater than the depth of the third isolation structure 283.

[0073] Please continue to refer to this. Figure 3 The N-type lateral double-diffused MOS field-effect transistor may also include: gate structure 270.

[0074] In this embodiment, the gate structure 270 is located at the interface between the body region 220 and the drift region 230, and the source region 221 and the drain region 231 are located on both sides of the gate structure 270.

[0075] Furthermore, the gate structure 270 may include a polysilicon gate and a gate oxide layer located between the surfaces of the body region 220 and the drift region 230 and the polysilicon gate.

[0076] In one embodiment, the N-type lateral double-diffused MOS field-effect transistor has a ring structure.

[0077] Specifically, it can be a concentric ring structure with base region 222 as the center, or a runway-shaped ring structure; this application does not limit this.

[0078] In one specific embodiment, the N-type lateral double-diffused MOS field-effect transistor has a ring structure, with the body region 220 located at the center, the drift region 230 surrounding the body region 220, the third well region 240 surrounding the drift region 230, the first well region 250 surrounding the third well region 240, and the second well region 260 surrounding the first well region 250.

[0079] Similarly, source region 221, drain region 231, second doped region 261, third doped region 262, first doped region 251, fourth doped region 241, gate structure 270, isolation structure, etc., can all be ring structures.

[0080] Accordingly, this invention also provides a method for fabricating an N-type lateral double-diffused MOS field-effect transistor to produce the aforementioned N-type lateral double-diffused MOS field-effect transistor.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An N-type lateral double-diffused MOS field-effect transistor, characterized in that, include: A substrate, wherein a buried layer is provided on the surface region of the substrate; A body region, a first well region, and a second well region are located on the buried layer along a direction parallel to the surface of the substrate, with the first well region located between the body region and the second well region; A first heavily doped region is located within the first well region and extends across to the second well region, wherein the doping concentration of the first heavily doped region is greater than that of the first well region and the second well region. The second and third doped regions are located within the second well region and are in close contact along a surface direction parallel to the substrate. Both the second and third doped regions are connected to the cathode. A source region and a base region, wherein the source region and the base region are adjacent and both are located within the body region, the source region is connected to the anode, and the base region is connected to the base. The second well region, the body region, and the second heavily doped region are all P-type in terms of conductivity; the first heavily doped region, the first well region, the buried layer, the source region, and the third heavily doped region are all N-type in terms of conductivity.

2. The N-type lateral double-diffused MOS field-effect transistor according to claim 1, characterized in that, The first heavily doped region is connected to the breakdown voltage terminal, and the voltage output by the breakdown voltage terminal is greater than or equal to 10V.

3. The N-type lateral double-diffused MOS field-effect transistor according to claim 1, characterized in that, Also includes: The drift region is located on the top surface of the buried layer and between the body region and the first well region; The drain region is located within the drift region, and both the drain region and the drift region are of the N-type conductivity.

4. The N-type lateral double-diffused MOS field-effect transistor according to claim 3, characterized in that, It also includes: a gate structure located at the interface between the body region and the drift region, wherein the source region and the drain region are located on opposite sides of the gate structure.

5. The N-type lateral double-diffused MOS field-effect transistor according to claim 1, characterized in that, Also includes: A first isolation structure is located within the second well region and between the second heavily doped region and the first heavily doped region, wherein the depths of both the second well region and the first well region are greater than the depth of the first isolation structure.

6. The N-type lateral double-diffused MOS field-effect transistor according to claim 1, characterized in that, Also includes: The third well region is located on the top surface of the buried layer and between the drift region and the first well region; The fourth doped region is located within the third well region, and both the third well region and the fourth doped region are P-type in terms of conductivity.

7. The N-type lateral double-diffused MOS field-effect transistor according to claim 6, characterized in that, Also includes: The second isolation structure is located between the first heavily doped region and the fourth heavily doped region, and between the first well region and the third well region. The depth of the first well region and the depth of the third well region are both greater than the depth of the second isolation structure.

8. The N-type lateral double-diffused MOS field-effect transistor according to claim 6, characterized in that, It also includes: a third isolation structure located between the drain region and the fourth heavily doped region, and between the drift region and the third well region, wherein the depth of the drift region and the depth of the third well region are both greater than the depth of the third isolation structure.

9. The N-type lateral double-diffused MOS field-effect transistor according to any one of claims 1 to 8, characterized in that, The N-type lateral double-diffused MOS field-effect transistor has a ring structure.

10. A method for fabricating an N-type lateral double-diffused MOS field-effect transistor, characterized in that, Prepare an N-type lateral double-diffused MOS field-effect transistor as described in any one of claims 1 to 9.

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