Clock tree circuit, clock signal transmission method and chip

Abstract

The application discloses a clock tree circuit, a clock signal transmission method and a chip, and the circuit comprises a current mode logic buffer at a clock sending end, a clock wire network and a clock buffer at a clock receiving end; the current mode logic buffer is used for driving enhancement and high-frequency performance enhancement on an original differential clock signal generated by a clock source, obtaining an enhanced differential clock signal and driving the enhanced differential clock signal to the clock wire network; wherein the high-frequency performance enhancement is realized through an equivalent negative capacitance generated at an output end of the current mode logic buffer; the clock wire network is used for transmitting the enhanced differential clock signal to one or more clock receiving ends; and the clock buffer is used for performing level conversion and signal correction on the received enhanced differential clock signal, and obtaining a target differential clock signal. According to the application, the clock signal can be accurately and efficiently transmitted without additionally inserting a buffer in the clock wire.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a clock tree circuit, a clock signal transmission method, and a chip. Background Technology

[0002] With the development of high-speed circuits and the continuous improvement of data transmission rates, the number of input / output (I / O) interfaces on chips is constantly increasing. The clock signal, as the core reference for data synchronization in chip interfaces, needs to be transmitted to each I / O interface after being generated by the internal clock source of the chip. More I / O interfaces often mean that the clock signal needs to be transmitted over a longer physical distance within the chip. Clock signals are prone to degradation such as phase shift and duty cycle distortion during long-distance transmission, thus affecting the reliability of data synchronization. Therefore, ensuring accurate and efficient transmission of clock signals over long distances has become an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a clock tree circuit, a clock signal transmission method, and a chip. At the clock transmitting end, a current-mode logic buffer with a negative capacitance load is introduced to provide sufficient driving force and improve the high-frequency transmission quality. At the clock receiving end, a clock buffer is used for signal correction. Thus, without the need to insert an additional buffer in the clock trace, the clock signal can be transmitted accurately and efficiently.

[0004] A first aspect of the present invention provides a clock tree circuit, including: a current-mode logic buffer located at the clock transmitting end, a clock routing network, and a clock buffer located at the clock receiving end; The current-mode logic buffer is used to drive and enhance the high-frequency performance of the original differential clock signal generated by the clock source, to obtain an enhanced differential clock signal and drive it to the clock trace network; wherein, the high-frequency performance enhancement is achieved by generating an equivalent negative capacitance at the output of the current-mode logic buffer; The clock routing network is used to transmit the enhanced differential clock signal to one or more clock receivers; The clock buffer is used to perform level conversion and signal correction on the received enhanced differential clock signal to obtain the target differential clock signal.

[0005] Optionally, the clock trace network is composed of wires.

[0006] Optionally, the current-mode logic buffer includes: a differential input amplifier module and a cross-coupled load module; wherein the output terminal of the current-mode logic buffer is connected to the output terminal of the differential input amplifier module and the input terminal of the cross-coupled load module; The differential input amplifier module is used to amplify the original differential clock signal and transmit the amplified differential clock signal to the output terminal of the current mode logic buffer. The cross-coupled load module is used to enhance the high-frequency performance of the amplified differential clock signal based on the equivalent negative capacitance generated by the first capacitor connected between the output terminals of the cross-coupled transistors, so as to output the enhanced differential clock signal.

[0007] Optionally, the output terminal of the current-mode logic buffer includes: a first positive output terminal and a first negative output terminal; The cross-coupled load module includes: the cross-coupled transistor pair, a first capacitor, a first current source, and a second current source; wherein, the cross-coupled transistor pair includes: a first switching transistor and a second switching transistor; The input terminal of the first switching transistor is connected to the first inverting output terminal, the control terminal of the first switching transistor is connected to the first non-inverting output terminal, and the output terminal of the first switching transistor is connected to the input terminal of the first current source. The input terminal of the second switch is connected to the first non-inverting output terminal, the control terminal of the second switch is connected to the first inverting output terminal, and the output terminal of the second switch is connected to the input terminal of the second current source. The first terminal of the first capacitor is connected to the output terminal of the first switching transistor, and the second terminal of the first capacitor is connected to the output terminal of the second switching transistor. The output terminals of both the first and second current sources are grounded.

[0008] Optionally, the input terminals of the current-mode logic buffer include: a first non-inverting input terminal and a first inverting input terminal; The differential input amplifier module includes: a differential input pair transistor, a first variable resistor, a second variable resistor, and a tail current source; wherein, the differential input pair transistor includes: a third switch transistor and a fourth switch transistor; The control terminal of the third switch is connected to the first positive input terminal, the input terminal of the third switch is connected to the first terminal of the first variable resistor, and the output terminal of the third switch is connected to the input terminal of the tail current source. The control terminal of the fourth switch is connected to the first inverting input terminal, the input terminal of the fourth switch is connected to the first terminal of the second variable resistor, and the output terminal of the fourth switch is connected to the input terminal of the tail current source. The first inverting output terminal is connected to the first terminal of the first variable resistor, and the first non-inverting output terminal is connected to the first terminal of the second variable resistor. The second terminal of both the first variable resistor and the second variable resistor are used to connect to the power supply voltage.

[0009] Optionally, the clock buffer includes: a differential input processing module and a cross-coupled latch module; The differential input processing module is used to perform level conversion and duty cycle correction on the received enhanced differential clock signal to obtain a positive clock signal and an inverted clock signal, and transmit the positive clock signal to the positive output link and the inverted clock signal to the inverted output link. The cross-coupled latch module is used to sequentially regenerate the signals at n symmetrical positions in the positive and negative output links according to the internal n-stage positive feedback loop to obtain the target differential clock signal; wherein, n≥1; when multiple symmetrical positions are set on the positive or negative output link, there is at least one buffer unit between any two adjacent symmetrical positions; the first-stage positive feedback loop is used to perform the regeneration processing on the positive and negative clock signals; the regeneration processing includes: phase correction, target duty cycle locking and jitter suppression; the cross-coupled latch module includes: n latches constituting corresponding positive feedback loops and n-1 inverter combinations for inter-stage connection; the n latches are set one-to-one with the n symmetrical positions.

[0010] Optionally, the k-th latch includes a first inverter and a second inverter that are cross-coupled; where 1≤k≤n; The kth symmetrical position point in the positive output link is connected to the second positive input terminal of the kth latch and the second positive output terminal of the kth latch; The k-th symmetrical position point in the inverting output link is connected to the second inverting input terminal of the k-th latch and the second inverting output terminal of the k-th latch.

[0011] Optionally, when n≥2, the j-th inverter combination includes the third inverter and the fourth inverter; where 1≤j≤n-1; The input terminal of the third inverter is connected to the second positive input terminal of the preceding latch, and the output terminal of the third inverter is connected to the second inverting input terminal of the following latch. The input terminal of the fourth inverter is connected to the second inverting input terminal of the preceding latch, and the output terminal of the fourth inverter is connected to the second non-inverting input terminal of the following latch.

[0012] Optionally, the differential input processing module includes a non-inverting input processing branch and an inverting input processing branch; wherein, the non-inverting input processing branch includes: a second capacitor, a fifth inverter, a first feedback resistor, and a sixth inverter; The first terminal of the second capacitor is used to receive the positive phase signal in the enhanced differential clock signal, and the second terminal of the second capacitor is connected to the input terminal of the fifth inverter. The first end of the first feedback resistor is connected to the output terminal of the fifth inverter, and the second end of the first feedback resistor is connected to the input terminal of the fifth inverter. The input of the sixth inverter is connected to the output of the fifth inverter, and the output of the sixth inverter is connected to the input of the positive output link.

[0013] Optionally, the circuit further includes: a clock source composed of a phase-locked loop; wherein the phase-locked loop is used to generate a raw differential clock signal and transmit it to the current-mode logic buffer.

[0014] A second aspect of the present invention provides a clock signal transmission method, applicable to the clock tree circuit described in any embodiment of the first aspect; the method includes: The original differential clock signal generated by the clock source is driven and enhanced in high frequency performance by a current-mode logic buffer to obtain an enhanced differential clock signal, which is then driven to the clock trace network. The high frequency performance enhancement is achieved by generating an equivalent negative capacitance at the output of the current-mode logic buffer. The enhanced differential clock signal is transmitted to one or more clock receivers via a clock routing network. The received enhanced differential clock signal is level-shifted and corrected using a clock buffer to obtain the target differential clock signal.

[0015] A third aspect of the present invention provides a chip including the clock tree circuit described in any of the first aspects.

[0016] Compared with existing technologies, this invention provides a clock tree circuit, a clock signal transmission method, and a chip. At the clock transmitting end, a current-mode logic buffer with negative capacitance compensation is used to enhance the original differential clock signal's drive and high-frequency performance, resulting in an enhanced differential clock signal that is then driven to the clock trace network. Simultaneously, at the clock receiving end, a clock buffer with level conversion and signal correction functions is provided to perform level conversion and signal correction on the received enhanced differential clock signal, obtaining the target differential clock signal. This invention can effectively suppress clock signal phase shift and duty cycle distortion in long traces and high-load scenarios without the need for additional buffers in the clock traces, enhancing the circuit's resistance to process, voltage, and temperature variations, thereby achieving low-loss, high-precision clock signal transmission. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the clock tree circuit provided by the present invention; Figure 2 This is a schematic diagram of another embodiment of the clock tree circuit provided by the present invention; Figure 3 This is a schematic diagram of the structure of an embodiment of the current-mode logic buffer provided by the present invention; Figure 4 This is a schematic diagram of the structure of an embodiment of the differential input amplifier module provided by the present invention; Figure 5 This is a schematic diagram of another embodiment of the differential input amplifier module provided by the present invention; Figure 6 This is a schematic diagram of the structure of an embodiment of the clock buffer provided by the present invention; Figure 7 This is a schematic diagram of another embodiment of the clock buffer provided by the present invention; Figure 8 This is a flowchart illustrating an embodiment of the clock signal transmission method provided by the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that in scenarios with long clock traces corresponding to high-speed interfaces, related technologies typically transmit the clock signal generated by the internal clock source of the chip directly. They ensure the phase accuracy and duty cycle of the clock signal during transmission from the clock source to the high-speed interface by controlling the matching of multi-phase clock traces and inserting appropriate buffers or inverters in the trace layout. However, after research, the inventors discovered the following technical shortcomings in these technologies: (1) It has poor resistance to changes in process, voltage, and temperature (PVT) and is easily affected by process fluctuations, working voltage deviations and changes in ambient temperature, resulting in clock duty cycle distortion and clock skew. (2) There are requirements for the length of the trace. When the trace is too long, a large number of buffer devices need to be added to the trace to ensure the clock driving capability. This will not only significantly increase the power consumption of the circuit, but also further aggravate the clock skew.

[0020] See Figure 1 This is a schematic diagram of an embodiment of the clock tree circuit provided by the present invention.

[0021] To solve the above-mentioned technical problems, a first aspect of the present invention provides a clock tree circuit, including: a current-mode logic buffer 100 located at the clock transmitting end, a clock routing network 200, and a clock buffer 300 located at the clock receiving end. The current-mode logic buffer 100 is used to drive and enhance the high-frequency performance of the original differential clock signal generated by the clock source, to obtain an enhanced differential clock signal and drive it to the clock trace network 200; wherein, the high-frequency performance enhancement is achieved by generating an equivalent negative capacitance at the output terminal of the current-mode logic buffer 100. The clock routing network 200 is used to transmit the enhanced differential clock signal to one or more clock receivers. The clock buffer 300 is used to perform level conversion and signal correction on the received enhanced differential clock signal to obtain the target differential clock signal.

[0022] It should be noted that the clock transmitting end in this embodiment of the invention includes a clock source and a current-mode logic buffer 100. This embodiment of the invention can use a phase-locked loop (PLL) as the clock source to generate the original differential clock signals (denoted as CLK0 and CLK180), and transmit CLK0 and CLK180 to the current-mode logic buffer 100 (Current Mode Logic Buffer, CML BUFF). The CML BUFF enhances the drive and high-frequency performance of the received CLK0 and CLK180 to obtain enhanced differential clock signals (denoted as O_CLK0 and O_CLK180), and drives them to the clock routing net 200 (denoted as the CLK tree), i.e., the clock tree is driven by the CML BUFF. To further improve the high-frequency transmission quality, this embodiment of the invention introduces an equivalent negative capacitor at the output of the CML BUFF to compensate for the high-frequency loss caused by parasitic capacitance in the transmission channel, thereby enhancing the high-frequency performance of O_CLK0 and O_CLK180.

[0023] The clock trace net 200 is located between the clock transmitter and the clock receiver. It can be a clock tree (CLK tree) composed of metal traces, and no buffers need to be inserted on the traces. For example... Figure 2 The diagram shown is a structural schematic of another embodiment of the clock tree circuit provided by the present invention. Figure 2In the CLK tree, the CML BUFF processes CLK0 and CLK180 generated by the PLL, outputting O_CLK0 and O_CLK180. The CLK tree transmits O_CLK0 and O_CLK180 to one or more clock receivers. Each clock receiver includes a corresponding clock buffer 300 (denoted as CLK BUFF) and a transmitter (denoted as TX). In the CLK tree routing layout, the relative matching of O_CLK0 and O_CLK180 traces to all clock receivers must be ensured. The clock receiver is the clock signal receiving node corresponding to the internal chip / clock routing net 200, and can also serve as the clock signal transmitting node for the next-level device / external chip device. Figure 2 As shown, the clock receiver first processes the transmitted signal of CLKtree through CLK BUFF to obtain the target differential clock signal; then, the transmitter (TX) in the clock receiver outputs the target differential clock signal to the external device of the chip.

[0024] In each clock receiver, clock buffer 300 serves as the clock receiving circuit for the corresponding transmitter (TX), physically located adjacent to the parallel-to-serial conversion circuit of the corresponding TX. CLK BUFF performs level conversion (i.e., converting from a small-swing CML level to a full-swing CMOS level) and signal correction (i.e., phase correction and duty cycle correction) on the received O_CLK0 and O_CLK180, ultimately outputting a high-precision target differential clock signal for use by the parallel-to-serial conversion circuit of the TX.

[0025] As can be seen from the above, the clock tree circuit provided in this embodiment of the invention enhances the driving performance and high-frequency performance at the clock transmitting end by using a CML BUFF with negative capacitor compensation. At the same time, a CLK BUFF with level conversion and signal correction functions is set at the clock transmitting end (such as the external interface). Thus, in high-load and long-trace scenarios, there is no need to insert an additional buffer in the clock trace, which can effectively suppress the phase offset and duty cycle distortion of the clock signal, improve the ability to resist PVT fluctuations, and realize the efficient and accurate transmission of the clock signal.

[0026] It is worth noting that the clock tree circuit provided in this embodiment of the invention is mainly used to transmit the original differential clock signal generated by the clock source to the target receiving node (such as an external interface). The applicability of this clock tree circuit does not depend on a specific clock source. Any module that can provide a stable clock signal (i.e., the original differential clock signal) can be used as the clock source in this embodiment of the invention, such as a frequency divider, a frequency multiplier, and a front-end clock relay module, and is not limited to a phase-locked loop (PLL).

[0027] In an optional embodiment, the current-mode logic buffer 100 includes: a differential input amplifier module and a cross-coupled load module; wherein the output terminal of the current-mode logic buffer 100 is connected to the output terminal of the differential input amplifier module and the input terminal of the cross-coupled load module. The differential input amplifier module is used to amplify the received original differential clock signal and transmit the amplified differential clock signal to the output terminal of the current mode logic buffer 100. The cross-coupled load module is used to enhance the high-frequency performance of the amplified differential clock signal based on the equivalent negative capacitance generated by the first capacitor connected between the output terminals of the cross-coupled transistors, so as to output the enhanced differential clock signal.

[0028] It should be noted that the differential input amplifier module differentially amplifies the inputs CLK0 and CLK180, providing preset gain and drive capability. The cross-coupled load module internally contains a pair of cross-coupled transistors (such as NMOS transistors), with a first capacitor C1 connected between the outputs of the two transistors, forming an equivalent negative capacitance at the output of the CML BUFF. Through the inverted phase characteristic between the outputs via cross-coupling, when the phase of the CML BUFF output flips, the first capacitor C1 couples transient AC current (actively providing AC current). Observed from the output of the CML BUFF, the current direction of the first capacitor C1 is completely opposite to the current direction of the parasitic capacitance (positive capacitance) of the clock trace, thus canceling the negative impact of the parasitic capacitance.

[0029] See Figure 3 This is a schematic diagram of an embodiment of the current-mode logic buffer provided by the present invention.

[0030] In an optional embodiment, the output of the current-mode logic buffer 100 includes: a first positive output terminal OUTP1 and a first inverted output terminal OUTN1; The cross-coupled load module includes: the cross-coupled transistor pair, a first capacitor C1, a first current source I1, and a second current source I2; wherein, the cross-coupled transistor pair includes: a first switch M1 and a second switch M2; The input terminal of the first switch M1 is connected to the first inverting output terminal OUTN1, the control terminal of the first switch M1 is connected to the first non-inverting output terminal OUTP1, and the output terminal of the first switch M1 is connected to the input terminal of the first current source I1. The input terminal of the second switch M2 is connected to the first positive output terminal OUTP1, the control terminal of the second switch M2 is connected to the first inverted output terminal OUTN1, and the output terminal of the second switch M2 is connected to the input terminal of the second current source. The first terminal of the first capacitor C1 is connected to the output terminal of the first switching transistor M1, and the second terminal of the first capacitor C1 is connected to the output terminal of the second switching transistor M2. The output terminals of the first current source I1 and the second current source I2 are both grounded.

[0031] It should be noted that, as Figure 3 As shown, taking the example that both the first switch M1 and the second switch M2 are NMOS, the internal connection relationship of the cross-coupled load module is described in detail; wherein, the drain of the NMOS is the input terminal of the switch, the gate of the NMOS is the control terminal of the switch, and the source of the NMOS is the output terminal of the switch.

[0032] exist Figure 3 In this configuration, the drain of M1 is connected to OUTN1, and the gate of M1 is connected to OUTP1. The source of M1 is connected to the input terminal of the first current source I1 and the first terminal of the first capacitor C1. The drain of M2 is connected to OUTP1, and the gate of M2 is connected to OUTN1. The source of M2 is connected to the input terminal of the second current source I2 and the second terminal of the first capacitor C1. The first capacitor C1 is connected across the source of M1 and the source of M2. The output terminals of both the first current source I1 and the second current source I2 are grounded; and both current sources I1 and I2 provide the same current.

[0033] The original differential clock signal is amplified by the differential input amplifier module, forming a differential signal on OUTP1 and OUTN1. When OUTP1 is high and OUTN1 is low, M1 is turned on and M2 is turned off; when OUTP1 is low and OUTN1 is high, M1 is turned off and M2 is turned on. Since the conduction states of M1 and M2 are always opposite, their source voltage changes in opposite directions (i.e., in opposite phase).

[0034] During the dynamic process of OUTP1 and OUTN1 high-frequency switching, the sources of M1 and M2 generate voltage swings in opposite directions, causing the first capacitor C1 to couple and generate transient AC current (i.e., actively providing AC current). Observed from the OUTP1 and OUTN1 ports, the first capacitor C1 and the cross-coupled transistors work together to form an active equivalent negative capacitor, which can offset the high-frequency losses caused by parasitic capacitance in the clock trace, thereby effectively improving the high-frequency driving capability of the circuit.

[0035] In an optional embodiment, the input terminals of the current-mode logic buffer 100 include: a first non-inverting input terminal INP1 and a first inverting input terminal INN1; The differential input amplifier module includes: a differential input pair transistor, a first variable resistor R1, a second variable resistor R2, and a tail current source I0; wherein, the differential input pair transistor includes: a third switch transistor M3 and a fourth switch transistor M4; The control terminal of the third switch M3 is connected to the first positive input terminal INP1, the input terminal of the third switch M3 is connected to the first terminal of the first variable resistor R1, and the output terminal of the third switch M3 is connected to the input terminal of the tail current source I0. The control terminal of the fourth switch M4 is connected to the first inverting input terminal INN1, the input terminal of the fourth switch M4 is connected to the first terminal of the second variable resistor R2, and the output terminal of the fourth switch M4 is connected to the input terminal of the tail current source I0. The first inverting output terminal OUTN1 is connected to the first terminal of the first variable resistor R1, and the first non-inverting output terminal OUTP1 is connected to the first terminal of the second variable resistor R2. The second terminal of the first variable resistor R1 and the second terminal of the second variable resistor R2 are both used to connect to the power supply voltage VDD.

[0036] It should be noted that, as Figure 3 As shown, taking the third switch M3 and the fourth switch M4 as NMOS as an example, the internal connection relationship of the differential input amplifier module is described as follows: The gate of M3 is connected to INP1; the drain of M3 is connected to the first terminal of R1 and the first inverting output terminal OUTN1; the source of M3 is connected to the input terminal of the tail current source I0; the gate of M4 is connected to INP1; the drain of M4 is connected to the first terminal of R2 and the first non-inverting output terminal OUTP1; the source of M4 is connected to the input terminal of the tail current source I0; the output terminal of the tail current source I0 is grounded; the second terminals of R1 and R2 are both used to connect to the supply voltage VDD.

[0037] The differential input amplifier module operates as follows: The original differential clock signals CLK0 and CLK180 are input to the first non-inverting input terminal INP1 and the first inverting input terminal INN1, respectively. When INP1 is high and INN1 is low, M3 is turned on and M4 is turned off. The current provided by the tail current source I0 flows through M3 and R1, generating a voltage drop across R1, causing OUTN1 to output a low level. At the same time, since M4 is turned off, no current flows through R2, and its voltage drop is 0, causing OUTP1 to output a high level. Further, combined with the cross-coupled load module, when OUTP1 is high and OUTN1 is low, M1 is turned on and M2 is turned off. The first current source I1 is turned on and forms a current loop, while the second current source I2 is turned off. At this time, the total current flowing through R1 includes three current components: the tail current source I0, the first current source I1, and the transient AC current Ic generated by the reverse swing of the source voltages of M1 and M2 due to the first capacitor C1.

[0038] When the original differential clock signal flips (i.e., INP1 is low and INN1 is high), M3 is off, M4 is on, and the tail current source I0 flows entirely through M4 and R2, making OUTP1 low and OUTN1 high. This causes M1 to be off, M2 to be on, and the second current source I2 to be on, forming a current loop. The first current source I1 is off. At this time, the total current flowing through R2 includes three current components: the tail current source I0, the second current source I2, and the transient AC current Ic. Among them, R2 equals R1, and I2 equals I1.

[0039] In this embodiment of the invention, the swing and gain of the CML BUFF output signals (O_CLK0 and O_CLK180) can be changed by adjusting the resistance values ​​of the first variable resistor R1 and the second variable resistor R2, thereby meeting the design requirements of different application scenarios.

[0040] It is worth noting that the first variable resistor R1 and the second variable resistor R2 can be replaced by MOSFETs. For example... Figure 4 The diagram shown is a structural schematic of an embodiment of the differential input amplifier module provided by the present invention. Figure 4 In this configuration, R1 and R2 are replaced by two PMOS transistors (denoted as P1 and P2). The sources of both P1 and P2 are connected to VDD. The gate of P1 is shorted to its drain, and the drain of P1 is connected to the drain of M3. The gate of P2 is shorted to its drain, and the drain of P2 is connected to the drain of M4. Figure 5 The diagram shown is a structural schematic of another embodiment of the differential input amplifier module provided by the present invention. Figure 5 In this circuit, R1 and R2 are also replaced by two PMOS transistors (denoted as P3 and P4). The sources of P3 and P4 are both connected to VDD, the gate of P3 is connected to the gate of P4, the drain of P3 is connected to the drain of M3, and the drain of P4 is connected to the drain of M4.

[0041] Figure 4 and Figure 5 The PMOS transistors (P1~P4) in the circuit are always on when the circuit is working normally. The differential input amplifier module converts the current changes on the two branches into voltage rises and falls at the corresponding output nodes OUTP1 and OUTN1 based on the current distribution between the tail current source I0 in the corresponding branches of the differential input pair transistors (M3 and M4) and the equivalent impedance characteristics of the PMOS transistors. Finally, a differential voltage swing is formed at the OUTP1 and OUTN1 terminals.

[0042] In an optional embodiment, the clock buffer 300 includes: a differential input processing module and a cross-coupled latch module; The differential input processing module is used to perform level conversion and duty cycle correction on the received enhanced differential clock signal to obtain a positive clock signal and an inverted clock signal, and transmit the positive clock signal to the positive output link and the inverted clock signal to the inverted output link. The cross-coupled latch module is used to sequentially regenerate the signals at n symmetrical positions in the positive and negative output links according to the internal n-stage positive feedback loop to obtain the target differential clock signal; wherein, n≥1; when multiple symmetrical positions are set on the positive or negative output link, there is at least one buffer unit between any two adjacent symmetrical positions; the first-stage positive feedback loop is used to perform the regeneration processing on the positive and negative clock signals; the regeneration processing includes: phase correction, target duty cycle locking and jitter suppression; the cross-coupled latch module includes: n latches constituting corresponding positive feedback loops and n-1 inverter combinations for inter-stage connection; the n latches are set one-to-one with the n symmetrical positions.

[0043] It should be noted that the enhanced differential clock signal is a CML differential signal with a small swing and a low common-mode level. After receiving the CML signal from the clock trace 200, the differential input processing module converts it into a CMOS signal (full swing) and performs duty cycle correction, outputting a positive clock signal and an inverted clock signal. The positive clock signal is transmitted to the positive output link, and the inverted clock signal is transmitted to the inverted output link.

[0044] The first-stage positive feedback loop is directly connected to the input terminals of the non-inverting and inverting output links, and is used to perform the initial regeneration processing of the non-inverting and inverting clock signals output by the differential input processing module. This positive feedback loop utilizes the cross-coupling connection of two inverters to form a bistable structure, which can effectively correct phase deviation and force the differential signals to maintain a complementary relationship, thereby avoiding jitter and duty cycle loss. Since the duty cycle has already been corrected by the differential input processing module, the constraint of forced phase complementarity by the positive feedback loop will not destroy the corrected duty cycle, but can further stabilize and lock the target duty cycle.

[0045] When n≥2, the subsequent positive feedback loops are located at symmetrical points further back than the inverting and non-inverting output links. After the first regeneration process, the differential signal continues to propagate along the transmission link. During this period, it may deteriorate again due to factors such as parasitic capacitance of the traces. Subsequent positive feedback loops regenerate it sequentially. After n stages of regeneration by the positive feedback loops, the inverting and non-inverting output links output the final target differential clock signal for use by the TX parallel-to-serial conversion circuit. When designing the CLK BUFF circuit, appropriate buffer units (such as inverters) are inserted into the traces of the inverting and non-inverting output links according to their trace lengths to provide sufficient drive capability and compensate for trace load. On the inverting or non-inverting output link, the first symmetrical point is set at the input of the inverting or non-inverting output link (i.e., the input of the first buffer unit), and the remaining symmetrical points are set with one or more buffer units between them and the previous symmetrical point.

[0046] Clearly, the value of n is related to the number of buffer stages required to drive the corresponding trace length of the non-inverting or inverting output link. Inside the CLK BUFF, if the physical trace between the output of the differential input processing module and the parallel-to-serial conversion circuit of TX is long, the non-inverting and inverting output links require more buffer stages to provide sufficient driving capability to drive the load corresponding to the long trace. In this case, the value of n increases accordingly. For example, when the number of buffer stages required for the positive / inverting output links inside the CLK BUFF is 1 to 3, two-stage positive feedback loops can be configured, namely the input-stage positive feedback loop and the output-stage positive feedback loop. When the required number of buffer stages increases further, three-stage positive feedback loops can be configured; when the required number of buffer stages is even larger, more stages of positive feedback loops can be configured. If the physical trace is very short, n can be 1. In general, when designing the CLK BUFF circuit, the number of buffer stages (such as the number of inverters) of the positive / negative output links inside the CLK BUFF should be adaptively adjusted according to the actual physical trace length / load conditions. Furthermore, by reasonably selecting the value of n, the circuit can be flexibly adjusted according to the actual layout, thereby reducing unnecessary power consumption and area overhead while ensuring the quality of the clock signal.

[0047] like Figure 6 The diagram shown is a structural schematic of an embodiment of the clock buffer provided by the present invention. The input terminal INP2 of the CLK BUFF is used to input the positive phase signal in the enhanced differential clock signal, and the input terminal INN2 is used to input the negative phase signal in the enhanced differential clock signal. The output terminal OUTP2 of the CLK BUFF is the output terminal of the positive phase output link, and OUTN2 is the output terminal of the negative phase output link.

[0048] exist Figure 6In the process, the differential input processing module performs level conversion (CML to CMOS) and duty cycle correction on the received enhanced differential clock signal, and outputs a positive clock signal and an inverted clock signal. The positive clock signal is transmitted to the positive output link composed of inverters D9, D10 and D11; the inverted clock signal is transmitted to the inverted output link composed of inverters D14, D15 and D16. Figure 6 The cross-coupled latch module includes two stages of positive feedback loops. The first stage positive feedback loop (input stage positive feedback loop) performs the first regeneration processing on the signals at the corresponding input terminals (points a and b) of D9 and D14, completing phase correction, duty cycle locking, and jitter suppression. The signals after the first regeneration processing continue to be transmitted along the positive and negative output links. The second stage positive feedback loop (output stage positive feedback loop) performs the second regeneration processing on the signals at the corresponding output terminals (points c and d) of D10 and D15, further repairing the degradation caused by factors such as parasitic capacitance of the traces during signal transmission. After the two stages of regeneration processing, the two differential signals are driven and enhanced and shaped by inverters D11 and D16 respectively before the final output, and finally the target differential clock signal is obtained at the OUTP2 and OUTN2 terminals.

[0049] See Figure 7 This is a schematic diagram of another embodiment of the clock buffer provided by the present invention.

[0050] In an optional embodiment, the cross-coupled latch module includes: n latches forming corresponding positive feedback loops and n-1 inverter combinations for inter-stage connection; the k-th latch includes a first inverter and a second inverter cross-coupled; wherein, 1≤k≤n; The kth symmetrical position point in the positive output link is connected to the second positive input terminal of the kth latch and the second positive output terminal of the kth latch; The k-th symmetrical position point in the inverting output link is connected to the second inverting input terminal of the k-th latch and the second inverting output terminal of the k-th latch.

[0051] Furthermore, when n≥2, the j-th inverter combination includes the third inverter and the fourth inverter; where 1≤j≤n-1; The input terminal of the third inverter is connected to the second positive input terminal of the preceding latch, and the output terminal of the third inverter is connected to the second inverting input terminal of the following latch. The input terminal of the fourth inverter is connected to the second inverting input terminal of the preceding latch, and the output terminal of the fourth inverter is connected to the second non-inverting input terminal of the following latch.

[0052] Specifically, such as Figure 7As shown, taking n=2 as an example, the cross-coupled latch module is explained as follows: D1~D16 are all inverters; the first latch (input stage positive feedback loop) is composed of D1 and D2, which are cross-coupled to form a bistable structure; the first latch acts on the input terminals of the positive output link and the negative output link; specifically, the input terminal of the positive output link (point a) is connected to the second positive input terminal of the first latch (the input terminal of D2) and the second positive output terminal of the first latch (i.e., the output terminal of D1), and the input terminal of the negative output link (point b) is connected to the second negative input terminal of the first latch (the input terminal of D1) and the second negative output terminal of the first latch (the output terminal of D2). The second latch (output stage positive feedback loop) consists of D5 and D6, which are also cross-coupled. The second non-inverting input of the second latch is the input of D5, the second inverting input of the second latch is the input of D6, the second non-inverting output of the second latch is the output of D5, and the second inverting output of the second latch is the output of D6. The second latch operates on the outputs of D10 and D15 (points c and d, close to the final outputs OUTP2 and OUTN2).

[0053] The first inverter combination (used for interstage connection) consists of D3 and D4. The input of D3 is connected to the second non-inverting input of the first latch (i.e., the input of D2), and the output of D3 is connected to the second inverting input of the second latch (the input of D6). The connection method of D4 is similar to that of D3, and will not be described in detail here.

[0054] The inverter group (D3 and D4) enables drive enhancement and phase matching between the preceding and following latches, while also playing a crucial role in maintaining and transmitting the corrected duty cycle. After regeneration processing by D1 and D2 in the first latch, the target duty cycle of the differential signal is stably locked, forming a differential waveform with complementary phase and symmetrical waveform. D3 and D4 only perform level flipping and drive enhancement on the signal without changing the duty cycle information. They can completely transmit the duty cycle information of the first latch to the second latch, enabling the second latch to apply positive feedback to the signals at corresponding symmetrical positions (points c and d) in the positive and negative output links, effectively suppressing jitter, phase deviation, and duty cycle distortion introduced in the positive / negative output links.

[0055] In an optional embodiment, the differential input processing module includes a non-inverting input processing branch and an inverting input processing branch; wherein, the non-inverting input processing branch includes: a second capacitor C2, a fifth inverter D7, a first feedback resistor R3, and a sixth inverter D8; The first terminal of the second capacitor C2 is used to receive the positive phase signal in the enhanced differential clock signal, and the second terminal of the second capacitor C2 is connected to the input terminal of the fifth inverter D7. The first end of the first feedback resistor is connected to the output terminal of the fifth inverter D7, and the second end of the first feedback resistor is connected to the input terminal of the fifth inverter D7. The input terminal of the sixth inverter D8 is connected to the output terminal of the fifth inverter D7, and the output terminal of the sixth inverter D8 is connected to the input terminal of the non-inverting output link.

[0056] It should be noted that, in Figure 7 In the non-inverting input processing branch, the second capacitor C2, the fifth inverter D7, the first feedback resistor R3, and the sixth inverter D8 work together to achieve duty cycle correction and conversion from CML level to CMOS level. The second capacitor C2 AC couples the positive-inverting signal in the enhanced differential clock signal to isolate the DC component and low-frequency offset in the positive-inverting signal. The first feedback resistor R3 and the output terminal of the fifth inverter D7 form a feedback bias recovery path, which is used to establish an adaptive dynamic operating point (DC bias) for the input node of the fifth inverter D7. With the help of this dynamic operating point, the fifth inverter D7 performs threshold re-determination on the rising and falling edges of the AC-coupled positive-inverting signal, thereby reducing the duty cycle deviation of the positive-inverting signal caused by long trace transmission distortion, PVT, etc., to obtain the duty cycle corrected CMOS clock signal and transmit it to the sixth inverter D8, which further drives, enhances, and shapes the waveform of the CMOS clock signal.

[0057] The inverting input branch is symmetrical and includes: the third capacitor C3, the seventh inverter D12, the second feedback resistor R4, and the eighth inverter D13. The inverting input branch is symmetrical to the non-inverting input processing branch and operates on the same principle; therefore, it will not be described in detail here.

[0058] It is worth noting that NAND (NAND gate) or NOR (NOR gate) can be used to... Figure 6 or Figure 7 Replacing the inverter in the CLK BUFF can achieve the same functionality. This embodiment of the invention does not impose specific limitations on the internal circuit implementation of the CLK BUFF, as long as it can achieve level conversion (i.e., CML-to-CMOS) and signal correction (i.e., duty cycle correction and phase correction).

[0059] See Figure 8 This is a flowchart illustrating an embodiment of the clock signal transmission method provided by the present invention.

[0060] A second aspect of the present invention provides a clock signal transmission method, applicable to the clock tree circuit described in any of the first aspects above; comprising steps S1 to S3, as follows: Step S1: The original differential clock signal generated by the clock source is driven and enhanced in high frequency performance through a current-mode logic buffer to obtain an enhanced differential clock signal and drive it to the clock trace network; wherein, the high frequency performance enhancement is achieved by generating an equivalent negative capacitance at the output of the current-mode logic buffer; Step S2: Transmit the enhanced differential clock signal to one or more clock receivers via a clock routing network; Step S3: The received enhanced differential clock signal is level-shifted and signal-corrected using a clock buffer to obtain the target differential clock signal.

[0061] It should be noted that the clock signal transmission method provided in this embodiment of the invention can implement all the processing flows in the clock tree circuit described in any of the embodiments of the first aspect above. The specific implementation schemes and technical effects of the clock signal transmission method correspond to the same specific implementation schemes and technical effects of the clock tree circuit described in any of the embodiments of the first aspect above, and will not be repeated here.

[0062] A third aspect of the present invention provides a chip including the clock tree circuit described in any of the first aspects of the present invention.

[0063] It should be noted that the chip in the embodiments of the present invention can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0064] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A clock tree circuit, characterized in that, include: The current-mode logic buffer and clock routing net are located at the clock transmitting end, and the clock buffer is located at the clock receiving end. The current-mode logic buffer is used to drive and enhance the high-frequency performance of the original differential clock signal generated by the clock source, to obtain an enhanced differential clock signal and drive it to the clock trace network; wherein, the high-frequency performance enhancement is achieved by generating an equivalent negative capacitance at the output of the current-mode logic buffer; The clock routing network is used to transmit the enhanced differential clock signal to one or more clock receivers; The clock buffer is used to perform level conversion and signal correction on the received enhanced differential clock signal to obtain the target differential clock signal.

2. The clock tree circuit as described in claim 1, characterized in that, The clock wiring network is composed of wires.

3. The clock tree circuit as described in claim 1, characterized in that, The current-mode logic buffer includes a differential input amplifier module and a cross-coupled load module; wherein the output terminal of the current-mode logic buffer is connected to the output terminal of the differential input amplifier module and the input terminal of the cross-coupled load module. The differential input amplifier module is used to amplify the original differential clock signal and transmit the amplified differential clock signal to the output terminal of the current mode logic buffer. The cross-coupled load module is used to enhance the high-frequency performance of the amplified differential clock signal based on the equivalent negative capacitance generated by the first capacitor connected between the output terminals of the cross-coupled transistors, so as to output the enhanced differential clock signal.

4. The clock tree circuit as described in claim 3, characterized in that, The output terminals of the current-mode logic buffer include: a first positive output terminal and a first inverted output terminal; The cross-coupled load module includes: the cross-coupled transistor pair, a first capacitor, a first current source, and a second current source; wherein, the cross-coupled transistor pair includes: a first switching transistor and a second switching transistor; The input terminal of the first switching transistor is connected to the first inverting output terminal, the control terminal of the first switching transistor is connected to the first non-inverting output terminal, and the output terminal of the first switching transistor is connected to the input terminal of the first current source. The input terminal of the second switch is connected to the first non-inverting output terminal, the control terminal of the second switch is connected to the first inverting output terminal, and the output terminal of the second switch is connected to the input terminal of the second current source. The first terminal of the first capacitor is connected to the output terminal of the first switching transistor, and the second terminal of the first capacitor is connected to the output terminal of the second switching transistor. The output terminals of both the first and second current sources are grounded.

5. The clock tree circuit as described in claim 4, characterized in that, The input terminals of the current-mode logic buffer include: a first positive input terminal and a first negative input terminal; The differential input amplifier module includes: a differential input pair transistor, a first variable resistor, a second variable resistor, and a tail current source; wherein, the differential input pair transistor includes: a third switch transistor and a fourth switch transistor; The control terminal of the third switch is connected to the first positive input terminal, the input terminal of the third switch is connected to the first terminal of the first variable resistor, and the output terminal of the third switch is connected to the input terminal of the tail current source. The control terminal of the fourth switch is connected to the first inverting input terminal, the input terminal of the fourth switch is connected to the first terminal of the second variable resistor, and the output terminal of the fourth switch is connected to the input terminal of the tail current source. The first inverting output terminal is connected to the first terminal of the first variable resistor, and the first non-inverting output terminal is connected to the first terminal of the second variable resistor. The second terminal of both the first variable resistor and the second variable resistor are used to connect to the power supply voltage.

6. The clock tree circuit as described in claim 1, characterized in that, The clock buffer includes: a differential input processing module and a cross-coupled latch module; The differential input processing module is used to perform level conversion and duty cycle correction on the received enhanced differential clock signal to obtain a positive clock signal and an inverted clock signal, and transmit the positive clock signal to the positive output link and the inverted clock signal to the inverted output link. The cross-coupled latch module is used to sequentially regenerate the signals at n symmetrical positions in the positive and negative output links according to the internal n-stage positive feedback loop to obtain the target differential clock signal; wherein, n≥1; when multiple symmetrical positions are set on the positive or negative output link, there is at least one buffer unit between any two adjacent symmetrical positions; the first-stage positive feedback loop is used to perform the regeneration processing on the positive and negative clock signals; the regeneration processing includes: phase correction, target duty cycle locking and jitter suppression; the cross-coupled latch module includes: n latches constituting corresponding positive feedback loops and n-1 inverter combinations for inter-stage connection; the n latches are set one-to-one with the n symmetrical positions.

7. The clock tree circuit as described in claim 6, characterized in that, The k-th latch consists of a first inverter and a second inverter that are cross-coupled; where 1≤k≤n; The kth symmetrical position point in the positive output link is connected to the second positive input terminal of the kth latch and the second positive output terminal of the kth latch; The k-th symmetrical position point in the inverting output link is connected to the second inverting input terminal of the k-th latch and the second inverting output terminal of the k-th latch.

8. The clock tree circuit as described in claim 7, characterized in that, When n≥2, the j-th inverter combination includes the third inverter and the fourth inverter; where 1≤j≤n-1; The input terminal of the third inverter is connected to the second positive input terminal of the preceding latch, and the output terminal of the third inverter is connected to the second inverting input terminal of the following latch. The input terminal of the fourth inverter is connected to the second inverting input terminal of the preceding latch, and the output terminal of the fourth inverter is connected to the second non-inverting input terminal of the following latch.

9. The clock tree circuit as described in claim 6, characterized in that, The differential input processing module includes a non-inverting input processing branch and an inverting input processing branch; wherein, the non-inverting input processing branch includes: a second capacitor, a fifth inverter, a first feedback resistor, and a sixth inverter; The first terminal of the second capacitor is used to receive the positive phase signal in the enhanced differential clock signal, and the second terminal of the second capacitor is connected to the input terminal of the fifth inverter. The first end of the first feedback resistor is connected to the output terminal of the fifth inverter, and the second end of the first feedback resistor is connected to the input terminal of the fifth inverter. The input of the sixth inverter is connected to the output of the fifth inverter, and the output of the sixth inverter is connected to the input of the positive output link.

10. The clock tree circuit as described in claim 1, characterized in that, The circuit further includes a clock source composed of a phase-locked loop; wherein the phase-locked loop is used to generate the original differential clock signal and transmit it to the current-mode logic buffer.

11. A clock signal transmission method, characterized in that, Applicable to clock tree circuits as described in any one of claims 1 to 10; The method includes: The original differential clock signal generated by the clock source is driven and enhanced in high frequency performance by a current-mode logic buffer to obtain an enhanced differential clock signal, which is then driven to the clock trace network. The high frequency performance enhancement is achieved by generating an equivalent negative capacitance at the output of the current-mode logic buffer. The enhanced differential clock signal is transmitted to one or more clock receivers via a clock routing network. The received enhanced differential clock signal is level-shifted and corrected using a clock buffer to obtain the target differential clock signal.

12. A chip, characterized in that, Includes the clock tree circuit as described in any one of claims 1 to 10.

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