A single-stage boost inverter
By using a single-stage boost inverter structure and bridge arm clamping control, the problems of high bus voltage and output voltage distortion are solved, achieving continuous inductor current and high-quality AC output, and simplifying the control structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 浙江屹晶微电子股份有限公司
- Filing Date
- 2026-04-03
- Publication Date
- 2026-06-23
AI Technical Summary
Existing inverters have problems such as high bus voltage requirements, the output voltage being easily distorted due to the series connection of the Boost power electronics stage and the inverter stage, the inductor current being difficult to return to zero naturally under light load conditions, and the ground sampling being prone to bias.
The single-stage boost inverter structure is adopted, in which the left and right bridge arms alternately participate in the boosting during the positive and negative half-cycles. The first and second inductors complete energy storage and energy release in different half-cycles respectively, and the boosting circuit is formed by the bridge arm clamping method. Combined with the voltage loop and current loop for closed-loop control, the boosting and inversion functions are coordinated.
While achieving boost and inversion in a single-stage topology, it avoids output voltage distortion, ensures the continuity of inductor current, simplifies the control structure, and reduces the number of system components.
Smart Images
Figure CN122268185A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics technology, specifically to a single-stage boost inverter. Background Technology
[0002] With the development of photovoltaic power generation, energy storage inverters, motor drives, and various distributed power supply systems, the demand for DC power to output electrical energy to AC loads is constantly increasing. Currently, most inverters on the market use a buck converter topology for their DC-AC power electronics conversion section. This topology requires the DC bus voltage to be higher than the peak value of the output AC voltage to obtain a sinusoidal output that meets the amplitude requirements. Existing Boost converters typically connect the boost circuit and the inverter circuit in series. The ripple, bias, and dynamic response of the Boost converter's output voltage directly affect the modulation effect of the inverter bridge, especially under light loads or near the zero-crossing point of the output voltage, which can easily lead to AC voltage waveform distortion.
[0003] Therefore, existing technologies still have limitations in terms of topology, modulation method, synchronous freewheeling, voltage sampling, and filter capacitor configuration, making it difficult to simultaneously meet the requirements of boost function and high-quality AC output. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a single-stage boost inverter that solves the problems of high bus voltage requirements, output voltage distortion caused by the series connection of the Boost power electronics stage and the inverter stage, difficulty in the inductor current returning to zero naturally under light load conditions, and easy bias generation during ground sampling in existing inverters.
[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: a single-stage boost inverter, comprising a left bridge arm, a right bridge arm, a first inductor L3, a second inductor L4, a controller, a first filter capacitor, and a second filter capacitor. The left bridge arm includes a second upper transistor S7 and a second lower transistor S8, the connection point of which constitutes the output node Vacl of the left bridge arm. The right bridge arm includes a first upper transistor S5 and a first lower transistor S6, the connection point of which constitutes the output node Vacn of the right bridge arm. The controller is used to generate PWM drive signals for each switching transistor of the left and right bridge arms.
[0006] During the positive half-cycle of the output voltage, the controller controls the first upper transistor S5 to turn on and the first lower transistor S6 to turn off, and controls the second upper transistor S7 and the second lower transistor S8 to perform switching control, so that the first inductor L3 and the left bridge arm form a boost circuit.
[0007] During the negative half-cycle of the output voltage, the controller controls the second upper transistor S7 to turn on and the second lower transistor S8 to turn off, and controls the first upper transistor S5 and the first lower transistor S6 to perform switching control, so that the second inductor L4 and the right bridge arm form a boost circuit.
[0008] Vacl and Vacn constitute the AC output terminal of the inverter, and the AC output terminal voltage Vac is the potential difference between Vacl and Vacn.
[0009] Preferably, the controller includes a voltage loop and a current loop. The voltage loop generates a reference current Iref based on the AC output voltage Vac, and the current loop generates PWM drive signals for each switch transistor in the left and right bridge arms based on the reference current Iref.
[0010] Preferably, the voltage loop acquires the AC output voltage Vac in each PWM cycle and updates the PWM duty cycle within that PWM cycle.
[0011] Preferably, during the positive half-cycle boost, when the first lower transistor S6 is in the off state, the controller controls the second upper transistor S7 to turn on, so that the inductor current of the first inductor L3 forms a freewheeling path through the left bridge arm. During the negative half-cycle boost, when the second lower transistor S8 is in the off state, the controller controls the first upper transistor S5 to turn on, so that the inductor current of the second inductor L4 forms a freewheeling path through the right bridge arm.
[0012] Preferably, the first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 are all power switching devices used to control the opening and closing of the corresponding bridge arms.
[0013] Preferably, the AC output voltage Vac is acquired by a sampling circuit connected between Vacl and Vacn.
[0014] Preferably, the first inductor L3 participates in the boost during the positive half-cycle of the output voltage, and the second inductor L4 participates in the boost during the negative half-cycle of the output voltage.
[0015] Preferably, the first filter capacitor is connected between the output node Vacl of the left bridge arm and the positive terminal of the DC bus, and the second filter capacitor is connected between the output node Vacn of the right bridge arm and the positive terminal of the DC bus.
[0016] Preferably, the first end of the first inductor L3 is connected to the left bridge arm output node Vacl, and the first end of the second inductor L4 is connected to the right bridge arm output node Vacn.
[0017] Preferably, a method of using a single-stage boost inverter, for use in any one of claims 1-9, the method comprising the following steps:
[0018] S1. Collect the AC output voltage Vac between Vacl and Vacn;
[0019] S2. Generate a reference current Iref based on Vac.
[0020] S3. Calculate the PWM duty cycle of the first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 based on Iref;
[0021] S4. During the positive half-cycle, control the first upper transistor S5 to be turned on and the first lower transistor S6 to be turned off, so that the first inductor L3 and the left bridge arm form a boost circuit.
[0022] S5. During the negative half-cycle, control the second upper tube S7 to be turned on and the second lower tube S8 to be turned off, so that the second inductor L4 and the right bridge arm form a boost circuit.
[0023] S6. When the first lower transistor S6 is turned off, the second upper transistor S7 is turned on to form a freewheeling path for the first inductor L3.
[0024] S7. When the second lower tube S8 is turned off, the first upper tube S5 is turned on to form a freewheeling path for the second inductor L4.
[0025] S8. Generate the AC output voltage Vac based on the potential difference between Vacl and Vacn.
[0026] This invention provides a single-stage boost inverter. It has the following advantages:
[0027] 1. In this invention, by utilizing the alternating participation of the left and right bridge arms in the positive and negative half-cycles of the voltage boosting process, the first inductor L3 and the second inductor L4 complete energy storage and release in different half-cycles respectively, and form a reference point for the boost circuit through bridge arm clamping. This achieves both boosting and inversion functions in a single-stage topology. Through the differential output Vac, a bipolar AC voltage can be directly obtained, avoiding the need for a separate boost stage and making the overall structure more focused and clear.
[0028] 2. In this invention, during the positive half-cycle, the first inductor L3 and the left bridge arm form a boost circuit, and during the negative half-cycle, the second inductor L4 and the right bridge arm form a boost circuit. When the lower transistor is turned off, the upper transistor of the corresponding bridge arm or the anti-parallel diode provides a freewheeling path for the inductor, so that the inductor current remains continuous in both half-cycles, forming a complete energy storage, energy release and freewheeling process, ensuring the continuity of boost control action during half-cycle switching.
[0029] 3. In this invention, the AC output voltage Vac is acquired in real time through a sampling circuit connected between Vacl and Vacln. Then, a voltage loop generates a reference current Iref based on the acquired voltage, and a current loop adjusts the PWM drive signals of each inverter switch according to Iref. The first upper switch S5 and the first lower switch S6 form the right bridge arm, and the second upper switch S7 and the second lower switch S8 form the left bridge arm. The controller updates the PWM duty cycle of the four bridge arm switches cycle by cycle, enabling the output voltage Vac to be adjusted according to changes in the reference signal. This control method forms a closed loop between the boost process and inverter modulation in a single-stage structure, allowing the output waveform to be generated according to the set target. Attached Figure Description
[0030] Figure 1 This is a circuit diagram of the present invention. Detailed Implementation
[0031] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] Please see the appendix Figure 1 This invention provides a single-stage boost inverter, including a left bridge arm, a right bridge arm, a first inductor L3, a second inductor L4, a controller, a first filter capacitor, and a second filter capacitor. The left bridge arm includes a second upper transistor S7 and a second lower transistor S8, and the connection point of the second upper transistor S7 and the second lower transistor S8 forms the output node Vacl of the left bridge arm. The right bridge arm includes a first upper transistor S5 and a first lower transistor S6, and the connection point of the first upper transistor S5 and the first lower transistor S6 forms the output node Vacn of the right bridge arm. The controller is used to generate PWM drive signals for each switch transistor of the left and right bridge arms.
[0033] During the positive half-cycle of the output voltage, the controller controls the first upper transistor S5 to turn on and the first lower transistor S6 to turn off, and controls the second upper transistor S7 and the second lower transistor S8 to perform switching control, so that the first inductor L3 and the left bridge arm form a boost circuit.
[0034] During the negative half-cycle of the output voltage, the controller controls the second upper transistor S7 to turn on and the second lower transistor S8 to turn off, and controls the first upper transistor S5 and the first lower transistor S6 to perform switching control, so that the second inductor L4 and the right bridge arm form a boost circuit.
[0035] Vacl and Vacn constitute the AC output terminal of the inverter, and the AC output voltage Vac is the potential difference between Vacl and Vacn.
[0036] Specifically, the PWM drive signals generated by the controller for each switch in the left and right bridge arms enable each bridge arm to perform functions such as boost, clamping, and freewheeling at different operating periods. During the positive half-cycle of the output voltage, the controller puts the first upper transistor S5 of the right bridge arm into the conducting state and the first lower transistor S6 into the off state, clamping the output node Vacn of the right bridge arm to the DC bus potential. At the same time, the controller performs PWM control on the second upper transistor S7 and the second lower transistor S8 in the left bridge arm, causing the first inductor L3 to form a boost circuit through the periodic switching of the bridge arm switches. When the second lower transistor S8 is turned off, the inductor current of the first inductor L3 forms a freewheeling current through the second upper transistor S7 or the anti-parallel diode, thereby ensuring the continuity of the inductor current and boosting the potential of Vacl relative to Vacn, forming the AC output voltage waveform of the positive half-cycle.
[0037] During the negative half-cycle of the output voltage, the controller turns on the second upper transistor S7 of the left bridge arm and turns off the second lower transistor S8, clamping Vacl to the DC bus potential. Simultaneously, the controller performs PWM control on the first upper transistor S5 and the first lower transistor S6 of the right bridge arm, creating a boost circuit between the second inductor L4 and the right bridge arm. When the first lower transistor S6 is turned off, the inductor current of the second inductor L4 freewheels through the first upper transistor S5 or the anti-parallel diode, boosting the potential of Vacn relative to Vacl, thus obtaining the negative half-cycle AC output voltage waveform. Through this alternating boost between the positive and negative half-cycles, the inverter in this embodiment can obtain a bipolar AC output voltage in a single-stage topology. Furthermore, since the open-loop characteristics of boost are different from those of buck, a fixed SPWM modulation wave cannot be used, otherwise severe sine wave distortion will occur. Therefore, the output voltage must be sampled for each PWM cycle and the duty cycle of the power PWM must be adjusted so that the output voltage is regulated in each PWM cycle, avoiding the sine wave distortion generated under fixed SPWM modulation.
[0038] Through the above-described operation, the two bridge arms undertake the boosting task during the positive and negative half-cycles, respectively, and achieve continuous current mode through synchronous freewheeling of the inductor current. Compared with the traditional two-stage structure that requires boosting before H-bridge inversion, this embodiment enables a single-stage structure to complete both boosting and inversion functions through clamping control of the two bridge arms and PWM coordination. This reduces the number of system components and simplifies the control structure. Since the output voltage is formed by the differential method of Vacl and Vacn, this embodiment can establish a higher amplitude AC output through inductor boosting while keeping the bus voltage constant. Therefore, it can be used in scenarios requiring a single-stage high boost ratio AC output, such as photovoltaic, energy storage inverters, and drive power supplies.
[0039] Please see the appendix Figure 1The controller includes a voltage loop and a current loop. The voltage loop generates a reference current Iref based on the AC output voltage Vac, and the current loop generates PWM drive signals for each switch transistor in the left and right bridge arms based on the reference current Iref.
[0040] Specifically, this is achieved through voltage and current loops within the controller. The voltage loop adjusts the amplitude of the AC output voltage, taking the acquired AC output voltage Vac as its input. The voltage loop then generates a reference current Iref based on the deviation between Vac and a preset voltage reference, indicating the target output current required by the inverter in the current operating state. The current loop tracks Iref on a faster timescale and adjusts the PWM duty cycle of the first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 based on the current deviation, thereby controlling the boost and inversion operations within each PWM cycle. This ensures that the on / off states of each switch are adjusted according to changes in the reference current Iref, thus controlling the output current waveform.
[0041] Please see the appendix Figure 1 The voltage loop acquires the AC output voltage Vac in each PWM cycle and updates the PWM duty cycle within that PWM cycle.
[0042] Specifically, the voltage loop acquires the AC output voltage Vac in each PWM cycle and compares the acquired voltage value with the voltage reference value. Based on the comparison result, the voltage loop updates the reference current Iref within the PWM cycle, so that the reference current can reflect the changes in the output voltage in real time and realize the cycle-by-cycle adjustment of the output voltage amplitude.
[0043] Please see the appendix Figure 1 During the positive half-cycle boost, when the first lower transistor S6 is in the off state, the controller controls the second upper transistor S7 to turn on, so that the inductor current of the first inductor L3 forms a freewheeling path through the left bridge arm. During the negative half-cycle boost, when the second lower transistor S8 is in the off state, the controller controls the first upper transistor S5 to turn on, so that the inductor current of the second inductor L4 forms a freewheeling path through the right bridge arm.
[0044] Specifically, during the positive half-cycle boost, when the first lower transistor S6 of the right bridge arm is off, the inductor current of the first inductor L3 cannot be interrupted instantaneously. However, to provide a continuous current path, the controller needs to turn on the second upper transistor S7 of the left bridge arm, allowing the inductor current of the first inductor L3 to form a freewheeling path through the left bridge arm. During the negative half-cycle boost, when the second lower transistor S8 of the left bridge arm is off, the inductor current of the second inductor L4 also needs to freewheel. The controller turns on the first upper transistor S5 of the right bridge arm, allowing the inductor current of the second inductor L4 to form a freewheeling path through the right bridge arm, thus ensuring the continuity of the inductor current. Under light load conditions, the inductor current amplitude is small. If a synchronous freewheeling path is not provided, the inductor current will remain non-zero, causing distortion of the output voltage near the zero-crossing point. Therefore, during the lower transistor's off period, the upper transistor or an anti-parallel diode provides a freewheeling path, allowing the inductor current to naturally return to zero and ensuring the normal zero-crossing process of the sine wave.
[0045] Please see the appendix Figure 1 The first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 are all power switching devices used to control the opening and closing of the corresponding bridge arms.
[0046] Specifically, the power switching devices, such as the first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8, can realize the opening and closing of the corresponding bridge arms, thereby controlling the conduction state and current flow of each bridge arm.
[0047] Please see the appendix Figure 1 The AC output voltage Vac is acquired through a sampling circuit connected between Vacl and Vacn.
[0048] Specifically, the inverter incorporates a voltage sampling circuit connected between Vacl and Vacln to acquire the AC output voltage Vac. This sampling circuit converts Vac into a signal that the controller can process and sends the sampled value to the voltage loop in each PWM cycle. The voltage loop generates a reference current Iref based on the deviation between the sampled Vac and the voltage reference value. The current loop adjusts the PWM control of each bridge arm switch based on Iref, causing the output voltage Vac to gradually converge to the target value within consecutive PWM cycles, thus achieving periodic adjustment of the output voltage amplitude. Through real-time sampling and closed-loop control of Vac, the inverter can adjust its output in a timely manner according to the operating status, ensuring that the AC output voltage changes stably with the set reference. In this way, the detection, adjustment, and updating of the AC output voltage can be completed within each PWM cycle, enabling the system to adjust the boost ratio and output waveform in real time according to load conditions and operating status.
[0049] The output voltage Vac is acquired by differential sampling across Vacl and Vacn, instead of sampling to ground, to avoid DC bias introduced by changes in the state of the bridge arm switches, thus maintaining symmetry at the zero-crossing point of the output voltage.
[0050] Please see the appendix Figure 1 The first inductor L3 participates in the boost during the positive half-cycle of the output voltage, and the second inductor L4 participates in the boost during the negative half-cycle of the output voltage.
[0051] Specifically, during the positive half-cycle of the output voltage, the first inductor L3, in conjunction with the left bridge arm, forms a boost circuit. During the positive half-cycle, the controller performs PWM control on the second upper transistor S7 and the second lower transistor S8 of the left bridge arm, causing the first inductor L3 to complete the energy storage and dissipation process in each PWM cycle, thereby regulating the potential change of the output node Vacl of the left bridge arm. During the negative half-cycle of the output voltage, the second inductor L4, in conjunction with the right bridge arm, forms a boost circuit. During the negative half-cycle, the controller performs PWM control on the first upper transistor S5 and the first lower transistor S6 of the right bridge arm, causing the second inductor L4 to complete the energy storage and dissipation process, thereby regulating the potential change of the output node Vacn of the right bridge arm. By driving L3 and L4 to participate in the boost circuit during the positive and negative half-cycles respectively, the AC output voltage Vac achieves bipolar regulation capability in a single-stage structure, meeting the requirements of AC output.
[0052] Please see the appendix Figure 1 The first filter capacitor is connected between the output node Vacl of the left bridge arm and the positive terminal of the DC bus, and the second filter capacitor is connected between the output node Vacn of the right bridge arm and the positive terminal of the DC bus.
[0053] Specifically, the inverter is equipped with a first filter capacitor and a second filter capacitor. The first filter capacitor is connected between the left bridge arm output node Vacl and the positive terminal of the DC bus, and the second filter capacitor is connected between the right bridge arm output node Vacn and the positive terminal of the DC bus. This arrangement provides each bridge arm output node with a capacitor buffer path relative to the DC bus. When the bridge arm switches perform PWM modulation, the switching on and off of the second upper transistor S7 and the second lower transistor S8 of the left bridge arm causes a voltage change in the left bridge arm output node Vacl. The first filter capacitor absorbs the high-frequency voltage component of this node. Similarly, the switching on and off of the first upper transistor S5 and the first lower transistor S6 of the right bridge arm causes a voltage change in the right bridge arm output node Vacn. The second filter capacitor absorbs the high-frequency voltage component of this node, thus maintaining a relatively stable potential change for both output nodes during modulation. Therefore, when the bridge arm switches perform PWM modulation, the filter capacitors can absorb the high-frequency components of the node voltage, making the potential changes of Vacl and Vacn more stable. The filter capacitor participates in smoothing the node voltage during both the positive and negative half-cycles, ensuring that the differential output voltage Vac remains continuously controllable during inductor boosting and bridge arm switching. Operators can select the capacitor capacity and type according to the actual power rating to meet the corresponding voltage stress and ripple current requirements.
[0054] This filter capacitor uses AC output lines L and N to filter VBUS+ separately, instead of the traditional boost to filter VBUS-. This allows the voltage across the filter capacitor to be mainly the change in the AC output node voltage, rather than the DC bus voltage, thus reducing the voltage rating requirement for the capacitor.
[0055] Please see the appendix Figure 1 The first end of the first inductor L3 is connected to the output node Vacl of the left bridge arm, and the first end of the second inductor L4 is connected to the output node Vacn of the right bridge arm.
[0056] Specifically, since Vacl and Vacn are the switching nodes of the left and right bridge arms, respectively, when the bridge arm switches switch according to the PWM signal output by the controller, the potentials of the two nodes change between the DC bus potential and the reference potential depending on the bridge arm state. During the positive half-cycle, the first inductor L3 is connected to Vacl. By PWM modulation of the second upper transistor S7 and the second lower transistor S8 of the left bridge arm, L3 completes the energy storage and dissipation process in each PWM cycle, thereby adjusting the potential of Vacl relative to Vacn and achieving positive voltage boost. L4, connected to Vacn, does not participate in the voltage boost in this half-cycle. During the negative half-cycle, the second inductor L4 is connected to Vacn. By PWM modulation of the first upper transistor S5 and the first lower transistor S6 of the right bridge arm, L4 completes the energy storage and dissipation process in each PWM cycle, thereby adjusting the potential of Vacn relative to Vacl and achieving negative voltage boost. By directly connecting the first end of the inductor to the switching node, the inductor can participate in energy storage and release during the PWM switching process of the bridge arm, thereby enabling different inductors and corresponding bridge arms to form a boost circuit in the positive and negative half-cycles.
[0057] A method of using a single-stage boost inverter includes the following steps:
[0058] S1. Collect the AC output voltage Vac between Vacl and Vacn;
[0059] S2. Generate a reference current Iref based on Vac.
[0060] S3. Calculate the PWM duty cycle of the first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 based on Iref;
[0061] S4. During the positive half-cycle, control the first upper transistor S5 to be turned on and the first lower transistor S6 to be turned off, so that the first inductor L3 and the left bridge arm form a boost circuit.
[0062] S5. During the negative half-cycle, control the second upper transistor S7 to be turned on and the second lower transistor S8 to be turned off, so that the second inductor L4 and the right bridge arm form a boost circuit.
[0063] S6. When the first lower transistor S6 is turned off, the second upper transistor S7 is turned on to form a freewheeling path for the first inductor L3.
[0064] S7. When the second lower tube S8 is turned off, the first upper tube S5 is turned on to form a freewheeling path for the second inductor L4.
[0065] S8. Generate the AC output voltage Vac based on the potential difference between Vacl and Vacn.
[0066] Specifically, through the above steps, the inverter can complete output voltage acquisition, voltage regulation, current regulation, and positive and negative half-cycle boost control in a single-stage topology. This allows the first inductor L3 and the second inductor L4 to participate in the boost during the positive and negative half-cycles, respectively, and forms energy storage, energy release, and freewheeling paths through the switching of the bridge arms, thereby achieving bipolar regulation of the AC output voltage Vac. Furthermore, during operation, the system continuously updates the PWM duty cycle of each bridge arm switch based on the reference voltage and reference current, ensuring that the AC output voltage Vac changes with the given value and maintains a stable electromagnetic energy conversion process within continuous PWM cycles. This single-stage boost inverter method allows the inverter to achieve coordinated control of boost and inversion without the need for a separate boost stage, enabling the AC output to generate the required voltage waveform according to the set reference, meeting the AC output requirements of a single-stage structure.
[0067] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A single-stage boost inverter, comprising a left bridge arm, a right bridge arm, a first inductor L3, a second inductor L4, a controller, a first filter capacitor, and a second filter capacitor, characterized in that, The left bridge arm includes a second upper transistor S7 and a second lower transistor S8. The connection point of the second upper transistor S7 and the second lower transistor S8 forms the output node Vacl of the left bridge arm. The right bridge arm includes a first upper transistor S5 and a first lower transistor S6. The connection point of the first upper transistor S5 and the first lower transistor S6 forms the output node Vacn of the right bridge arm. The controller is used to generate PWM drive signals for each switching transistor of the left and right bridge arms. During the positive half-cycle of the output voltage, the controller controls the first upper transistor S5 to turn on and the first lower transistor S6 to turn off, and controls the second upper transistor S7 and the second lower transistor S8 to perform switching control, so that the first inductor L3 and the left bridge arm form a boost circuit. During the negative half-cycle of the output voltage, the controller controls the second upper transistor S7 to turn on and the second lower transistor S8 to turn off, and controls the first upper transistor S5 and the first lower transistor S6 to perform switching control, so that the second inductor L4 and the right bridge arm form a boost circuit. Vacl and Vacn constitute the AC output terminal of the inverter, and the AC output terminal voltage Vac is the potential difference between Vacl and Vacn.
2. The single-stage boost inverter according to claim 1, characterized in that, The controller includes a voltage loop and a current loop. The voltage loop generates a reference current Iref based on the AC output voltage Vac, and the current loop generates PWM drive signals for each switch transistor in the left and right bridge arms based on the reference current Iref.
3. A single-stage boost inverter according to claim 1, characterized in that, The voltage loop acquires the AC output voltage Vac in each PWM cycle and updates the PWM duty cycle within that PWM cycle.
4. A single-stage boost inverter according to claim 1, characterized in that, During the positive half-cycle boost, when the first lower transistor S6 is in the off state, the controller controls the second upper transistor S7 to turn on, so that the inductor current of the first inductor L3 forms a freewheeling path through the left bridge arm. During the negative half-cycle boost, when the second lower transistor S8 is in the off state, the controller controls the first upper transistor S5 to turn on, so that the inductor current of the second inductor L4 forms a freewheeling path through the right bridge arm.
5. A single-stage boost inverter according to claim 1, characterized in that, The first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 are all power switching devices used to control the opening and closing of the corresponding bridge arms.
6. A single-stage boost inverter according to claim 1, characterized in that, The AC output voltage Vac is acquired by a sampling circuit connected between Vacl and Vacn.
7. A single-stage boost inverter according to claim 1, characterized in that, The first inductor L3 participates in the boost during the positive half-cycle of the output voltage, and the second inductor L4 participates in the boost during the negative half-cycle of the output voltage.
8. A single-stage boost inverter according to claim 1, characterized in that, The first filter capacitor is connected between the output node Vacl of the left bridge arm and the positive terminal of the DC bus, and the second filter capacitor is connected between the output node Vacn of the right bridge arm and the positive terminal of the DC bus.
9. A single-stage boost inverter according to claim 1, characterized in that: The first end of the first inductor L3 is connected to the left bridge arm output node Vacl, and the first end of the second inductor L4 is connected to the right bridge arm output node Vacn.
10. A method of using a single-stage boost inverter, characterized in that, For a single-stage boost inverter according to any one of claims 1-9, the method comprises the following steps: S1. Collect the AC output voltage Vac between Vacl and Vacn; S2. Generate a reference current Iref based on Vac. S3. Calculate the PWM duty cycle of the first upper transistor S5, the first lower transistor S6, the second upper transistor S7, and the second lower transistor S8 based on Iref; S4. During the positive half-cycle, control the first upper transistor S5 to be turned on and the first lower transistor S6 to be turned off, so that the first inductor L3 and the left bridge arm form a boost circuit. S5. During the negative half-cycle, control the second upper tube S7 to be turned on and the second lower tube S8 to be turned off, so that the second inductor L4 and the right bridge arm form a boost circuit. S6. When the first lower transistor S6 is turned off, the second upper transistor S7 is turned on to form a freewheeling path for the first inductor L3. S7. When the second lower tube S8 is turned off, the first upper tube S5 is turned on to form a freewheeling path for the second inductor L4. S8. Generate the AC output voltage Vac based on the potential difference between Vacl and Vacn.