Method for manufacturing a light emitting diode chip
By etching the mesa and isolation trench in a single step during the fabrication of LED chips, the problems of high process cost and misalignment in existing technologies are solved, achieving a highly efficient etching process and high-quality LED chip production.
Patent Information
- Application Number
- CN202610145668.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-02
- Publication Date
- 2026-06-23
AI Technical Summary
In the existing technology for manufacturing LED chips, the mesa and isolation trench are processed by two photolithography processes, resulting in high process costs and easy misalignment.
A transparent conductive layer and an etch barrier layer are sequentially deposited on one side of the epitaxial layer. A mesa and isolation trench are formed by a single etching process. The transparent conductive layer serves to conduct electricity and block etching, while the etch barrier layer provides additional etching protection. The photoresist layer is used as a mask to preferentially etch the epitaxial layer to create a height difference.
It simplifies the etching process, reduces manufacturing costs, avoids alignment deviations, and improves the quality and optical crosstalk performance of LEDs.
Smart Images
Figure CN122269885A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a light-emitting diode chip. Background Technology
[0002] A light-emitting diode (LED) chip is a semiconductor device that can convert electrical energy into light energy.
[0003] In related technologies, during the fabrication of light-emitting diode chips, mesa (mesa) and isolation trench (ISO) need to be etched on the epitaxial layer. The mesa and isolation trench are obtained through two photolithography processes.
[0004] However, since the platform and isolation trench are processed through two photolithography processes, the process cost is high, and the alignment of the two photolithography processes is prone to deviation. Summary of the Invention
[0005] This disclosure provides a method for fabricating a light-emitting diode (LED) chip, which simplifies the etching process and reduces manufacturing costs. The technical solution is as follows: This disclosure provides a method for fabricating a light-emitting diode (LED) chip, including: Growth epitaxial layer; A transparent conductive layer and an etch barrier layer are sequentially deposited on one side of the epitaxial layer; The transparent conductive layer and the etch barrier layer are patterned to expose a portion of the epitaxial layer; A photoresist layer is prepared on the side of the etch barrier layer opposite to the transparent conductive layer, such that the photoresist layer covers a portion of the etch barrier layer; The exposed transparent conductive layer, etching barrier layer, and epitaxial layer are etched to form mesas and isolation trenches.
[0006] In one implementation of this disclosure, a transparent conductive layer and an etch barrier layer are sequentially deposited on one side of the epitaxial layer, including: A first deposition thickness and a second deposition thickness are determined, wherein the first deposition thickness is the deposition thickness of the transparent conductive layer, and the second deposition thickness is the deposition thickness of the etch barrier layer; The transparent conductive layer is deposited according to the first deposition thickness; The etching barrier layer is deposited according to the second deposition thickness.
[0007] In one implementation of this disclosure, determining the first deposition thickness and the second deposition thickness includes: The first deposition thickness is set to 30~150nm; The total deposition thickness is determined, which is the sum of the first deposition thickness and the second deposition thickness; The second deposition thickness is calculated based on the total deposition thickness and the first deposition thickness.
[0008] In one implementation of this disclosure, determining the total deposition thickness includes: The depth difference between the platform and the isolation trench, the first etch selectivity ratio and the second etch selectivity ratio are determined. The first etch selectivity ratio is the etch selectivity ratio between the transparent conductive layer and the epitaxial layer, and the second etch selectivity ratio is the etch selectivity ratio between the etch barrier layer and the epitaxial layer. The total deposition thickness is determined based on the depth difference, the first etching selectivity ratio, and the second etching selectivity ratio.
[0009] In one implementation of this disclosure, the deposition of an etch barrier layer includes: A second layer of SiO2, Al2O3, Si3N4, or AlN is deposited on the side of the transparent conductive layer opposite to the epitaxial layer, and serves as the etching barrier layer.
[0010] In one implementation of this disclosure, etching the exposed transparent conductive layer, etching barrier layer, and epitaxial layer includes: A mixture of Cl2 and BCl3 gases was used as the etching gas. The etching process is carried out in three stages in sequence to form mesa and isolation trenches. The three stages of etching are performed continuously.
[0011] In one implementation of this disclosure, etching is performed in three stages sequentially, including: The first stage of etching is performed, etching the exposed etch barrier layer and the epitaxial layer until the exposed etch barrier layer is completely etched away.
[0012] In one implementation of this disclosure, etching is performed in three stages sequentially, including: A second stage of etching is performed to etch the exposed transparent conductive layer and the epitaxial layer until the exposed transparent conductive layer is completely etched away, thereby forming the height difference between the mesa and the isolation trench.
[0013] In one implementation of this disclosure, etching is performed in three stages sequentially, including: A third stage of etching is performed to etch the exposed epitaxial layer to form the mesa and the isolation trench.
[0014] In one implementation of this disclosure, after forming the platform and the isolation trench, the following steps are included: Remove the photoresist layer; The remaining etching barrier layer is etched away.
[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: According to the fabrication method provided in this disclosure, during the fabrication of a light-emitting diode chip, a transparent conductive layer and an etch barrier layer are sequentially deposited on one side of the epitaxial layer. The transparent conductive layer serves both to achieve its own conductivity and to act as an etch barrier. However, due to the limited thickness of the transparent conductive layer, its etch barrier function alone is insufficient to meet the etching requirements. Therefore, an etch barrier layer is deposited on one side of the transparent conductive layer to provide sufficient etch barrier effect. After the transparent conductive layer and the etch barrier layer are deposited, they are patterned to expose a portion of the epitaxial layer, allowing this portion to be preferentially etched. Then, a photoresist layer is fabricated on the side of the etch barrier layer facing away from the transparent conductive layer. The photoresist layer covers the portion of the etch barrier layer, thus acting as a photomask. Finally, etching is performed. During the etching process, the etch barrier layer and a portion of the exposed epitaxial layer are etched first, forming an isolation trench after this portion of the epitaxial layer is etched away. After the etch barrier layer is removed, the underlying transparent conductive layer is etched, and the etching of the exposed portion of the epitaxial layer continues. After the transparent conductive layer is removed, the etching of the underlying epitaxial layer begins, forming a mesa after this portion of the epitaxial layer is etched away. Because a portion of the exposed epitaxial layer has already been etched, a height difference is created between the mesa and the isolation trench. After etching is completed, a mesa and isolation trench with a height difference are formed.
[0016] In other words, mesa and isolation trenches can be formed in a single etching process, effectively simplifying the etching procedure and reducing manufacturing costs. Furthermore, since the mesa and isolation trenches are formed in a single etching operation, there is no misalignment, thus improving the quality of the LED. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of this disclosure; Figure 2This is a flowchart of another method for fabricating a light-emitting diode chip provided in this disclosure embodiment; Figure 3 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 7 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 9 This is a test diagram of the optical crosstalk effect of a light-emitting diode chip without isolation trench in related technologies; Figure 10 This is a test diagram of the optical crosstalk effect of the light-emitting diode chip provided in the embodiments of this disclosure.
[0019] Icon labels: 10. Epitaxial layer; 110. N-type semiconductor layer; 120. Active layer; 130. P-type semiconductor layer; 20. Transparent conductive layer; 30. Etching barrier layer; 40. Photoresist layer; 50. Countertop; 60. Isolation trench; 70. Substrate. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0021] ADB (Adaptive Driving Beam) is a new type of vehicle lighting system that has been widely used in automobiles, especially in new energy vehicles.
[0022] In related technologies, the main light-emitting device of ADB automotive lights is a light-emitting diode (LED) chip. During the fabrication of the LED chip, a mesa (mesa) and an isolation trench (ISO) need to be etched on the epitaxial layer. The mesa and isolation trench are obtained through two photolithography processes.
[0023] However, since the platform and isolation trench are processed through two photolithography processes, the process cost is high, and the alignment of the two photolithography processes is prone to deviation.
[0024] To address the aforementioned technical problems, this disclosure provides a method for fabricating a light-emitting diode (LED) chip. Figure 1 For a flowchart of the preparation method, see [link to flowchart]. Figure 1 In this embodiment, the preparation method includes: Step 101: Grow epitaxial layer 10.
[0025] Step 102: Pattern the transparent conductive layer 20 and the etch barrier layer 30 to expose a portion of the epitaxial layer 10.
[0026] Step 103: Prepare a photoresist layer 40 on the side of the etch barrier layer 30 that faces away from the transparent conductive layer 20, so that the etch barrier layer 30 is partially covered by the photoresist layer 40.
[0027] Step 104: Etch the exposed transparent conductive layer 20, the barrier layer 30, and the epitaxial layer 10 to form the mesa 50 and the isolation trench 60.
[0028] According to the fabrication method provided in this embodiment, during the fabrication of a light-emitting diode chip, a transparent conductive layer 20 and an etch barrier layer 30 are sequentially deposited on one side of the epitaxial layer 10. The transparent conductive layer 20 serves both to conduct electricity and to act as an etch barrier. However, due to the limited thickness of the transparent conductive layer 20, its etch barrier function alone is insufficient to meet the etching requirements. Therefore, an etch barrier layer 30 is deposited on one side of the transparent conductive layer 20 to provide sufficient etch barrier effect. After the transparent conductive layer 20 and the etch barrier layer 30 are deposited, they are patterned to expose a portion of the epitaxial layer 10, allowing this portion to be preferentially etched. Then, a photoresist layer 40 is prepared on the side of the etch barrier layer 30 facing away from the transparent conductive layer 20, so that the portion of the etch barrier layer 30 covered by the photoresist layer 40, i.e., the photoresist layer 40, acts as a mask. Finally, etching is performed. During the etching process, the etch barrier layer 30 and a portion of the exposed epitaxial layer 10 are etched first, and this portion of the epitaxial layer 10 forms an isolation trench 60 after etching. After the etch barrier layer 30 is etched away, the transparent conductive layer 20 below is etched, and the portion of the exposed epitaxial layer 10 is etched again. After the transparent conductive layer 20 is etched away, the epitaxial layer 10 below is etched, and this portion of the epitaxial layer 10 forms a mesa 50 after etching. Since the portion of the exposed epitaxial layer 10 has already been etched, a height difference is formed between the mesa 50 and the isolation trench 60. After etching is completed, a platform 50 with varying elevations and an isolation trench 60 are formed.
[0029] In other words, the mesa 50 and the isolation trench 60 can be formed in a single etching process, effectively simplifying the etching procedure and reducing process costs. Furthermore, since the mesa 50 and the isolation trench 60 are formed in a single etching operation, there will be no alignment misalignment, thus improving the quality of the light-emitting diode.
[0030] Figure 2 For a flowchart of another method for fabricating a light-emitting diode chip provided in this disclosure embodiment, please refer to [link to flowchart]. Figure 2 In this embodiment, the preparation method includes: Step 201: Provide a substrate 70.
[0031] For example, the substrate 70 is a sapphire substrate, a silicon wafer substrate, or other light-emitting diode chip substrate material.
[0032] Step 202: Prepare epitaxial layer 10 (see...) Figure 3 ).
[0033] For example, metal-organic chemical vapor deposition (MOCVD) is used to sequentially grow an N-type semiconductor layer 110, an active layer 120, and a P-type semiconductor layer 130.
[0034] For example, the N-type semiconductor layer 110 is an N-type GaN layer, the active layer 120 is a quantum well layer, and the P-type semiconductor layer 130 is a P-type GaN layer.
[0035] Step 203: Deposit a transparent conductive layer 20 on one side of the epitaxial layer 10.
[0036] In this embodiment, step 203 includes the following steps: Step 2031: Determine the first deposition thickness. The first deposition thickness is the deposition thickness of the transparent conductive layer 20.
[0037] For example, the first deposition thickness is set to 30~150nm.
[0038] In the above implementation, the first deposition thickness should be primarily determined by the functionality of the transparent conductive layer 20, while its etching-blocking effect is secondary. This is because the transparent conductive layer 20 should not be designed to be too thick, and a thinner transparent conductive layer 20 has a weaker etching-blocking effect. Therefore, designing the first deposition thickness primarily based on the functionality of the transparent conductive layer 20 can effectively ensure its functionality.
[0039] Of course, if there is a certain design margin, and the first deposition thickness meets the functionality of the transparent conductive layer 20, then the etching blocking effect can be considered to make further design modifications to the first deposition thickness.
[0040] For example, when the first deposition thickness is 100~130nm, it can meet its own functionality. Therefore, when designing, the design considerations for the blocking effect can only be carried out within 100~130nm, so as not to affect the functionality of the transparent conductive layer 20 itself.
[0041] Step 2032: Deposit a transparent conductive layer 20 according to the first deposition thickness.
[0042] For example, the transparent conductive layer 20 is an indium tin oxide (ITO) layer, which can be prepared by magnetron sputtering and pulsed laser deposition.
[0043] Step 204: Deposit an etching barrier layer 30 on one side of the transparent conductive layer 20 (see...) Figure 4 ).
[0044] In this embodiment, step 204 includes the following steps: Step 2041: Determine the second deposition thickness. The second deposition thickness is the deposition thickness of the etch barrier layer 30.
[0045] First, determine the total deposition thickness, which is the sum of the first and second deposition thicknesses.
[0046] Then, the second deposition thickness is calculated based on the total deposition thickness and the first deposition thickness.
[0047] In the above implementation, the first deposition thickness has been determined by step 2031. Since the total deposition thickness is the sum of the first deposition thickness and the second deposition thickness, the second deposition thickness can be calculated by subtracting the first deposition thickness from the total deposition thickness.
[0048] In this embodiment, the total deposition thickness is determined through the following steps: First, determine the depth difference between the platform and the isolation trench 60, the first etching selectivity ratio, and the second etching selectivity ratio.
[0049] Then, the total deposition thickness is determined based on the depth difference, the first etch selectivity ratio, and the second etch selectivity ratio.
[0050] The first etch selectivity ratio is the etch selectivity ratio between the transparent conductive layer 20 and the epitaxial layer 10, and the second etch selectivity ratio is the etch selectivity ratio between the etch barrier layer 30 and the epitaxial layer 10.
[0051] The etch selectivity ratio refers to the ratio of the etching rate of the mask material to the etching rate of the target material. For example, if the transparent conductive layer 20 is the mask material and the epitaxial layer 10 is the target material, the first etch selectivity ratio is the ratio of the etching rate of the transparent conductive layer 20 to the etching rate of the epitaxial layer 10. If the etch barrier layer 30 is the mask material and the epitaxial layer 10 is the target material, the second etch selectivity ratio is the ratio of the etching rate of the etch barrier layer 30 to the etching rate of the epitaxial layer 10.
[0052] For example, the first etch selectivity ratio is 1:9 and the second etch selectivity ratio is 1:3.
[0053] When the etching time is constant, the etching depth is positively correlated with the etching rate. That is, the faster the etching rate, the greater the etching depth. By utilizing the etching rate difference between the transparent conductive layer 20, the etch barrier layer 30, and the epitaxial layer 10, it is possible to create a height difference between the mesa and the isolation trench 60 on the epitaxial layer 10 by sacrificing a smaller thickness of etching the transparent conductive layer 20 and the etch barrier layer 30.
[0054] Therefore, by reverse derivation, the total deposition thickness of the transparent conductive layer 20 and the etch barrier layer 30 can be determined by the depth difference, the first etch selectivity ratio, and the second etch selectivity ratio.
[0055] For example, if the depth difference is 12 (this is just an example value, and the unit is not limited), the first etch selectivity is 1:9, and the second etch selectivity is 1:3, then the total deposition thickness of the transparent conductive layer 20 and the etch barrier layer 30 is 1. That is, within the same etching time, the transparent conductive layer 20 and the etch barrier layer 30, both with a thickness of 1, are etched away, and the epitaxial layer 10 is etched away by a thickness of 12.
[0056] It is worth noting that the values mentioned in the examples above are all ratios, and do not involve depth units or thickness units.
[0057] Step 2042: Deposit an etch barrier layer 30 according to the second deposition thickness.
[0058] For example, the etching barrier layer 30 is one of SiO2 layer, Al2O3 layer, Si3N4 layer, and AlN layer.
[0059] In this embodiment, the etching barrier layer 30 is a SiO2 layer, and the second deposition thickness is 200~2000nm.
[0060] It is worth noting that since different materials have different etching rates, if the etching barrier layer 30 is made of other materials, the etching rate will change accordingly, and the second deposition thickness will also change accordingly, which will not be elaborated here.
[0061] Step 205: Pattern the transparent conductive layer 20 and the etch barrier layer 30 to expose a portion of the epitaxial layer 10 (see...) Figure 5 ).
[0062] For example, the transparent conductive layer 20 and the etch barrier layer 30 are patterned by photolithography using an inductively coupled plasma (ICP) process.
[0063] In the above implementation, by using the patterned transparent conductive layer 20 and the etch barrier layer 30, a portion of the epitaxial layer 10 can be exposed. This portion of the epitaxial layer 10 is the epitaxial layer 10 that is preferentially etched in subsequent processes, corresponding to the isolation trench 60.
[0064] Step 206: Prepare a photoresist layer 40 on the side of the etch barrier layer 30 facing away from the transparent conductive layer 20, such that the etch barrier layer 30 is partially covered by the photoresist layer 40 (see...). Figure 6 ).
[0065] In the above implementation, after the photoresist is coated, it is photolithographically developed to form a photoresist layer 40.
[0066] Step 207: Etch the exposed transparent conductive layer 20, the etch barrier layer 30, and the epitaxial layer 10 to form the mesa 50 and the isolation trench 60 (see...) Figure 7 ).
[0067] For example, a mixture of Cl2 gas and BCl3 gas is used as the etching gas, and three stages of etching are performed sequentially to form a mesa 50 and an isolation trench 60. The three stages of etching are performed continuously.
[0068] It is worth noting that although the etching is divided into three stages, these three stages are carried out continuously, and in essence, it is a complete etching process, that is, one etching operation.
[0069] Step 2071: Perform the first stage of etching, etching the exposed etch barrier layer 30 and epitaxial layer 10 until the exposed etch barrier layer 30 is completely etched away.
[0070] In the first stage of etching, since the etching barrier layer 30 is located above the transparent conductive layer 20, only the etching barrier layer 30 and the exposed epitaxial layer 10 are etched simultaneously.
[0071] Step 2072: Perform the second stage of etching, etching the exposed transparent conductive layer 20 and epitaxial layer 10 until the exposed transparent conductive layer 20 is completely etched away, so as to form the height difference between the mesa 50 and the isolation trench 60.
[0072] In the second stage of etching, since the etching barrier layer 30 has been etched away in the first stage of etching, the transparent conductive layer 20 is exposed, and the transparent conductive layer 20 and the exposed epitaxial layer 10 are etched simultaneously.
[0073] Step 2073: Perform the third stage of etching to etch the exposed epitaxial layer 10 to form mesa 50 and isolation trench 60.
[0074] In the third stage of etching, since the transparent conductive layer 20 has already been etched away in the second stage, the epitaxial layer 10 beneath the transparent conductive layer 20 is also exposed, and the exposed epitaxial layer 10 is simultaneously etched. Because all the epitaxial layers 10 are etched simultaneously, the height difference between the mesa 50 and the isolation trench 60 can be maintained until the third stage of etching is completed.
[0075] Step 208: Remove the photoresist layer 40 and etch away the remaining etch stop layer 30 (see...) Figure 8 ).
[0076] The light-emitting diode chip prepared by the preparation method provided in this disclosure has at least the following beneficial effects: 1. The etching of the 50-degree plateau and the etching of the isolation trench are combined into one photolithography step, saving the cost of one photolithography step.
[0077] 2. It avoids the problem of misalignment in the 60-degree photolithography of the isolation trench.
[0078] 3. The size of the isolation trench 60 has been maximized to effectively improve the prevention of light crosstalk and enhance contrast.
[0079] Figure 9 This is a test diagram showing the optical crosstalk effect of a light-emitting diode chip without isolation trench 60 in related technologies. Figure 10 This is a test diagram of the optical crosstalk effect of the light-emitting diode chip prepared in the embodiments of this disclosure.
[0080] exist Figure 9 In the figure, sum=54.51%, at1µA, refers to the sum of the brightness percentages of the 24 LED chips (excluding the central LED chip) in the surrounding area when a current of 1µA is applied, which is 54.51%. By comparing the sum of brightness percentages under different currents, the uniformity of brightness distribution can be analyzed. The larger the sum of brightness percentages, the more severe the optical crosstalk. Figure 10 and Figure 9 The same applies, so I won't repeat it here.
[0081] Combination Figure 9 and Figure 10As can be seen, the light crosstalk effect of the LED chip prepared in the present invention is significantly better than that of the LED chip without isolation trench in the related art.
[0082] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0083] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A method for fabricating a light-emitting diode chip, characterized in that, include: Growth of epitaxial layer (10); A transparent conductive layer (20) and an etch barrier layer (30) are sequentially deposited on one side of the epitaxial layer (10). The transparent conductive layer (20) and the etch barrier layer (30) are patterned to expose a portion of the epitaxial layer (10). A photoresist layer (40) is prepared on the side of the etch barrier layer (30) opposite to the transparent conductive layer (20), such that the photoresist layer (40) covers a portion of the etch barrier layer (30). The exposed transparent conductive layer (20), etching barrier layer (30) and epitaxial layer (10) are etched to form mesa (50) and isolation trench (60).
2. The preparation method according to claim 1, characterized in that, A transparent conductive layer (20) and an etch barrier layer (30) are sequentially deposited on one side of the epitaxial layer (10), including: Determine a first deposition thickness and a second deposition thickness, wherein the first deposition thickness is the deposition thickness of the transparent conductive layer (20) and the second deposition thickness is the deposition thickness of the etch barrier layer (30); The transparent conductive layer (20) is deposited according to the first deposition thickness. The etching barrier layer (30) is deposited according to the second deposition thickness.
3. The preparation method according to claim 2, characterized in that, Determining the first and second deposition thicknesses includes: The first deposition thickness is set to 30~150nm; The total deposition thickness is determined, which is the sum of the first deposition thickness and the second deposition thickness; The second deposition thickness is calculated based on the total deposition thickness and the first deposition thickness.
4. The preparation method according to claim 3, characterized in that, Determine the total deposition thickness, including: Determine the depth difference between the mesa (50) and the isolation trench (60), the first etch selectivity ratio and the second etch selectivity ratio, wherein the first etch selectivity ratio is the etch selectivity ratio between the transparent conductive layer (20) and the epitaxial layer (10), and the second etch selectivity ratio is the etch selectivity ratio between the etch barrier layer (30) and the epitaxial layer (10); The total deposition thickness is determined based on the depth difference, the first etching selectivity ratio, and the second etching selectivity ratio.
5. The preparation method according to claim 1, characterized in that, The deposition etch barrier layer (30) includes: A second-thickness SiO2 layer, Al2O3 layer, Si3N4 layer, or AlN layer is deposited on the side of the transparent conductive layer (20) opposite to the epitaxial layer (10) and serves as the etching barrier layer (30).
6. The preparation method according to claim 1, characterized in that, Etching the exposed transparent conductive layer (20), etching barrier layer (30), and epitaxial layer (10) includes: A mixture of Cl2 and BCl3 gases was used as the etching gas. The etching is performed in three stages in sequence to form a mesa (50) and an isolation trench (60), and the three stages of etching are performed continuously.
7. The preparation method according to claim 6, characterized in that, The etching process is performed in three stages, including: The first stage of etching is performed to etch the exposed etch barrier layer (30) and the epitaxial layer (10) until the exposed etch barrier layer (30) is completely etched away.
8. The preparation method according to claim 6, characterized in that, The etching process is performed in three stages, including: A second stage of etching is performed to etch the exposed transparent conductive layer (20) and the epitaxial layer (10) until the exposed transparent conductive layer (20) is completely etched away to form the height difference between the mesa (50) and the isolation trench (60).
9. The preparation method according to claim 6, characterized in that, The etching process is performed in three stages, including: A third stage of etching is performed to etch the exposed epitaxial layer (10) to form the mesa (50) and the isolation trench (60).
10. The preparation method according to claim 1, characterized in that, After forming the platform (50) and the isolation trench (60), including: Remove the photoresist layer (40); The remaining etching barrier layer (30) is etched away.