A multi-chip optical interconnect architecture and method of manufacture

By fabricating a double-layer optical waveguide on a glass substrate and using an arrayed waveguide grating router, the expansion requirements for optical interconnection between multiple chips were solved, achieving efficient multi-chip optoelectronic interconnection and improving the system's transmission performance and heat dissipation capabilities.

CN122284022BActive Publication Date: 2026-07-24CENT SOUTH UNIV
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Patent Information

Application Number
CN202610758093.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-05-29
Publication Date
2026-07-24
Estimated Expiration
2046-05-29

AI Technical Summary

Technical Problem

Existing optoelectronic co-packaging structures are insufficient to meet the expansion requirements of multi-chip interconnection. Traditional electrical interconnects suffer from problems such as limited bandwidth, severe signal crosstalk, decreased signal integrity, and increased power consumption. Existing optical interconnect technologies have failed to effectively solve the problem of all-optical interconnection between multiple chips.

Method used

A multi-chip optical interconnect architecture based on a glass substrate is adopted. By fabricating a double-layer optical waveguide structure on the glass substrate and combining it with an arrayed waveguide grating router (AWGR), controllable electromigration and coupling of three-dimensional optical waveguides are achieved, avoiding cross-over of optical waveguides. By adopting a multi-layer optical waveguide architecture and a bidirectional AWGR routing structure, full interconnection is achieved and the number of optical waveguides is reduced.

Benefits of technology

It achieves high-bandwidth, low-loss optical interconnection between multiple chips, solves the problems of signal interference and loss, improves the system transmission rate and reduces power consumption, and is suitable for high-performance computing and high-speed data exchange.

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Abstract

The application belongs to the field of advanced packaging technology, and particularly relates to a multi-chip optical interconnection architecture and a manufacturing method. The manufacturing method comprises the following steps: S1, plating a hard mask on a substrate surface; S2, spin-coating a photoresist on the hard mask, pre-baking, aligning and exposing, developing, post-baking, transferring a lower layer circuit to the hard mask, and removing the photoresist and cleaning; S3, manufacturing a surface layer ion exchange optical waveguide; S4, printing a matrix electrode and a circuit on the substrate surface to form a controllable electric field and a lower layer optical waveguide; S5, plating a film on the substrate surface, photoetching, and etching to form an upper layer optical waveguide; S6, laying the photonic integrated chip and an arrayed waveguide grating router on the substrate surface, and aligning and coupling the photonic integrated chip and the arrayed waveguide grating router with the upper and lower layer optical waveguides; and S7, depositing a cladding layer on the substrate surface and polishing to expose the upper surface of the photonic integrated chip. The application can effectively reduce optical path intersection and improve interconnection density, thereby realizing large-bandwidth, low-loss optical interconnection between multi-chips on a chip.
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Citation Information

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