Signal processing system based on heterogeneous processing platform, signal generation and transmission method

CN122285574APending Publication Date: 2026-06-26SICHUAN JIUZHOU ELECTRIC GROUP CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SICHUAN JIUZHOU ELECTRIC GROUP CO LTD
Filing Date
2026-03-30
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

Traditional signal processing systems struggle to balance performance, flexibility, and processing power, and suffer from low data transmission efficiency and insufficient reliability, making them particularly prone to system failure in industrial settings.

Method used

The signal processing system, based on a heterogeneous processing platform, achieves rapid signal generation, accurate processing, and high-speed transmission through the collaborative work of the main control processing module, dedicated signal processing module, digital-to-analog conversion module, analog-to-digital conversion module, and RF front end, combined with multiple bus designs and redundant control.

Benefits of technology

It achieves high-performance, high-flexibility, and high-reliability signal processing, supports rapid switching of multiple modulation methods, reduces hardware costs, and improves the system's anti-interference capability and data transmission accuracy in industrial environments.

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Abstract

This invention relates to the field of electronics and communication technology, and discloses a signal processing system and signal generation and transmission method based on a heterogeneous processing platform. The system includes a host computer, a main control processing module, a dedicated signal processing module, a digital-to-analog converter (DAC) module, an analog-to-digital converter (ADC) module, and a radio frequency (RF) front-end. The main control processing module integrates a programmable logic unit (PLU), a processing system unit, and an on-chip memory module. The host computer is connected to the PLU via a first high-speed external bus and to the processing system unit via a first control bus. The dedicated signal processing module is connected to the PLU via a second high-speed external bus and a second control bus, respectively. Both the PLU and ADC modules are controlled by the PLU, and the output and input terminals of the PLU are connected to the RF front-end. This invention is compatible with processor hardware environments that do not support RapidIO messages, offering high transmission rates and low pin usage.
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