Method of metal interconnection for flexible circuits
By employing overlapping metal pattern design, wet and dry etching techniques, and electroplating processes in flexible circuits, the alignment error and breakage problems in metal interconnects of flexible circuits have been solved, thereby improving the interconnect reliability and signal transmission quality between metal layers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TIANKAI FULAI SENSING (TIANJIN) SEMICONDUCTOR CO LTD
- Filing Date
- 2026-05-28
- Publication Date
- 2026-06-26
AI Technical Summary
During the testing of micro LED chips, the metal interconnects of flexible circuits suffer from problems such as difficulty in aligning interlayer vias, severe side etching during etching, easy breakage of fine lines and contacts, resulting in poor reliability of vertical interconnects between metal layers.
The design employs an overlapping metal pattern, combined with wet and dry etching techniques. By adjusting the ratio of etchant to deionized water and using low-temperature etching, the adhesion of the bonding layer is increased. The serpentine traces and thickness gradient design, along with seed layers and electroplating processes, create thick electrical contact points.
It improves the reliability of vertical interconnects between metal layers, reduces the risk of lateral corrosion and fracture, enhances the interconnect quality and signal transmission quality of flexible circuits, and ensures the reliability and wear resistance of electrical connections.
Smart Images
Figure CN122294657A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of flexible electronics technology, and in particular relates to a metal interconnection method for flexible circuits. Background Technology
[0002] Electroluminescence detection technology is a commonly used detection method. When inspecting micro light-emitting diode (Micro-LED) chips, flexible probes are required to avoid damaging the chips. Flexible circuitry is a key component of flexible probes.
[0003] To improve detection efficiency and facilitate the detection of multiple miniature light-emitting diodes, the internal metal wiring of flexible circuits is relatively dense, presenting the following technical challenges when performing metal interconnection: 1. Interlayer vias are difficult to align, resulting in poor reliability of vertical interconnects between metal layers; 2. Severe lateral etching during the etching process can easily lead to open circuits; 3. Thin wires are prone to breakage; 4. The contacts are thin and easily broken. Summary of the Invention
[0004] This invention provides a metal interconnection method for flexible circuits, which effectively solves the above-mentioned technical problems and overcomes the shortcomings of the prior art.
[0005] The technical solution adopted in this invention is: a metal interconnection method for flexible circuits, comprising the following steps: Coating the first dielectric layer; Deposit the first metal layer and photolithographically pattern the first metal pattern; A second dielectric layer is coated and interlayer vias are photolithographically etched. A second metal layer is deposited and a second metal pattern is photolithographically formed. The second metal pattern overlaps with the first metal pattern to form an overlap region. The width of the overlap region is greater than the diameter of the interlayer via. The overlap width of the overlap region is 0.5 to 80 μm. A third dielectric layer is coated and contact windows are photolithographically etched; Deposition of passivation layer; Fabrication of metal contacts includes: Evaporated seed layer; Electroplated metal contacts are used to make the metal contacts protrude from the contact window.
[0006] Furthermore, both the first metal layer and the second metal layer include an adhesion layer and a conductive layer. The adhesion layer is made of Cr, Ti, Ta, W, NiCr or TiW, and the conductive layer is made of Au, Cu, Ag, Al, Pt or Pd. The thickness of the first metal layer and the second metal layer is 11 to 1100 nm.
[0007] Furthermore, dry etching is used when photolithographically etching the interlayer vias, which includes an etching stage and a passivation stage. The etching stage and passivation stage are performed cyclically. The etching power is 150-450W, the total etching time is 20-180s, and the angle between the sidewall of the interlayer via and the bottom of the via is 75-90°.
[0008] Furthermore, when etching the first and second metal patterns, wet etching is used, with the volume ratio of etchant to deionized water being 1:(0.2-15), the etching temperature being 15-35°C, and an inhibitor being added to the etching solution, with the inhibitor being added at a ratio of 0.05-2%.
[0009] Furthermore, the first and second metal patterns are arranged in a serpentine pattern, and the corners of the patterns are set as arcs with a radius of 0.5 to 80 μm.
[0010] Furthermore, in the first metal pattern and the second metal pattern, the thickness of the fine line area with a line width less than the first preset threshold is 50-100 nm, and the thickness of the coarse line area with a line width greater than the second preset threshold is 200-500 nm.
[0011] Furthermore, the thickness of the seed layer is 5–200 nm, and the electroplating increases the thickness by 0.5–100 μm.
[0012] The advantages and positive effects of this invention are: 1. The upper and lower metal layers are set to overlap, and the overlap width compensates for the alignment error of the through holes between the layers, which improves the reliability of vertical interconnection between metal layers.
[0013] 2. The metal layer is etched using wet etching. By adjusting the ratio of etchant to deionized water and using low-temperature etching, the etching rate is reduced. An inhibitor is added to the etchant to improve the anisotropy of wet etching and reduce lateral etching. The dielectric layer is etched using dry etching. The etching and passivation stages are cyclically performed to effectively avoid lateral etching. This improves the etching accuracy of both wet and dry etching, effectively avoids open circuits in flexible circuits, and enhances the interconnection quality of flexible circuits.
[0014] 3. By setting an adhesion layer, the bonding force between the metal layer and the dielectric layer is improved; the metal pattern serpentine trace has reserved length redundancy, which transforms tensile strain into geometric deformation; the thin and thick trace areas have different thicknesses, adopting a thickness gradient design; the fracture resistance of the thin traces in the flexible circuit is improved, making it easier for the high-density wiring of the flexible circuit.
[0015] 4. The seed layer provides a conductive foundation for the electroplating process, ensuring that the electroplated metal can be deposited evenly and firmly in the designated area. The electroplating filler builds thick electrical contact points, reduces contact resistance, improves signal transmission quality, and enhances the mechanical strength and wear resistance of the contacts.
[0016] 5. Electroplating ensures a fill rate of over 80% for the contact window, guaranteeing reliable electrical connections and preventing cracking under thermal cycling. Low contact resistance (<100 mΩ) is achieved through the combined use of three technologies: thick contact electroplating, selection of highly conductive metals, and surface cleaning and activation. Attached Figure Description
[0017] The above and other objects, features, and advantages of the present invention will become more apparent from the more detailed description of the embodiments of the invention in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same parts or steps.
[0018] Figure 1 This is a schematic flowchart of a metal interconnection method for flexible circuits according to an embodiment of the present invention.
[0019] Figure 2 This is a schematic diagram of the first dielectric layer of a metal interconnection method for a flexible circuit according to an embodiment of the present invention.
[0020] Figure 3 This is a schematic diagram of the first metal layer of a metal interconnection method for a flexible circuit according to an embodiment of the present invention.
[0021] Figure 4 This is a schematic diagram of the second dielectric layer of a metal interconnection method for flexible circuits according to an embodiment of the present invention.
[0022] Figure 5 This is a schematic diagram of the second metal layer of a metal interconnection method for a flexible circuit according to an embodiment of the present invention.
[0023] Figure 6 This is a schematic diagram of the third dielectric layer in a metal interconnection method for a flexible circuit according to an embodiment of the present invention.
[0024] Figure 7 This is a schematic diagram of the contact window of a metal interconnection method for a flexible circuit according to an embodiment of the present invention.
[0025] Figure 8 This is a schematic diagram of the seed layer of a metal interconnection method for flexible circuits according to an embodiment of the present invention.
[0026] Figure 9 This is a schematic diagram of the contacts in a metal interconnection method for a flexible circuit according to an embodiment of the present invention.
[0027] In the diagram: 1. Base layer; 2. First dielectric layer; 3. First metal layer; 4. Second dielectric layer; 5. Interlayer via; 6. Second metal layer; 7. Third dielectric layer; 8. Contact window; 9. Seed layer; 10. Contact. Detailed Implementation
[0028] This invention provides a method for metal interconnection of flexible circuits. The embodiments of this invention will be described below with reference to the accompanying drawings.
[0029] In the description of the embodiments of this invention, it should be understood that the terms "top," "bottom," etc., indicating orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, it should be noted that unless otherwise explicitly specified and limited, the terms "set" and "connected" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention through specific circumstances.
[0030] like Figure 1 As shown, an embodiment of the present invention provides a metal interconnection method for a flexible circuit, comprising the following steps: coating a first dielectric layer 2; depositing a first metal layer 3 and photolithographically etching a first metal pattern; coating a second dielectric layer 4 and photolithographically etching interlayer vias 5; depositing a second metal layer 6 and photolithographically etching a second metal pattern, wherein the second metal pattern overlaps with the first metal pattern; coating a third dielectric layer 7 and photolithographically etching a contact window 8; depositing a passivation layer; evaporating a seed layer 9; and electroplating metal contacts 10. Compared with the prior art, the overlapping arrangement of the first and second metal patterns allows for tolerance of alignment even if the interlayer vias 5 are misaligned, ensuring the reliability of the metal interconnection. Evaporating the seed layer 9 and electroplating increases the thickness of the contacts 10, reduces the contact resistance of the contacts 10, extends the service life of the contacts 10, and ensures the accuracy of detection. A detailed description follows: S1. Coating the first dielectric layer 2; Clean the substrate layer 1. The substrate layer 1 is made of a rigid material, serving as a support carrier for subsequent multilayer thin film deposition. After the flexible circuit is fabricated on the support carrier, it is then transferred using water-soluble adhesive tape. Preferably, the substrate layer 1 can be a silicon wafer, glass, or quartz.
[0031] like Figure 2 As shown, a first dielectric layer 2 is coated on the surface of the substrate layer 1 and cured using a stepped heating method. The first dielectric layer 2 serves as the bottom base film of the flexible circuit. This base film not only provides mechanical support for the flexible circuit but also acts as electrical insulation, providing a smooth surface for subsequent metal wiring. The material of the first dielectric layer 2 can be polyimide (PI), parylene, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), photosensitive polyimide, benzocyclobutene (BCB), or SU-8. Preferably, the first dielectric layer 2 is polyimide. Polyamic acid is coated on the surface of the substrate layer 1, and curing heating causes the polyamic acid molecular chains to undergo a dehydration cyclization reaction, forming a stable and rigid five-membered imide ring structure, thereby generating polyimide, i.e., the first dielectric layer 2.
[0032] S2. Deposit the first metal layer 3 and photolithographically pattern the first metal pattern; like Figure 3 As shown, a first metal layer 3 is deposited on the surface of the first dielectric layer 2 by physical vapor deposition, such as sputtering or evaporation. Photoresist is then coated, and the layers are exposed and developed using a mask to form the pattern of the first metal layer. Finally, an etching process is used to remove the metal not protected by the photoresist, forming the first metal pattern. The first metal layer 3 is the first electrode layer of the flexible circuit.
[0033] The first metal layer 3 is a double-layer metal interface structure, including an adhesion layer and a conductive layer. The adhesion layer is made of a refractory metal or a transition metal, with a thickness in the nanometer range. The conductive layer is made of a noble metal or a highly conductive metal, with a thickness in the tens to hundreds of nanometers range. The adhesion layer is made of Cr, Ti, Ta, W, NiCr, or TiW, and the conductive layer is made of Au, Cu, Ag, Al, Pt, or Pd. Chemical bonds (Cr-OC, Ti-OC) are formed between the adhesion layer and the dielectric layer, improving the bonding force between the metal layer and the dielectric layer. The bonding force is >1.5 N / mm, preventing the metal layer from peeling off from the dielectric layer when the flexible circuit is bent. Preferably, the adhesion layer is made of Cr, and the conductive layer is made of Au.
[0034] Preferably, the thickness of the first metal layer and the second metal layer is 11 to 1100 nm, wherein the thickness of the adhesion layer is 1 to 100 nm and the thickness of the conductive layer is 10 to 1000 nm.
[0035] Preferably, the first metal pattern is a serpentine trace. Compared with a straight trace, the serpentine trace can reserve length redundancy, convert tensile strain into geometric deformation, and the trace corners are set as arcs with a radius of 0.5 to 80 μm. The arc corners can avoid right-angle stress concentration and effectively prevent the breakage of thin lines.
[0036] Preferably, in the first metal pattern, the thickness of the thin line area (with a linewidth less than a first preset threshold) is 50–100 nm, and the thickness of the thick line area (with a linewidth greater than a second preset threshold) is 200–500 nm. The thin line area is the region in the flexible circuit used for transmitting high-frequency signals or for high-density wiring, and its linewidth is 5–20 μm. The thick line area refers to the main conductor region used for transmitting power or high-current signals, and its linewidth is 50–200 μm. The thin line area uses thin metal to enhance flexibility, while the thick line area uses thick metal to ensure conductivity.
[0037] The type of etching solution is not specifically limited, such as aqua regia, sulfuric acid-based, cyanide-based, or thiourea-based solutions. In some feasible embodiments, the volume ratio of etchant to deionized water in the Au etching solution is 1:(0.2-15). Preferably, to balance the etching rate and lateral etching control, the volume ratio of etchant to deionized water is 1:1, and the etchant contains KI and I2. In the Cr etching solution, the volume ratio of etchant to deionized water is 1:(0.2-10). Preferably, to avoid over-etching damage to the first dielectric layer 2, the volume ratio of etchant to deionized water is 1:2, and the etchant contains Ce. 4+ And HNO3.
[0038] During wet etching, the etching temperature is 15–35°C. Lowering the temperature reduces the etching rate and improves anisotropy. End-point detection, such as ODS optical emission spectroscopy, is used to precisely control the etching progress and avoid over-etching.
[0039] The table below shows the comparison of wet etching process parameters and results:
[0040] The first set of experimental data shows that under high temperature and high concentration, the measured linewidth fluctuates between 96.5 and 97.5 μm. Although the etching rate is fast, the linewidth becomes thinner by about 3.5 μm due to the intense reaction and side etching.
[0041] The second set of experimental data shows that at low temperature and low concentration, the measured linewidth is between 100.4 and 101.0 μm, which is very close to the theoretical value, indicating that the corrosion inhibitor plays an excellent edge protection role at low temperature.
[0042] The experimental data from the third set show that at intermediate temperature and concentration, the measured linewidth is stable between 98.5 and 99.0 μm, with the deviation controlled within ±1.5 μm, proving that this parameter combination achieves the best balance between rate and accuracy.
[0043] The data from the fourth set of experiments show that although the linewidth data appears perfect (about 100μm), it is actually because the etching solution concentration is too low and the temperature is too low, causing the etching reaction to almost stop and the metal layer to be not effectively removed.
[0044] The fifth set of experimental data shows that when the concentration and temperature limits are exceeded and no corrosion inhibitor is used, the measured linewidth deviates significantly to 94-96 μm (with a deviation of ±6.0 μm), proving that the lateral etching is out of control and cannot meet the requirements of precision circuits.
[0045] S3. Coat the second dielectric layer 4 and photolithographically etch the interlayer vias 5; like Figure 4 As shown, a second dielectric layer 4 is coated on the first metal layer 3. The second dielectric layer 4 uses the same material and coating / curing method as the first dielectric layer 2. Dry etching is used to photolithographically etch interlayer vias 5 on the second dielectric layer 4. The second dielectric layer 4 serves as an interlayer insulating medium, isolating the first metal layer 3 from the subsequently deposited second metal layer 6 to prevent short circuits. At the same time, the interlayer vias 5 provide a channel for electrical connections between the upper and lower metal layers.
[0046] Preferably, the dry etching process includes an etching stage and a passivation stage, which are performed cyclically. Within one etching cycle, the etching stage is performed first, during which an etching gas is introduced, causing the hole to deepen vertically downwards. Then, the passivation stage is performed, during which a passivation gas is introduced, depositing on the entire inner wall of the hole to form a protective film. At the start of the next etching cycle, the protective film at the bottom of the hole is etched away by the vertically oriented etching gas, while the protective film on the hole wall is retained because it is not etched vertically, effectively preventing lateral etching and ensuring that the angle between the sidewall and the bottom of the hole is 75–90°. The etching stage duration is set to 20–55 s, the passivation stage duration is set to 5–15 s, and the total etching time is 20–180 s.
[0047] Dry etching employs reactive ion etching (RIE), and the type of etching gas is not limited, such as one or more of CF4, CHF3, C4F8, O2, Ar, Cl2, BCl3, or SF6. In some feasible embodiments, the etching gas is a mixture of CF4, O2, and Ar at a flow rate ratio of 20:5:10 sccm. CF4 provides fluorine radicals, which react with C, H, and O in the polyimide to generate volatile products such as CO, CO2, and H2O, while also providing anisotropic etching capability. O2 promotes polymer removal. O radicals combine with the carbon dissociated from CF4 to generate CO / CO2, inhibiting carbon deposition and oxidizing the surface, thereby increasing the etching rate of the polyimide and improving the removal of residues after etching. Ar, as an inert ion, performs physical bombardment, enhancing the energy transfer of ion bombardment, breaking the chemical bonds of the polyimide, accelerating the desorption of reactants, improving anisotropy, and reducing micro-loading effects.
[0048] The etching power is set to 150–450 W to balance chemical and physical etching. The etching pressure is set to 50–150 mTorr to improve ion directionality.
[0049] The table below shows the process parameters and results for dry etching of interlayer vias:
[0050] The experimental data from the third set show that under the conditions of 300W power and 90s time, the average included angle is 85°, and the five specific data (84-86°) are concentrated, indicating that the etching anisotropy is good under this process window, the sidewall flatness is the best, and the through hole morphology is the most ideal.
[0051] The first set of experimental data shows that reducing the etching power and increasing the etching time reduced the average included angle to 76°, with specific values between 75-77°. This indicates that at lower power, the physical bombardment effect weakens, the proportion of chemical etching increases, resulting in a slight tilting of the sidewalls (though this is relatively gradual), but the through-hole can still be formed without short circuits.
[0052] The second set of experimental data shows that increasing the etching power and reducing the etching time resulted in an average etching angle of 89°, with specific values between 88-90°. High power resulted in a very strong vertical bombardment effect with excellent perpendicularity, but the etching time needed to be controlled to avoid over-etching.
[0053] The fourth set of experimental data shows that the power is too low, with an average angle of only 60° and data fluctuations between 59-61°. This excessively small tilt angle indicates severe sidewall tilt, leading to incomplete etching at the bottom (bottom residue), which can easily cause open circuits and fail to meet process requirements.
[0054] The fifth set of experimental data shows that when the power is too high, the average angle is 90°, with data ranging from 89-91°. Although the angle is perpendicular, the excessively fast etching rate makes it difficult to precisely control the endpoint, resulting in damage to the substrate at the bottom of the hole and affecting the reliability of the device.
[0055] S4. Deposit the second metal layer 6 and photolithographically etch the second metal pattern, with the second metal pattern overlapping the first metal pattern; like Figure 5 As shown, the second metal layer 6 has the same structure and fabrication method as the first metal layer 3, and will not be described in detail here. The second metal layer 6 is the second electrode layer of the flexible circuit, and the second metal layer 6 and the first metal layer 3 are electrically interconnected through interlayer vias 5. The second metal pattern and the first metal pattern are etched using the same wet etching process.
[0056] During the photolithography of the interlayer via 5, alignment of the via 5 is difficult, leading to alignment deviations and errors in the photolithography process, which may cause the position of the interlayer via 5 to shift. To ensure the reliability of the interconnection between the upper and lower metal layers, the second metal pattern overlaps with the first metal pattern to form an overlap area. The width of the overlap area is greater than the diameter of the interlayer via, and the overlap width is 0.5–80 μm. The second metal pattern and the first metal pattern form an annular or square overlap area around the interlayer via. The overlap width is set according to the alignment deviation and process fluctuation margin. The overlap width between the first metal layer 3 and the second metal layer 6 is 0.5–80 μm, preferably 5–20 μm. This overlap width is used to compensate for photolithographic alignment deviations, ensuring reliable electrical connection even with an alignment error of ±0.5 μm.
[0057] S5. Coat the third dielectric layer 7 and photolithographically etch the contact window 8; like Figure 6 and Figure 7 As shown, a third dielectric layer 7 is coated on the second metal layer 6. The third dielectric layer 7 uses the same material and coating / curing method as the first dielectric layer 2. Photolithography is performed to photolithographically create contact windows 8 on the third dielectric layer 7, exposing the first metal layer 3 and the second metal layer 6. The third dielectric layer 7 serves as a protective passivation layer, covering and protecting the internal circuit structure from external environmental corrosion (such as moisture and dust). The photolithographically formed windows expose the contact point 10 areas that need to be electrically connected to the outside. During the etching process, the dielectric layer is etched using a dry etching method as described above, and the metal layer is etched using a wet etching method as described above.
[0058] S6, Deposited passivation layer; A thin film of metal oxide, such as silicon dioxide or aluminum oxide, is deposited as a passivation layer, and the pattern is further refined by photolithography. The passivation layer enhances the surface's insulation properties and chemical stability, serving as the final protective layer to ensure the reliability of the circuit under complex operating environments, while also providing good adhesion for the subsequent evaporation of the seed layer 9. The passivation layer is not shown in the figure.
[0059] S7, vapor-deposited seed layer 9; like Figure 8 As shown, a thin metal seed layer 9 is deposited by vapor deposition, followed by coating with a thick resist and photolithography to prepare for electroplating. The metal of the seed layer 9 can be titanium or copper, preferably copper. The seed layer 9 provides a conductive base for the subsequent electroplating process, ensuring that the electroplated metal can be deposited uniformly and firmly in the designated area. The thickness of the seed layer 9 is 5–200 nm.
[0060] S8, electroplated metal contact 10.
[0061] like Figure 9 As shown, a thick metal is electroplated onto the seed layer 9 to form a highly conductive contact 10, followed by the removal of the photoresist and excess seed layer 9. The electroplated metal can be copper or gold. Preferably, the electroplated metal is copper. The electroplating increases the thickness by 0.5–100 μm. By constructing a thick electrical contact 10 through electroplating, the contact resistance is reduced, the signal transmission quality is improved, and the mechanical strength and wear resistance of the contact 10 are enhanced.
[0062] Preferably, the electroplating solution can be acidic copper sulfate, copper pyrophosphate, cuprous cyanide, copper sulfonate, or cyanide-free alkaline copper. The electroplating solution contains additives, including accelerators, inhibitors, and leveling agents. Accelerators adsorb onto the copper surface, accelerating deposition. Inhibitors suppress surface and sidewall deposition, forming a diffusion barrier layer. Leveling agents inhibit deposition on protrusions, resulting in a flat surface.
[0063] Electroplating fills the contact window 8 to ensure a fill rate greater than 80%, guaranteeing the reliability of the electrical connection and reducing the risk of cracking under thermal cycling. The fill rate refers to the volume percentage of metal electroplated filler within the through-hole, measured through FIB cross-section + SEM image analysis or resistance method.
[0064] The FIB cross-section combined with SEM image analysis method includes the following steps: Sample preparation: Select the sample to be tested and use focused ion beam (FIB) technology to vertically cut the contact window area to expose the longitudinal section of the contact window; Imaging: The cut cross-section was photographed using a scanning electron microscope (SEM) to obtain a high-resolution cross-sectional morphology image; Calculation: In the SEM image, identify and calculate the cross-sectional area (S1) of the actually filled metal within the contact window and the theoretical total cross-sectional area (S0) of the contact window. Judgment: Calculate the filling rate according to the formula filling rate = (S1 / S0) × 100%. If the calculation result is greater than 80%, it is judged as qualified.
[0065] The resistance method includes the following steps: Theoretical calculation: According to the geometric dimensions (diameter or length, width, height) of the contact window and the resistivity of the electroplated metal used (such as copper), calculate the theoretical resistance value (R0) when the contact window is completely filled with metal (100% filling). Actual measurement: Use a four-probe tester or a micro-ohmmeter to actually measure the actual resistance value (R1) at both ends of the contact window. Judgment: Estimate according to the formula filling rate = (R0 / R1) × 100%. Since the resistance is inversely proportional to the conductive cross-sectional area, when the actually measured resistance value R1 is close to the theoretical resistance value R0, it indicates that the filling rate is greater than 80%.
[0066] The metal contacts in the present invention reduce the contact resistance to below 100 mΩ, which is achieved through the coordination of three aspects: thick contact electroplating (contributing <50 mΩ), selection of high-conductive metal (contributing <20 mΩ), and surface cleaning and activation (contributing <30 mΩ).
[0067] The advantages and positive effects of the present invention are: 1. The upper and lower metal layer patterns are overlapped, and the overlapping width compensates for the alignment error of the interlayer vias, improving the reliability of the vertical interconnection between metal layers.
[0068] 2. The metal layer is etched by wet etching. By adjusting the ratio of the etchant to deionized water and using low-temperature etching, the etching rate is reduced, and an inhibitor is added to the etchant to enhance the anisotropy of wet etching and reduce side etching; the dielectric layer is etched by dry etching, and the etching stage and the passivation stage are cycled, effectively avoiding side etching; the etching accuracy of wet etching and dry etching is improved, effectively avoiding the open circuit of the flexible circuit, and improving the interconnection quality of the flexible circuit.
[0069] 3. By setting the adhesion layer, the bonding force between the metal layer and the dielectric layer is improved; the serpentine routing of the metal pattern reserves length redundancy, converting the tensile strain into geometric deformation, and the arc corner can avoid right-angle stress concentration; the thicknesses of the fine line area and the thick line area are different, and a thickness gradient design is adopted; through the coordination of triple mechanisms, the anti-fracture ability of the fine lines of the flexible circuit is improved, which is more convenient for the high-density wiring of the flexible circuit.
[0070] 4. The seed layer provides a conductive foundation for the electroplating process, ensuring that the electroplated metal can be deposited evenly and firmly in the designated area. The electroplating filler builds thick electrical contact points, reduces contact resistance, improves signal transmission quality, and enhances the mechanical strength and wear resistance of the contacts.
[0071] 5. Electroplating ensures a fill rate of over 80% for the contact window, guaranteeing reliable electrical connections and preventing cracking under thermal cycling. Low contact resistance (<100 mΩ) is achieved through the combined use of three technologies: thick contact electroplating, selection of highly conductive metals, and surface cleaning and activation.
[0072] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and have not been described in detail. Furthermore, the definitions of the various components described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.
[0073] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the patent coverage of the present invention.
Claims
1. A method for metal interconnection of flexible circuits, characterized in that, Includes the following steps: Coating the first dielectric layer; Deposit the first metal layer and photolithographically pattern the first metal pattern; A second dielectric layer is coated and interlayer vias are photolithographically etched. A second metal layer is deposited and a second metal pattern is photolithographically formed. The second metal pattern overlaps with the first metal pattern to form an overlap region. The width of the overlap region is greater than the diameter of the interlayer via. The overlap width of the overlap region is 0.5 to 80 μm. A third dielectric layer is coated and contact windows are photolithographically etched; Deposition of passivation layer; Fabrication of metal contacts includes: Evaporated seed layer; Electroplated metal contacts are used to make the metal contacts protrude from the contact window.
2. The metal interconnection method for flexible circuits according to claim 1, characterized in that: Both the first metal layer and the second metal layer include an adhesion layer and a conductive layer. The adhesion layer is made of Cr, Ti, Ta, W, NiCr or TiW, and the conductive layer is made of Au, Cu, Ag, Al, Pt or Pd. The thickness of the first metal layer and the second metal layer is 11 to 1100 nm.
3. A metal interconnection method for flexible circuits according to claim 1 or 2, characterized in that: Dry etching is used when photolithographically etching the interlayer vias, which includes an etching stage and a passivation stage. The etching stage and passivation stage are performed cyclically. The etching power is 150-450W and the total etching time is 20-180s. The angle between the sidewall of the interlayer via and the bottom of the via is 75-90°.
4. A metal interconnection method for flexible circuits according to claim 1 or 2, characterized in that: When etching the first and second metal patterns, wet etching is used, with the volume ratio of etchant to deionized water being 1:0.2-15, the etching temperature being 15-35°C, and a corrosion inhibitor being added to the etching solution at a ratio of 0.05-2%.
5. The metal interconnection method for a flexible circuit according to claim 4, characterized in that: The first and second metal patterns are arranged in a serpentine pattern, and the corners of the patterns are set as arcs with a radius of 0.5 to 80 μm.
6. The metal interconnection method for a flexible circuit according to claim 5, characterized in that: In the first metal pattern and the second metal pattern, the thickness of the fine line area with a line width less than the first preset threshold is 50-100 nm, and the thickness of the coarse line area with a line width greater than the second preset threshold is 200-500 nm.
7. The metal interconnection method for flexible circuits according to claim 1, characterized in that: The thickness of the seed layer is 5–200 nm, and the thickness is increased by 0.5–100 μm by electroplating.