High-K / Metal Gate LDMOS Nanosheet Device

Abstract

This disclosure relates to a high-k / metal-gate LDMOS nanosheet device. Examples of the disclosure include a microelectronic device (100) and a method of manufacturing such a device. One example includes a nanosheet laterally diffused metal-oxide-semiconductor (LDMOS) transistor (101). The LDMOS transistor (101) may include a gate dielectric (136) of a high-k material and a metal gate (137). The LDMOS transistor (101) includes a source (141) and a drain (151) extending into a semiconductor substrate (104). A nanosheet region (116) extends between the source (141) and the drain (151). A nanosheet channel layer (135c) alternates with a metal gate layer (137) extending from the source (141) to the drain (151). A nanosheet drain drift layer (138) alternates with a field plate conductor layer (147) extending from the drain (151) to the source (141).

Description

Technical Field

[0001] This disclosure relates to the field of microelectronic devices. More specifically, but not exclusively, this disclosure relates to gate-controlled devices, such as LDMOS transistors, and more particularly, nanosheet LDMOS transistors. Background Technology

[0002] Semiconductor components are constantly being improved to operate reliably with smaller feature sizes. Manufacturing increasingly high-performance semiconductor devices that simultaneously meet performance and reliability specifications presents various challenges. Summary of the Invention

[0003] This summary is provided to offer a simplified overview of the disclosed concepts, which will be further described below in specific embodiments including the provided figures. This summary is not intended to limit the scope of this disclosure or the claims.

[0004] The disclosed examples include microelectronic devices, such as integrated circuits, and methods of manufacturing such devices. One example includes a microelectronic device comprising a nanosheet laterally diffused metal-oxide-semiconductor (LDMOS) transistor. The LDMOS transistor may include a high-k gate dielectric and a metal gate. The LDMOS transistor includes a source region and a drain region having a first conductivity type, extending into a semiconductor substrate. A nanosheet region comprising semiconductor nanosheets extends between the source and drain regions. The nanosheets alternate with a gate conductor layer extending from the source to the drain region and a field plate conductor layer extending from the drain to the source region, wherein a gate dielectric layer and a field release dielectric layer separate the gate conductor layer from the field plate conductor layer. Attached Figure Description

[0005] Figure 1A and 1B The perspective view and top view of an example microelectronic device are shown respectively. The microelectronic device includes a nanosheet LDMOS transistor with a field plate.

[0006] Figure 1C and 1D Show each Figure 1A Longitudinal and transverse cross-sectional views of the microelectronic device;

[0007] Figures 2A to 15A Displays 16, 17A to 19A and 20 to 22 Figure 1A Longitudinal cross-sectional views of microelectronic devices in various configuration states;

[0008] Figures 2B to 15B and exhibits 17B to 19B Figure 1A Various transverse cross-sectional views of microelectronic devices in various configuration states. Detailed Implementation

[0009] This disclosure is described with reference to the accompanying drawings. The drawings are not to scale and are provided for illustrative purposes only. Several aspects of this disclosure are described below with reference to exemplary applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited by the order in which actions or events are described, as some actions may occur in a different order and / or simultaneously with other actions or events unless otherwise stated. Furthermore, according to this disclosure, some of the described actions or events may be omitted in some instances.

[0010] Furthermore, although some of the examples illustrated herein are shown in two-dimensional views, with various regions having depth and width, it should be clearly understood that these regions are merely illustrations of parts of the actual three-dimensional structure of the device. Therefore, when fabricated on an actual device, these regions will have three dimensions, including length, width, and depth. Moreover, while this disclosure is illustrated by examples of active devices, these illustrations are not intended to limit the scope or applicability of this disclosure. The active devices of this disclosure are not intended to be limited to the illustrated physical structures. These structures are included to demonstrate the utility and application of this disclosure to various examples.

[0011] It should be noted that terms such as top, bottom, above, above, and below are used in this disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to a plane corresponding to the surface of a layer (e.g., the top surface of a semiconductor substrate). Furthermore, the term "about" unless otherwise stated, means a deviation of ±10% from the listed values. The term "approximately" means within ±20% of the listed values.

[0012] Microelectronic devices are constantly being improved to operate reliably with higher performance and smaller feature sizes. Fabricating such microelectronic devices that meet area reduction and reliability specifications has always been a challenge. Some gate-controlled devices, such as metal-oxide-semiconductor (MOS) transistors, include features for supporting high-voltage operation, for example, by applying voltages of 20 V, 30 V, 40 V, or even higher to their drain (or drain structure). Such MOS transistors may include drain diffusion profiles (or drain junction profiles) designed to support high voltages applied to the drain, for example, having extended portions to distribute voltage drops across a greater distance. Therefore, such MOS transistors may be referred to as extended-drain (ED) MOS transistors, such as extended-drain n-channel MOS (DENMOS) transistors, extended-drain p-channel MOS (DEPMOS) transistors, laterally diffused MOS (LDMOS) transistors, and groups of DENMOS and DEPMOS transistors (which may be referred to as complementary-drain extended MOS or DECMOS transistors). Other gate-controlled microelectronic devices may include gate-controlled bipolar semiconductor devices, gate-controlled unipolar semiconductor devices, insulated-gate bipolar transistors (IGBTs), MOS-triggered SCRs, MOS-controlled thyristors, and gate-controlled diodes. Miniaturizing ED transistors reduces microchip costs and improves circuit performance by reducing parasitic resistance and capacitance. Maintaining good reliability and yield can be challenging; therefore, improving transistor performance without considering lateral lithography scaling can be advantageous.

[0013] The physical geometry of the nanosheets in an ED transistor differs from that in a nanosheet digital CMOS transistor. For example, some nanosheet digital (switching) CMOS transistors typically utilize a nanosheet architecture comprising nanosheet layers only a few nanometers thick. Due to the relatively thin conductive paths, the carrier mobility of such nanosheet layers can be reduced, which may be irrelevant to switching applications. However, for high-voltage ED transistors, high drain drift region mobility can be beneficial, and nanosheets thicker than 10 nm can be used, for example, in the range of 20 nm to 500 nm or greater, to achieve the target RSP value for efficient power circuit designs. In some instances, the nanosheet thickness can be 50 nm to 500 nm, or 100 nm to 300 nm, which allows for sufficiently low doping concentrations in the drain drift region to maintain high electron mobility and thus reduce RSP. Furthermore, the exemplary nanosheet ED transistors of this disclosure may have drain drift regions with field-release structures to provide higher operating voltages than those potentially used in nanosheet switching transistors.

[0014] Stacking multiple transistor channels offers advantages by increasing the width of the channel and drift region between the source and drain, thereby reducing the on-resistance and increasing the on-current of the ED transistor. For planar transistors, such designs can utilize a larger die area than a preferred die area. Examples of this disclosure provide increased channel and drift region width by using multiple vertically stacked nanosheet channels between the source and drain. The width is proportional to the number of stacked layers. Figures 1A to 1D The example ED transistor described herein may have a nanosheet drift region, wherein the nanosheet drift region has a dopant concentration dose of 10. 12 Up to 10 13 cm -2 The doping distribution of the nanosheet regions within the resurf range determines the contribution of the drain drift region to the source-drain on-resistance (RDSON), which is typically the main contributor to the device resistance. Therefore, stacking multiple nanosheet ED transistors in parallel reduces the RDSON of the ED transistors in a given area, thereby reducing the cost-to-quality factor (RSP) for a given on-resistance (RSP) (cost-to-quality factor, for example, equal to RDSON multiplied by area), and improving power scaling for a given lithography scaling capability.

[0015] In some instances, this disclosure describes a device comprising: a gate dielectric layer between semiconductor channels of nanosheets in the gate region, and a field release dielectric layer thicker than the gate dielectric layer between drift regions of nanosheets in the drift region. Either or both of the gate dielectric layer and the field release dielectric layer may be silicon dioxide (k≈3.9) or a dielectric material with a dielectric constant higher than silicon dioxide, and either or both of the gate dielectric layer and / or the field release dielectric layer may have a single layer or two or more sublayers with a total dielectric constant greater than 3.9. Using a field release dielectric layer thicker than the gate dielectric layer in the drift region results in a higher breakdown voltage for the device and thus allows the device to operate at higher voltages compared to devices with thinner field release dielectric layers.

[0016] In conventional, such as planar drain extension devices, for transistors with higher rated voltages, it is sometimes necessary to use a thicker dielectric with different geometries (e.g., LOCOS, STI, etc.) above the drift region. In this disclosure, the gate dielectric layer and the field release dielectric layer are in contact with each other, and a continuous dielectric block or dielectric spacer is formed between the conductive layer acting as the gate on the source side of the transistor and the conductive layer acting as the field plate on the drain side of the transistor. The dielectric block between the gate layer and the field plate layer improves hot carrier performance and thus improves reliability. The dielectric block also allows for the implementation of a field plate layer with a different work function than the gate layer on the channel side of the transistor. The ability to have separate gate metals above the channel and field plate enables thinner field release dielectric layers than would otherwise be required for a given high-voltage operating condition. The work function of the gate metal can be greater than 3.9 eV. The gate metal can be TiAlN, TiN, TaN, Al, TaSiN, MoN, W, or other suitable metals.

[0017] This disclosure includes exemplary microelectronic devices comprising nanosheet LDMOS transistors, the nanosheet LDMOS transistors incorporating a high-k gate dielectric layer, a high-k field-release dielectric layer, and a gate layer and field plate layer with a work function greater than 3.9 eV. As used herein, the term "superlattice" refers to a periodic structure containing at least two different material layers. A superlattice may have many such layers, and in some cases may have only two layers, comprising a first material and a second material. Such layers may be referred to as "nanosheets," and their thickness (in a direction perpendicular to the principal surface of the substrate on which the superlattice is formed) may not exceed 500 nm. Nanosheets may also be active layers in semiconductor devices comprising said nanosheets. A superlattice may initially include one or more "sacrificial layers" formed in the superlattice, which may be removed in whole or in part later during the formation of the nanosheet transistor.

[0018] While such examples of the present disclosure may be expected to provide improved performance, such as reduced specific RSP, RSON and greater on-state current, reduced die area for implementing various devices, and / or higher operating voltage than some other comparable planar devices, no particular result is required by the present disclosure unless expressly stated in the specific claims.

[0019] Figure 1A A perspective view of a microelectronic device 100 is shown, which includes, for example, a nanosheet LDMOS transistor 101, sometimes referred to as nanosheet transistor 101 or simply transistor 101 for simplicity. The principles of this disclosure can be beneficially applied to the microelectronic device. Figure 1B Showing a top view, with longitudinal planes showing the microelectronic device 100 at various formation stages. Figure 1C and 2AThe orientation shown in the cross-sectional views to 15A, 16, 17A to 19A and 20 to 22, and the orientation in the transverse plane at various formation stages. Figure 1D , 2B The orientation is shown in the cross-sectional views to 15B and 17B to 19B. Figure 1C It is a cross-sectional view of the microelectronic device 100 passing through the longitudinal plane, and Figure 1D It is a cross-sectional view through a horizontal plane.

[0020] Figure 1A The perspective view shown has some layers removed for clarity. By way of example, a nanosheet transistor 101 is formed in or on a semiconductor substrate 104, which includes a substrate wafer 102 (e.g., a silicon wafer) and has a top surface 107 with a thickness that can be from 5 µm to 15 µm. A source contact 154 is electrically connected to a source region 141, and a drain contact 155 is electrically connected to a drain region 151. The first conductivity type of the source region 141 and the drain region 151 is n-type in various examples. The second conductivity type of the semiconductor material 103 is p-type in various examples. A gate contact 156 is connected to a lower volt gate, as further described below. Isolation of the transistor 101 is provided by a deep well 106 surrounding a gate dielectric layer 136 and a field release dielectric layer 146, extending into a buried layer, also described further below. The deep well 106 may sometimes also be referred to as a deep well ring. Although only a single source region 141 and a single drain region 151 are shown, example devices consistent with this disclosure may have multiple source regions 141 and drain regions 151, as well as corresponding nanosheet regions 116, which can provide parallel conductivity.

[0021] Figure 1B Explained with a floor plan Figure 1A Some features of the transistor 101 described herein include a shallow trench isolation (STI) structure 118, shown as being surrounded by a deep well 106, which also facilitates device isolation. This figure also provides various references to the cross-sections shown in the various figures described below. Figure 1C , 2A Transistors 101, as shown in figures 15A, 16, 17A, 19A, and 20 to 22, are formed in various stages along the longitudinal direction in a plane (XZ) parallel to the direction from the source contact 154 to the drain contact 155; and Figure 1D , 2B Transistors 101 are shown in various formation stages along the lateral direction in a plane (YZ) perpendicular to the longitudinal direction, up to 15B and 17B to 19B.

[0022] Refer to the description at the same time Figure 1C and Figure 1DThe nanosheet transistor 101 is shown in a late-stage formation phase. A deep well 106 extends from the top surface 107 through a semiconductor material 103 having a first conductivity type to a buried layer 105 having a first conductivity type, sometimes referred to as an n-type buried layer or NBL 105. A “buried layer” (sometimes abbreviated as “BL”) is defined as a semiconductor layer having a first doping characteristic (e.g., conductivity type, dopant type, or dopant concentration), such as NBL 105, which is spaced from the top surface 107 by another layer (e.g., semiconductor material 103) having a different second doping characteristic. The NBL 105 and the deep well 106 ring together define an isolation region in which the transistor 101 is located. The nanosheet region 116 includes a source trench 133 (containing a source region 141), a drain trench 144 (containing a drain region 151), a gate region 158, and a field plate region 159. The p-type nanosheet channel layer 135c extends from the source region 141 to the drain region 151, and the n-type nanosheet drain drift layer 138 extends from the drain region 151 to the source region 141. The source region 141, the drain region 151, the channel layer 135c, and the drain drift layer 138 are located in the nanosheet trench 112 (sometimes referred to as trench 112 for simplicity).

[0023] Gate layer 137 extends from gate contact 156 toward source region 141, and field plate layer 147 extends from gate contact 156 toward drain region 151. Gate layer 137 is laterally spaced from source region 141 by gate spacer 139, and field plate layer 147 is laterally spaced from drain region 151 by field plate spacer 149. Channel layer 135c is located between vertically adjacent elements of gate spacer layer 139 and gate layer 137. Drain drift layer 138 is located in n-type drain drift region 117 (sometimes referred to as NDRIFT region 117) and extends from drain region 151 to channel layer 135c between vertically adjacent elements of field plate spacer 149 and field plate layer 147. Thicker portion of drain drift layer 138 extends to source side of field plate layer 147, and thinner portion of drain drift layer 138 extends from thicker portion to channel layer 135c. The thinner portion of the drain drift layer 138 has a thickness substantially the same as that of the channel layer 135c. The longitudinal length (X direction) of the thinner portion may be as small as zero, or may be a considerable portion of the longitudinal width of the gate layer 137, for example, 50% or more as in the illustrated example.

[0024] Gate dielectric layer 136 is located between each of the gate layers 137 and a vertically adjacent channel layer 135c, and in some instances between the gate layer 137 and a thinner portion of the vertically adjacent drain drift layer 138. In some instances, such as those illustrated, three sides of the gate layer 137 are covered by a continuous conformal gate dielectric layer 136.

[0025] Between the source region 141 and the STI structure 118, a portion of the gate dielectric layer 136 contacts the STI structure 118, and a portion of the gate spacer 139 is located between the source region 141 and the gate dielectric layer 136. These features are products of the process of forming transistor 101 and are not expected to significantly contribute to the functional properties of transistor 101. Furthermore, portions of the gate dielectric layer 136 and the gate layer 137 on the STI structure 118 are products of the process of forming transistor 101, and their contribution to the functional properties of transistor 101 is negligible.

[0026] Additional features of transistor 101 include: a third pad oxide layer 129, a third hard mask layer 130, a fourth hard mask layer 163, and a dielectric layer 153 (sometimes referred to as a pre-metal dielectric layer 153). A metal terminal 157 above the PMD layer 153 provides electrical connections to the source contact 154, the drain contact 155, and the gate contact 156.

[0027] In field plate region 159, field release dielectric layer 146 contacts drain drift layer 138. Field plate layer 147 contacts field release dielectric layer 146. In the region where gate region 158 intersects with field plate region 159, gate dielectric layer 136 and field plate layer 147 provide electrical isolation between gate layer 137 and field plate layer 147. Field plate spacer 149 provides electrical isolation between field plate layer 147 and drain region 151. Between source region 141 and STI structure 118, a portion of third pad oxide layer 129 contacts STI structure 118, and a portion of field plate spacer 149 is between drain region 151 and third pad oxide layer 129, none of which are functional elements of nanosheet transistor 101.

[0028] In addition to the features described for transistor 101, Figure 1D The diagram also shows trench 124, which relates to certain sacrificial layers used to form transistor 101 as described below.

[0029] Now, at various formation stages, against the backdrop of continuous longitudinal or transverse cross-sectional views, the various structural features and formation steps of the microelectronic device 100 are described.

[0030] refer to Figure 2A and Figure 2BThe microelectronic device 100 is shown in an early stage of formation. The substrate wafer 102 can be a silicon wafer having any conductivity type. In some other examples, the substrate wafer 102 may contain a dielectric material, such as silicon dioxide or sapphire, to provide a silicon-on-insulator (SOI) substrate. A semiconductor material 103 has been formed on the substrate wafer 102. In various examples, the semiconductor material 103 primarily comprises silicon and may consist essentially of silicon and dopants (e.g., boron), in which case the semiconductor material is p-type. By way of example, the semiconductor material 103 can be formed by an epitaxial process and can be 5 μm to 15 μm in diameter. The semiconductor material 103 extends to a top surface 107. The substrate wafer 102 and the semiconductor material 103 form a substrate 104, referred to herein as substrate 104.

[0031] In some instances, and as shown, the buried layer 105 extends into both the substrate wafer 102 and the semiconductor material 103. The buried layer 105 has a first conductivity type, which in this example is n-type, and thus can be referred to without limitation as an n-type buried layer, or NBL 105. The NBL 105 can be formed by any conventional or previously undiscovered method. In one such instance, a dopant of a second conductivity type, such as phosphorus, arsenic, or antimony, is deposited into the substrate wafer 102 prior to the formation of the semiconductor material 103. Prior to the formation of the semiconductor material 103, the substrate wafer 102 can be annealed, and the semiconductor material 103 can subsequently be formed by an epitaxial process involving the thermal decomposition of silane, during which the dopant diffuses deeper into both the substrate wafer 102 and the semiconductor material 103, thereby forming the NBL 105.

[0032] A deep well 106 may be formed in semiconductor material 103, extending from the top surface 107 of substrate 104 to NBL 105. The deep well 106 may have a first conductivity type, such as n-type. The deep well 106 may be formed by implanting a dopant of the first conductivity type (e.g., phosphorus) into semiconductor material 103, and then thermally diffusing the implanted dopant into NBL 105 and activating the implanted dopant. The average concentration of the first conductivity type dopant in the deep well 106 may be at least 2 to 10 times the average concentration of a second conductivity type dopant in semiconductor material 103 outside the deep well 106. The deep well 106 provides isolation between nanosheet transistor 101 and other components of microelectronic device 100. The deep well 106 may preferably be degenerate-doped to provide low leakage between nanosheet transistor 101 and other components of microelectronic device 100.

[0033] Figure 3A and Figure 3BA microelectronic device 100 is shown after trench 112 has been formed. After forming NBL 105 and deep well 106, a first pad oxide layer 108 can be formed on the top surface 107 of substrate 104. By way of example, the first pad oxide layer 108 may primarily comprise silicon dioxide, can be formed by thermal oxidation or thermochemical vapor deposition (CVD) processes, and has a thickness of 5 nm to 200 nm. A first hard mask layer 109 can be formed on the first pad oxide layer 108. The first hard mask layer 109 may comprise a layer 109a of a material primarily composed of silicon nitride and a layer 109b of a material primarily containing silicon dioxide. The thickness of the first hard mask layer 109 may be 50 nm to 3 μm, depending on the depth of trench 112. The first pad oxide layer 108 can provide stress relief between semiconductor material 103 and the first hard mask layer 109. The silicon nitride portion of the first hard mask layer 109 can provide a stop layer for subsequent etching and planarization processes. The silicon dioxide layer of the first hard mask layer 109 can provide a hard mask during trench etching 111 used to form the trench 112. A trench photomask (not specifically shown) can be formed on the first hard mask layer 109, having openings that expose the first hard mask layer 109 in the region used for the trench 112.

[0034] Trench etching 111 forms trench 112 in substrate 104. Trench etching 111 may comprise multiple steps. After trench etching 111, a trench photomask is removed. After removing the trench photomask, trench sidewall spacers 113 are formed. Trench sidewall spacers 113 can be formed by depositing a dielectric blanket layer, such as silicon dioxide or silicon nitride, followed by anisotropic etching (neither process is specifically shown). Anisotropic etching leaves trench sidewall spacers 113, which prevent the deposition of semiconductor material on the sidewalls of trench 112 in subsequent processing steps. After forming trench sidewall spacers 113, the horizontal surface of trench 112 is typically free of dielectric material.

[0035] refer to Figure 4A and Figure 4BThe image shows a cross-section after the formation of the nanosheet region 116. The nanosheet region 116 can be formed by epitaxial deposition or atomic layer deposition (ALD) or other deposition methods to form a semiconductor layer 114 alternating with a sacrificial layer 115. In the example nanosheet transistor 101, the semiconductor layer 114 may be primarily single-crystal silicon, such as in-situ doped p-type, and the sacrificial layer 115 may be primarily single-crystal SiGe, such as undoped or intrinsic SiGe. Other examples within the scope of this disclosure may use other combinations of semiconductor layer 114 and sacrificial layer 115. For example, the roles of silicon and SiGe may be interchanged, such that SiGe is used as the semiconductor material of semiconductor layer 114, and silicon is used as sacrificial layer 115. Other combinations may also be used, wherein materials may be formed in alternating layers, and one layer may be preferentially removed, leaving semiconductor layer 114 intact. Without any implied limitations, the semiconductor layer may be referred to as silicon layer 114. The thickness of silicon layer 114 may be in the range of about 10 nm to 500 nm, but other thicknesses are also considered. The materials used to implement the silicon layer 114 and the sacrificial layer 115 can be selected such that the sacrificial layer 115 can be removed at a later processing stage by plasma etching or wet etching, while the silicon layer 114 remains intact.

[0036] Figure 5A and 5B Transistor 101 is shown after the formation of NDRIF region 117. An n-type dopant, such as phosphorus, can be implanted at least as deep as the bottom of trench 112, optionally using chain implantation to create an effective uniform dopant distribution in NDRIF region 117 after activation annealing. A portion of silicon layer 114 within NDRIF region 117 is converted from p-type to n-type nanosheet drain drift layer 138, and can be referred to as n-type doped silicon layer 114a to reflect the modification. When no further distinction is needed, both the n-type and p-type portions can be collectively referred to as silicon layer 114.

[0037] NDRIFT region 117 is formed in portions of substrate 104, semiconductor material 103, and nanosheet region 116, and will subsequently surround Figure 1C The drain region 151 is illustrated in the diagram. One or more n-type implantations are performed in the substrate 104 to form a drain drift region 117 (which may be referred to as an n-type drift region). The n-type dopant defining the n-type drift region 117 can be implanted in a one-step or multi-step manner. Arsenic can also be implanted, with a similar dosage but relatively higher energy compared to phosphorus implantation. The average doping concentration of the NDRIF region 117 is lower than that of the drain region 151 (…). Figure 1C The average doping concentration.

[0038] refer to Figure 6A and Figure 6BThe image shows a cross-section after the deposition of the STI structure 118. The STI structure 118 forms a dielectric gap fill between the nanosheet region 116 and the substrate 104. The STI structure 118 may include trench sidewall spacers 113 and deposited oxide, such as oxide formed by a high-density plasma (HDP) oxide deposition process.

[0039] refer to Figure 7A and Figure 7B The image shows a cross-section after the STI structure 118 outside the superlattice sidewall trenches has been removed by a chemical mechanical polishing (CMP) process 119. The STI structure 118 acts as a gap filler between the nanosheet region 116 and the substrate 104. After the CMP process 119, the first hard mask layer 109 and the first pad oxide layer 108 are removed.

[0040] refer to Figure 8A and Figure 8B The image shows a cross-section after trench 124 has been formed. A second pad oxide layer 120 and a hard mask layer 121 (e.g., SiN or SiON) have been formed, and a mask layer 122 (e.g., an organic photoresist) has been patterned with openings above the location where trench 124 will be formed. An etching process 123 removes portions of the hard mask layer 121, the second pad oxide layer 120, the n-type doped silicon layer 114a, and the sacrificial layer 115 below the openings in the mask layer 122. The etching process 123 may include multiple steps as needed to remove different material layers. After trench 124 is formed, the mask layer 122 is removed.

[0041] refer to Figure 9A and Figure 9B The diagram shows a cross-section after the formation of a sacrificial polysilicon-germanium layer 125 (sometimes referred to as a polycrystalline SiGe layer 125) in the top surface 107 and sacrificial polysilicon / germanium trench 124 of the nanosheet transistor 101. Following the formation of the polycrystalline SiGe layer 125, a portion of the polycrystalline SiGe layer 125 on the top surface 107 outside the sacrificial polysilicon / germanium trench 124 is removed using photo-patterning and plasma etching steps (neither specifically shown in the diagram). The outer boundary of the polycrystalline SiGe layer 125 lies above the STI structure 118. The polycrystalline SiGe layer can be formed using CVD or ALD methods. The polycrystalline SiGe layer 125 may have a thickness 127, which may be approximately the same thickness 128 as the n-type doped silicon layer 114a, for example, within ten percent. Process 126 represents the growth process and patterning of the polycrystalline SiGe layer 125.

[0042] refer to Figure 10A and Figure 10BThe image shows a cross-section after the formation of the source trench 133. A third pad oxide layer 129 is formed over the top surface 107 of the substrate 104 and the polycrystalline SiGe layer 125. A third hard mask layer 130 is formed on the third pad oxide layer 129. After forming the source optical lithography pattern 131, the third hard mask layer 130, the third pad oxide layer 129, and the nanosheet region 116 can be etched in the open areas of the source optical lithography pattern 131 using source trench etching 132 (which may include multiple steps).

[0043] refer to Figure 11A and Figure 11B The image shows a cross-section after a portion of the sacrificial layer 115 and polycrystalline SiGe layer 125 of nanosheet region 116 has been selectively removed by a plasma etching or wet etching process (not specifically shown). The sacrificial layer 115 and polycrystalline SiGe layer 125 are removed via exposed regions in source trench 133. The plasma etching or wet etching process used to remove portions of the sacrificial layer 115 and polycrystalline SiGe layer 125 can be timed etching to control the removal of portions of the sacrificial layer 115 and polycrystalline SiGe layer 125, thereby forming a first superlattice void 134, in which the remaining p-type doped portion of silicon layer 114 and the n-type doped silicon layer 114a remain between the first superlattice void 134. The first superlattice void 134 suspends the remaining portion of silicon layer 114 and the exposed portion of n-type doped silicon layer 114a above substrate 104, located in the region of silicon layer 114 closest to source trench 133. After removing the portion of the sacrificial layer 115 and the polycrystalline SiGe layer 125 closest to the source trench 133, a cleaning process that may include supercritical CO2 can be used to remove the residue.

[0044] refer to Figure 12A and Figure 12B The image shows a cross-section after a portion of the silicon layer 114 suspended above the substrate has been thinned using an optional isotropic etching process (not specifically shown) to form a p-type nanosheet channel layer 135c and a thin n-type drift region 135d. The isotropic etching process can be a gas-phase process with high partial pressure HCl, or a low-pressure plasma process with CF4 / O2 / He, or a similar process. Alternatively, a wet etching process containing HF, hydrogen peroxide, and acetic acid, or similar chemicals, can be used. The isotropic etching removes a portion of the silicon layer 114, leaving a thinned silicon layer 135 comprising the channel layer 135c and the thin n-type drift region 135d. In the gate region 158 (see...) Figure 1C The thinned silicon layer 135, formed by silicon layer 114, provides improved mechanical stability during fabrication. In field plate area 159 (see...) Figure 1CIn this process, the n-type doped silicon layer 114a is not thinned, which reduces the sheet resistance of the final drift region formed later in the field plate region 159. The silicon layer 114 can be trimmed to 33% of its initial thickness. The thinned channel layer 135c improves channel control of the nanosheet transistor 101.

[0045] refer to Figure 13A and Figure 13B The image shows a cross-section after the formation of the gate dielectric layer 136 and the first conductive layer 137 (sometimes referred to as gate layer 137). The gate dielectric layer 136 is formed on the exposed surface of the nanosheet transistor 101 (e.g., a portion of the substrate 104, a portion of the sacrificial layer 115, a portion of the polycrystalline SiGe layer 125, the third hard mask layer 130, and the thinned channel layer 135c). The gate layer 137 is formed on the gate dielectric layer 136. The gate dielectric layer 136 may be a material such as HfO / ZrO, or ZrO2, or other high-k materials, having a thickness between 1 nm and 2.5 nm. The thickness of the gate layer 137 allows it to fill the first superlattice voids 134. In various examples, the gate layer 137 may be TiAlN, TiN, or other suitable materials.

[0046] refer to Figure 14A and Figure 14B The image shows a cross-section after a portion of the gate layer 137 has been removed in gate metal etching process 160. Gate metal etching process 160 removes all of the gate layer 137 on the gate dielectric layer 136 above the third hard mask layer 130 in the source trench 133, as well as a portion of the gate layer 137 between the thinned channel layers 135c. In nanosheet transistor 101, the remaining portion of the gate layer 137 that contacts the thinned channel layer 135c is electrically active, while the remaining portion of the gate layer 137 above the STI structure 118 is not electrically active. When the gate dielectric layer 136 is a high-k gate dielectric, the gate dielectric layer 136 can provide additional hard mask margin during the removal of the gate layer 137.

[0047] refer to Figure 15A and Figure 15B The image shows a cross-section after the gate spacer 139 has been formed using conformal dielectric deposition and anisotropic dielectric etching (neither specifically shown). When the gate dielectric layer 136 is a high-k gate dielectric, it provides additional etch stop margin during the anisotropic etching of the gate spacer 139 compared to the standalone third hard mask layer 130. The gate spacer 139 may be silicon nitride, silicon oxynitride, silicon dioxide, or other dielectric materials. The gate spacer 139 is located at... Figure 15BThe front of the plane of the cross section. After forming the gate spacer 139, the third hard mask layer 130 and the gate dielectric layer 136 above the exposed area on the substrate 104 in the source trench 133 are removed.

[0048] refer to Figure 16 The image shows a cross-section after the source region 141 is formed by a selective n-type polysilicon deposition process 140. The selective n-type polysilicon deposition process 140 fills the source region 141 with polysilicon, wherein the polysilicon is not deposited on the third hard mask layer 130. Alternatively, the source region 141 may be formed by a blanket coating of polysilicon filling the source trench 133 and covering the third hard mask layer 130, followed by a polysilicon CMP process.

[0049] refer to Figure 17A and Figure 17B The image shows a cross-section after the formation of the drain trench 144. A fourth hard mask layer 163 is formed on the third hard mask layer 130, and a drain trench optical lithography pattern 142 is formed. The fourth hard mask layer 163, the third hard mask layer 130, the third pad oxide layer 129, and the nanosheet region 116 in the open region of the drain trench optical lithography pattern 142 can be etched using a drain trench etching 143 that may include multiple steps. The fourth hard mask layer 163 may be thinner than the third hard mask layer 130. After the formation of the drain trench 144, the drain trench optical lithography pattern 142 is removed.

[0050] refer to Figure 18A and Figure 18B The image shows a cross-section after a portion of the sacrificial layer 115 and polycrystalline SiGe layer 125 of the nanosheet region 116 has been selectively removed from the drain trench 144 using a plasma etching or wet etching process. The removal of the sacrificial layer 115 and polycrystalline SiGe layer 125 forms a second superlattice void 145. During the formation of the second superlattice void 145, all sacrificial layer 115 material is removed, with the second superlattice void 145 extending from the drain trench 144 to the gate dielectric layer 136. The second superlattice void 145 leaves a portion of the n-type doped silicon layer 114a, which may now be referred to as the drain drift layer 138. The drain drift layer 138 is suspended above the substrate 104 in the second superlattice void 145 between the gate dielectric layer 136 and the drain trench 144. The drain drift layer 138 is attached via the gate dielectric layer 136 and the gate layer 137. After removing the sacrificial layer 115 closest to the drain trench 144, a cleaning process including supercritical CO2 can be used to remove the residue.

[0051] refer to Figure 19A and Figure 19BThe image shows a cross-section after the formation of the field release dielectric layer 146 and the field plate layer 147. The field release dielectric layer 146 is thicker than the gate dielectric layer 136, which allows the nanosheet transistor 101 to operate at higher voltages. The field release dielectric layer 146 is formed on the exposed surfaces of the nanosheet transistor 101 (e.g., portions of the substrate 104, the n-type doped silicon layer 114a, and the fourth hard mask layer 163). The field plate layer 147 is formed on the field release dielectric layer 146. The field release dielectric layer 146 can be between 2.5 nm and 10 nm. The field plate layer 147 can be thick enough to fill the second superlattice voids 145. For example devices, NMOS and LDMOS, the field plate layer 147 can be TaN or another material with a work function higher than that of the gate layer 137. For PMOS devices, the field plate layer 147 can be tungsten or another metal layer material with a work function lower than that of the gate layer 137.

[0052] refer to Figure 20 The image shows a cross-section after a portion of the field layer 147 has been removed by the field metal etching process 161. The field metal etching process removes all of the field layer 147 in the drain trench 144 and above the fourth hard mask layer 163. Field metal etching process 161 removes portions of the field layer 147 between the n-type doped silicon layers 114a closest to the drain trench 144, leaving portions of the field layer 147 between nanosheets in the region closest to the source region 141. The amount of field layer 147 remaining after the field metal etching process can be adjusted by changing the timing of the field metal etching process. When the field release dielectric layer 146 is a high-k dielectric, the field release dielectric layer 146 can provide additional hard mask margin during the removal of the field layer 147.

[0053] refer to Figure 21 The image shows a cross-section after the field spacer 149 has been formed using conformal dielectric deposition and anisotropic dielectric etching (neither specifically shown). When the field release dielectric layer 146 is a high-k gate dielectric, it can provide additional etch stop margin during the anisotropic etching of the field spacer 149 when used alone in conjunction with the fourth hard mask layer 163 and the third hard mask layer 130. The field spacer 149 can be silicon nitride, silicon oxynitride, silicon dioxide, or other dielectric materials. After the field spacer 149 is formed, the field release dielectric layer 146 above the exposed areas on the substrate 104 in the fourth hard mask layer 163 and drain trench 144 is removed.

[0054] refer to Figure 22The image shows a cross-section after the formation of the drain region 151 in a selective n-type polysilicon deposition process 162. The selective n-type polysilicon deposition process 162 fills the drain region 151 with polysilicon, wherein the polysilicon is not deposited on a fourth hard mask layer 163. The fourth hard mask layer 163 prevents n-type polysilicon deposition on the source region 141. An alternative method for forming the drain region 151 could be to form a polysilicon blanket film that also fills the drain trench 144, and then form the drain region 151 using a polysilicon CMP process.

[0055] Additional routine processing can be performed to form Figure 1C The PMD layer 153, source contact 154, drain contact 155, gate contact 156, and metal terminal 157 are described in the document.

[0056] While various examples of this disclosure have been described above, it should be understood that they are presented by way of example only and not limitation. Thus, although the foregoing examples of using various resist layers (e.g., photoresist or photomask layers) to perform various process steps (e.g., implantation or etching steps) have been described, this disclosure is not limited thereto. For example, one or more hard masks (comprising one or more layers) may be patterned to define various regions for subsequent process steps to be applied (e.g., regions for receiving dopant atoms, regions for blocking etchants). Furthermore, in some examples, the resist layer may comprise multiple layers of resist instead of a single layer. Many changes may be made to the disclosed examples based on the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined according to the appended claims and their equivalents.

Claims

1. A microelectronic device comprising: A first doped semiconductor region and a second doped semiconductor region extending into a semiconductor substrate, the first and second doped semiconductor regions having a first conductivity type and the semiconductor substrate having the opposite second conductivity type; A semiconductor layer that contacts the first doped semiconductor region and the second doped semiconductor region; A first dielectric layer, which contacts the first doped semiconductor region; A second dielectric layer is in contact with the second doped semiconductor region; A first conductive layer contacts the first dielectric layer, wherein the first dielectric layer separates the first conductive layer from the first doped semiconductor. A third dielectric layer separates the first conductive layer from the semiconductor layer; A second conductive layer contacts the second dielectric layer, wherein the second dielectric layer separates the second conductive layer from the second doped semiconductor. and A fourth dielectric layer separates the second conductive layer from the semiconductor layer, wherein the second dielectric layer and the fourth dielectric layer are located between the first conductive layer and the second conductive layer.

2. The microelectronic device according to claim 1, wherein the semiconductor layer is one of a first and a second semiconductor layer connected between the first doped semiconductor region and the second doped semiconductor region, and the first and second conductive layers, the third dielectric layer and the fourth dielectric layer are located between the first semiconductor layer and the second semiconductor layer.

3. The microelectronic device of claim 1, wherein the first doped semiconductor region is a source region and the second doped semiconductor region is a drain region, the source region and the drain region have a first average dopant concentration, and the microelectronic device further includes a drain drift region in the semiconductor layer, the drain drift region having the first conductivity type and a lower second dopant concentration and extending from the drain region to the source region.

4. The microelectronic device according to claim 1, wherein the dielectric constants of the third dielectric layer and the fourth dielectric layer are greater than 3.

9.

5. The microelectronic device according to claim 1, wherein the work function of the first conductive layer and the second conductive layer is greater than 3.9 eV.

6. The microelectronic device according to claim 1, wherein the first conductive layer and the second conductive layer are selected from the group consisting of TiAlN, TiN, TaN, Al, TaSiN, MoN and W.

7. The microelectronic device according to claim 1, wherein the thickness of the semiconductor layer is greater than 10 nm.

8. The microelectronic device of claim 1, wherein the fourth dielectric layer is thicker than the third dielectric layer.

9. The microelectronic device of claim 1, wherein the gate contact is electrically connected to the first conductive layer and the second conductive layer.

10. A method of forming a microelectronic device, comprising: Trenches are formed in a semiconductor substrate having a first conductivity type; A stack of semiconductor nanosheets, comprising a semiconductor layer and a sacrificial layer, is formed in the trench. A source trench is formed in the semiconductor nanosheet stack, and the portion of the sacrificial layer that contacts the source trench is removed, exposing the portion of the semiconductor layer closest to the source trench. A third dielectric layer is formed in contact with the semiconductor layer. A first conductive layer is formed in contact with the third dielectric layer; A first dielectric layer is formed between the first conductive layer and the source trench; A first doped semiconductor region is formed by filling the source trench with a first doped semiconductor of the first conductivity type, wherein the first doped semiconductor is the source region; A drain trench is formed in the semiconductor nanosheet stack, and the sacrificial layer that contacts the drain trench is removed, thereby exposing the portion of the semiconductor layer closest to the drain trench. A fourth dielectric layer is formed on the semiconductor layer; A second conductive layer is formed on the fourth dielectric layer; A second dielectric layer is formed between the second conductive layer and the drain trench; and A second doped semiconductor region is formed by filling the drain trench with a second doped semiconductor of the first conductivity type, wherein the second doped semiconductor is the drain region.

11. The method of claim 10, wherein forming the semiconductor nanosheet stack comprises forming a first and a second semiconductor layer, including the sacrificial layer located between the first semiconductor layer and the second semiconductor layer.

12. The method of claim 10, further comprising forming a drain drift region in the semiconductor substrate, the drain drift region having the first conductivity type and an average dopant concentration less than that of the drain region and extending from the drain region toward the source region.

13. The method of claim 10, further comprising forming the third dielectric layer and the fourth dielectric layer having a dielectric constant greater than 3.

9.

14. The method of claim 10, comprising a first conductive layer and a second conductive layer having a power function greater than 3.9 eV.

15. The method of claim 10, further comprising forming the first conductive layer and the second conductive layer selected from the group consisting of TiAlN, TiN, TaN, Al, TaSiN, MoN and W.

16. The method of claim 10, further comprising forming the semiconductor layer with a thickness greater than 10 nm.

17. The method of claim 10, further comprising forming a fourth dielectric layer with a thickness greater than that of the third dielectric layer.

18. The method of claim 10, further comprising forming a gate contact electrically connected to the first conductive layer and the second conductive layer.

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