Chip package structure and method
By using chip staggered stacking and TMV technology, vertical interconnection of multi-layer chips is achieved, solving the problems of signal interconnection and product size limitations in traditional multi-chip stacking packaging. This results in a high-efficiency and low-cost packaging structure, improved power and signal integrity, reduced package size, and improved performance.
Patent Information
- Application Number
- CN202610414861.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-30
AI Technical Summary
In traditional multi-chip stacking packaging, signal interconnection and product size limitations are mutually restrictive, resulting in high process difficulty and high cost, making it difficult to meet the demand for high efficiency and low cost.
By employing chip staggered stacking combined with TMV technology, through-holes are fabricated within the plastic package and metallized, redistribution lines are set up and ball-mounted, achieving vertical interconnection of multi-layer chips, and using a solid metallization scheme to improve power and signal integrity.
It effectively utilizes space, reduces package size, increases I/O density and bandwidth, reduces power consumption, improves read and write performance of storage products, and is suitable for large-scale integration.
Smart Images
Figure CN122318908A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a chip packaging structure and method. Background Technology
[0002] With the continuous development of integrated circuit technology, the requirements for electronic products in terms of computing power, performance, size, power consumption, and cost are becoming increasingly higher. However, Moore's Law is approaching its limit, and a single chip often cannot meet product requirements. As a result, integrated circuit professionals are increasingly focusing on the field of advanced packaging. Multi-chip stacking packaging provides an effective solution to the above problems.
[0003] However, in the process of multi-chip stacking and packaging, the signal interconnection of each chip and the product size are mutually constrained. Traditional stacking and packaging methods often require complex interconnection structures to be completed within a limited size, which is difficult and costly. There is an urgent need for an efficient and low-cost chip stacking and packaging structure and method. Summary of the Invention
[0004] To address the problems in the prior art, the present invention aims to provide a chip packaging structure and method.
[0005] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: A chip packaging structure includes a molding compound I, which encapsulates at least four layers of chips. Through-holes are formed on the molding compound I and metallized thereon. Redistribution lines are provided on the molding compound I, and balls are placed on the redistribution lines.
[0006] Furthermore, the encapsulated body I contains four layers of chips. The bottom two layers are chips with a back adhesive layer and a bump structure, while the top two layers do not contain a bump structure.
[0007] This invention also discloses a chip packaging method, comprising the following steps: Step 1: Preprocess the wafer to obtain the chip; Step 2: Prepare a temporary carrier board and a temporary bonding layer on it; Step 3: Apply adhesive film to the temporary bonding layer; Step 4: Mount at least four layers of chips with the face up; Step 5: Perform plastic encapsulation on the mounted chips to obtain encapsulated body I; Step Six: Create a plastic-sealed through-hole; Step 7: Metallize the plastic-sealed through-holes created in the above steps; Step 8: Fabricate redistribution circuitry on the product obtained in Step 7; Step 9: Remove the temporary carrier plate and the temporary bonding layer on it, and carry out processes such as ball planting, grinding, marking, and cutting to obtain the final product.
[0008] Furthermore, in step one, the preprocessing of the wafer to obtain the chip includes: The wafer is thinned and separated into individual chips. Bump structures are then fabricated on the individual chips and thinned and separated into individual chips again. A back adhesive layer may or may not be provided depending on the mounting location.
[0009] Furthermore, in step four, four layers of chips are mounted with the surface facing upwards. The bottom two layers are chips with a back adhesive layer, while the top two layers do not contain bump structures.
[0010] Furthermore, in step six, through-holes are fabricated at the locations of the lower-layer chip pads using laser drilling or dry etching.
[0011] Furthermore, the sidewall angle of the plastic-sealed through hole should be greater than 60°, and the ratio of its depth to its opening diameter should be greater than 0.5:1.
[0012] Furthermore, in step seven, the metallization process includes: physical vapor deposition followed by copper electroplating, chemical copper plating followed by copper electroplating, or filling with conductive paste and sintering.
[0013] Furthermore, the conductive paste is a conductive copper paste or a conductive silver paste.
[0014] Furthermore, in step seven, the metal post-processing yields a solid or overmolded metal morphology.
[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves vertical interconnection of multi-layer chips by combining chip staggered stacking with TMV technology, effectively utilizing space and reducing package size; the TMV vias adopt a solid metallization scheme, which can effectively improve the power integrity and signal integrity of the product, improve the read and write performance of the storage product, increase I / O density and bandwidth, and reduce power consumption; the package structure can include multiple stacked structure arrays, which is suitable for large-scale integration and improves package density. Attached Figure Description
[0016] Figure 1-3 This is a structural schematic diagram of step one of the present invention; Figure 4 This is a schematic diagram of the structure of step two of the present invention; Figure 5 This is a schematic diagram of step three of the present invention; Figure 6 This is a structural schematic diagram of step four of the present invention; Figure 7This is a structural schematic diagram of step five of the present invention; Figure 8 This is a schematic diagram of step six of the present invention; Figure 9 This is a structural schematic diagram of step seven of the present invention; Figure 10 This is a structural schematic diagram of step eight of the present invention; Figure 11 This is a schematic diagram of step nine of the present invention. Detailed Implementation
[0017] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.
[0018] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.
[0019] like Figure 1-11 As shown, the present invention discloses a chip packaging structure, including a molding compound I8, which encapsulates at least four layers of chips. A molding through-hole 9 is formed on the molding compound I8 and metallized thereon. A redistribution line 10 is provided on the molding compound I8, and balls 11 are placed on the redistribution line 10.
[0020] A chip packaging method includes the following steps: Step 1: [The following text appears to be a separate, unrelated section:] ... Figure 1 Wafer 1 shown is subjected to the following processing: thinning and separation process to form as shown Figure 2 The single chip shown is for backup. Bump structures 2 can be fabricated on the single chip and then thinned and separated into single chips 3, thereby reducing the difficulty of TMV fabrication and improving yield. A back adhesive layer 4 can be set according to the mounting position, such as... Figure 3 As shown, the back adhesive layer 4 can also be omitted depending on the mounting position, further reducing costs.
[0021] Step Two: As Figure 4 As shown, a temporary carrier 5 and a temporary bonding layer 6 thereon are prepared. The temporary carrier 5 is not limited to a metal carrier or a glass carrier, but can also be a carrier of other suitable materials. The temporary bonding layer 6 includes, but is not limited to, temporary bonding adhesive and temporary bonding film.
[0022] Step 3: As Figure 5As shown, a layer of adhesive film 7 is applied to the temporary bonding layer 6 to protect the back of the chip.
[0023] Step Four: As Figure 6 As shown, apply two layers with the face up. Figure 3 The chip 3 shown and the two layers as shown Figure 2 The misalignment distance between the two chip layers shown (without bump structure 2) is determined by the position and size of the wafer pads / bumps. The specific misalignment size is not limited here; only the stability of the stacked structure needs to be ensured. The choice of which chips use the chip with bump structure 2 is determined by the TMV and its metallization capabilities.
[0024] Step 5: As Figure 7 As shown, the mounted chip is encapsulated to obtain encapsulated body I8. The encapsulation thickness can be adjusted according to the total thickness required by the product.
[0025] Step Six: As Figure 8 As shown, through-holes 9 are fabricated at the pad positions of the lower chip by laser drilling or dry etching. The sidewall angle of the through-hole 9 should be greater than 60°, and the ratio of its depth to its opening diameter should be greater than 0.5:1. The presence of the low bump structure 2 reduces the TMV yield and helps to improve the yield.
[0026] Step Seven: As Figure 9 As shown, the vias 9 fabricated in the above steps are metallized. Metallization methods include, but are not limited to, PVD + copper plating, electroless copper plating + copper plating, filling with conductive paste (including but not limited to conductive copper paste and conductive silver paste) and sintering. Furthermore, the resulting metallized form can be solid or overlay. This embodiment demonstrates a PVD + copper plating solid conductive path scheme. Solid metallization, compared to overlay metallization, can effectively improve the power integrity and signal integrity of the product, enhance the read / write performance of the storage product, increase I / O density and bandwidth, and reduce power consumption. Solid metallized vias can be fabricated using stacked vias, further shortening the circuit length and reducing the package size.
[0027] Step 8: As Figure 10 As shown, redistributed circuitry 10 is fabricated on the product obtained in step seven. The specific number and specifications of the circuitry layers are determined by the specific product to improve packaging efficiency.
[0028] Step Nine: Figure 11 As shown, the temporary carrier plate 5 and the temporary bonding layer 6 on it are removed, and the processes of ball planting 11, grinding, marking, and cutting are carried out to obtain the final product.
[0029] It should be noted that: 1. This embodiment only shows the stacking method of four-layer chips, but it is not limited to this. The method of this patent can be used to continue stacking six or eight layers, as long as the chip size and process capability can achieve it, the number of layers is not limited; 2. This embodiment ultimately includes a structure of four chips stacked in one place, but a package is not limited to this. Stacked structures can be integrated into the same package in an array; 3. Each stack is not limited to two layers. Depending on the actual product and technical capabilities, it can be any number of layers ≥1.
[0030] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.
[0031] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A chip packaging structure, characterized in that, The device includes a molding compound I, which encapsulates at least four layers of chips. The molding compound I has through-holes and is metallized. The molding compound I has redistribution lines and ball-mounted on the redistribution lines.
2. The chip packaging structure according to claim 1, characterized in that, The encapsulation body I contains four layers of chips. The bottom two layers are chips with a back adhesive layer and a bump structure, while the top two layers do not contain a bump structure.
3. A chip packaging method, characterized in that, Includes the following steps: Step 1: Preprocess the wafer to obtain the chip; Step 2: Prepare a temporary carrier board and a temporary bonding layer on it; Step 3: Apply adhesive film to the temporary bonding layer; Step 4: Mount at least four layers of chips with the face up; Step 5: Perform plastic encapsulation on the mounted chips to obtain encapsulated body I; Step Six: Create the plastic-sealed through-hole; Step 7: Metallize the plastic-sealed through-holes created in the above steps; Step 8: Fabricate redistribution circuitry on the product obtained in Step 7; Step 9: Remove the temporary carrier plate and the temporary bonding layer on it, and carry out processes such as ball planting, grinding, marking, and cutting to obtain the final product.
4. The chip packaging method according to claim 3, characterized in that, Step one, the preprocessing of the wafer to obtain the chip, includes the following steps: The wafer is thinned and separated into individual chips. Bump structures are then fabricated on the individual chips and thinned and separated into individual chips again. A back adhesive layer may or may not be provided depending on the mounting location.
5. A chip packaging method according to claim 3, characterized in that, In step four, four layers of chips are mounted with the face up. The bottom two layers are chips with a back adhesive layer, and the top two layers do not contain bump structures.
6. A chip packaging method according to claim 3, characterized in that, In step six, through-holes are created at the locations of the pads on the lower-layer chip using laser drilling or dry etching.
7. A chip packaging method according to claim 6, characterized in that, The sidewall angle of the plastic-sealed through hole should be greater than 60°, and the ratio of its depth to its opening diameter should be greater than 0.5:
1.
8. A chip packaging method according to claim 3, characterized in that, In step seven, the metallization process includes: physical vapor deposition followed by copper electroplating, chemical copper plating followed by copper electroplating, or filling with conductive paste and sintering.
9. A chip packaging method according to claim 8, characterized in that, The conductive paste is a conductive copper paste or a conductive silver paste.
10. A chip packaging method according to claim 7, characterized in that, In step seven, the metal post-processing yields a solid or overmolded metal morphology.