A multi-type device adapted semiconductor low frequency noise measurement system

Abstract

This application relates to the field of semiconductor device parameter testing technology, and discloses a semiconductor low-frequency noise measurement system adaptable to multiple types of devices, comprising a hardware measurement and software analysis subsystem. The hardware measurement subsystem includes a low-noise power supply and bias module, a dual-path device adapter, a multi-channel synchronous acquisition module, and a hierarchical adaptive preamplifier. The system superimposes a high-frequency perturbation sensing signal onto the measurement link, extracts feedback parameters to calculate the equivalent input impedance, quantizes the physical pole frequency, drives a controlled analog switch matrix to generate controlled physical zeros, and cancels additional low-pass poles caused by impedance mismatch. The dual-path device adapter synchronously extracts the mixed signal of the test channel and the common-mode leakage signal of the reference channel; the software analysis and control module reconstructs the transfer function, uses coherence coefficients to dynamically weight and fuse the physical prior and data-driven model, performs coherent subtraction and full-link inversion compensation in the complex frequency domain, and outputs a clean equivalent noise voltage spectral density sequence.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device parameter testing technology, specifically to a semiconductor low-frequency noise measurement system adaptable to multiple types of devices. Background Technology

[0002] Semiconductor low-frequency noise is a crucial physical parameter for evaluating the reliability and internal interface defect density of microelectronic devices. With the evolution of semiconductor manufacturing processes, the intrinsic noise amplitude of devices has gradually decreased, placing higher demands on the weak signal extraction capabilities of measurement systems. In practical testing environments, the device under test (DUT) and the preamplifier circuit of the measurement system form a physical coupling network. Different types of semiconductor devices have different dynamic resistances and junction capacitances. These internal parameters interact with the parasitic capacitances of external test cables and fixtures, introducing low-pass poles that dynamically change with the DUT in the measurement link. These poles cause attenuation of high-frequency signals within the target frequency band, leading to distortion of the extracted noise spectral density. Existing systems typically employ fixed-gain and fixed-bandwidth hardware architectures or rely on manual offline calibration, failing to provide adaptive broadband flatness compensation for the complex impedance characteristics of various device types.

[0003] To broaden the system's device compatibility, some measurement techniques attempt to introduce programmable passive component arrays into the signal conditioning link to adjust amplifier parameters. However, during the switching of the underlying hardware physical topology, the transient action of analog switches can induce internal charge injection and clock feedthrough effects. When different capacitor and resistor branches are directly switched on or off, the redistribution of residual charge can easily trigger instantaneous inrush currents. This transient interference between hardware levels can disrupt the original DC bias steady state of the measurement link, causing prolonged baseline drift and time-domain data contamination for already extremely weak low-frequency noise signals.

[0004] Furthermore, the measurement frequency band for semiconductor low-frequency noise often overlaps significantly with the mains power frequency and its harmonics, making the measurement process susceptible to common-mode interference such as spatial electromagnetic radiation and ground return current. Traditional measurement architectures often employ single-path acquisition or differential subtraction methods based on the assumption of ideal symmetry. Due to the asymmetry between the endpoint impedance and parasitic path in the actual test physical link, simple differential methods cannot establish an accurate common-mode noise leakage propagation model. This single processing mechanism struggles to effectively isolate the system's common-mode leakage signal from the true intrinsic noise of the device under test in complex electromagnetic interference environments, thus limiting the final extraction accuracy of the low-frequency noise spectral density. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a semiconductor low-frequency noise measurement system adaptable to multiple types of devices. It aims to solve the problems in existing technologies, such as measurement frequency band distortion caused by impedance mismatch between different types of devices, transient surge interference caused by switching actions during hardware parameter adjustment, and difficulty in accurately isolating common-mode leakage noise in complex electromagnetic environments.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a semiconductor low-frequency noise measurement system adaptable to multiple device types, comprising a hardware measurement subsystem and a software analysis subsystem: The hardware measurement subsystem includes a low-noise power supply and bias module, a dual-path device adapter, a multi-channel synchronous acquisition module, and a hierarchical adaptive preamplifier. The low-noise power supply and bias module connects to the device under test (DUT), providing it with operating voltage and DC bias voltage, and superimposing a high-frequency perturbation sensing signal onto the measurement link. The dual-path device adapter has symmetrically arranged test and reference channels. The test channels connect to the DUT and extract mixed signals, while the reference channels extract common-mode leakage signals. The multi-channel synchronous acquisition module synchronously receives analog noise signals from the test and reference channels and converts them into digital sequences. The hierarchical adaptive preamplifier connects the DUT to the multi-channel synchronous acquisition module, amplifying the input signal and receiving external control commands to adjust the frequency response characteristics of the hardware physical link. The software analysis subsystem includes a software analysis and control module, which establishes a communication connection with the hardware measurement subsystem. It receives digital sequences and performs equivalent impedance calculations, transfer function reconstruction, and coherence cancellation operations, outputting the equivalent noise voltage spectral density sequence at the input of the DUT.

[0007] In one specific embodiment, the low-noise power supply and bias module integrates an admittance feature injection unit. The hierarchical adaptive preamplifier includes a first-stage fixed-gain stage and a second-stage topology reconstruction stage connected in series. The first-stage fixed-gain stage uses a fixed-parameter topology to perform primary amplification of the input signal; the second-stage topology reconstruction stage internally incorporates a controlled analog switch matrix and a passive component array, used to switch the parameters of the connected passive component array to adjust the frequency response characteristics.

[0008] Preferably, the admittance feature injection unit outputs a continuous sine wave of a fixed frequency as a high-frequency perturbation sensing signal, which is then superimposed onto the DC bias voltage loop. The multi-channel synchronous acquisition module digitizes the amplified response voltage signal to generate a digital response sequence. The software analysis and control module performs orthogonal synchronous detection on the digital response sequence, extracting the feedback amplitude and feedback phase of the high-frequency perturbation sensing signal. Subsequently, it calls an impedance inversion algorithm to calculate the total equivalent input impedance using the feedback amplitude and feedback phase, and then solves for the equivalent series resistance and parasitic capacitance by separating the real and imaginary parts of the total admittance.

[0009] Furthermore, the software analysis and control module utilizes the calculated equivalent series resistance and parasitic capacitance to quantify the actual physical pole frequencies generated by impedance mismatch in the first-stage fixed-gain stage. Based on these actual physical pole frequencies, the software analysis and control module generates target zero frequencies and, in conjunction with an internally pre-set hardware database, executes the optimization mapping logic for the discrete passive component array, outputting the globally optimal switch combination index number. The controlled analog switch matrix receives serial control commands and, based on the globally optimal switch combination index number, generates controlled physical zeros in the feedback loop of the second-stage topology reconstruction stage to cancel parasitic poles, thereby reconstructing the inter-stage synthetic transfer function.

[0010] Preferably, the controlled analog switch matrix employs a time-delay switching control logic of "break first, then turn on" when performing physical actions. This time-delay switching control logic is configured with a preset hardware dead time to release residual accumulated charge in capacitor components and prevent transient surge currents caused by short circuits in different branches. After the physical switch action is completed and the control level is latched, the control measurement link enters a silent waiting period, allowing the amplifier bias current and node voltage to return to a stable DC steady state.

[0011] In one specific embodiment, a minimal damping correction factor is introduced into the denominator during the calculation of the interstage synthesized transfer function. This minimal damping correction factor is used to prevent arithmetic division-by-zero overflow at singular points of the transfer function, ensuring the convergence of frequency domain operations and the stability of numerical computation.

[0012] Preferably, the multi-channel synchronous acquisition module, based on a global trigger control word, executes synchronization trigger logic on the test channel and the reference channel under the condition of meeting the time deviation constraint of hardware synchronization alignment between channels, generating a dual-path synchronous observation matrix with strict time domain alignment. The dual-path synchronous observation matrix is ​​fully mapped to the pre-allocated memory area of ​​the host computer through direct memory access technology, via first-in-first-out data cache queue trigger block movement.

[0013] Furthermore, the software analysis and control module reconstructs the frequency-varying network impedance based on the asymmetric physical boundary conditions of the endpoints, deriving a physical prior model of the common-mode noise leakage transfer function. Simultaneously, the software analysis and control module performs a windowed discrete Fourier transform on the dual-path synchronous observation matrix, calculates the power spectral density using the Welch average periodogram method, and solves for the common-mode noise leakage data-driven transfer function.

[0014] Preferably, the software analysis and control module calculates the squared coherence coefficient of the frequency domain signal, and uses the squared coherence coefficient to dynamically weight and fuse the physical prior model and the data-driven transfer function to generate a composite frequency domain leakage weight. Based on the composite frequency domain leakage weight, the software analysis and control module performs a fully complex domain coherent subtraction operation containing real and imaginary parts on a data block-by-data-block basis in the frequency domain, and outputs the digital domain pure power spectral density.

[0015] In one specific embodiment, the software analysis and control module cascades and fuses the interstage integrated transfer function of the hierarchical adaptive preamplifier, the inherent complex transfer function of the low-pass anti-aliasing filter, and the equivalent discretized voltage gain constant of the analog-to-digital converter kernel to reconstruct the full-link integrated transfer function. The software analysis and control module combines the full-link integrated transfer function and performs point-by-point division compensation operation in the frequency domain to invert the pure power spectral density in the digital domain to the equivalent intrinsic power spectral density at the input terminal of the device under test. Then, it performs point-by-point square root operation on the equivalent intrinsic power spectral density at the input terminal to generate the equivalent noise voltage spectral density sequence at the input terminal.

[0016] This invention provides a semiconductor low-frequency noise measurement system adaptable to multiple types of devices. It has the following advantages: 1. This invention superimposes a high-frequency perturbation sensing signal onto the measurement link through an admittance feature injection unit, extracts feedback parameters to calculate the total equivalent input impedance, and uses this to quantize the physical pole frequency. This drives a controlled analog switch matrix to generate corresponding controlled physical zeros in a hierarchical adaptive preamplifier. This can eliminate additional low-pass poles caused by the mismatch between the dynamic impedance of different types of devices under test and the parasitic capacitance of the test link, compensate for the high-frequency attenuation of the physical link, and maintain the flatness of the system amplitude-frequency response within the target measurement frequency band without the need for manual calibration of hardware parameters.

[0017] 2. When the controlled analog switch matrix of the present invention performs passive component array switching operations, it employs a first-off-then-on delay switching timing control logic with a hardware dead time. This provides a buffer time between disconnecting the existing branch and closing the target branch, allowing residual charge in the parasitic capacitor to be released and preventing surge currents caused by instantaneous short circuits between different RC branches. Simultaneously, the subsequent silent waiting period allows the amplifier's bias state to return to DC steady state, avoiding time-domain data pollution caused by the switching charge injection effect on the extraction of weak low-frequency noise.

[0018] 3. This invention obtains the time-domain aligned test channel and reference channel synchronous observation matrix through a dual-path device adapter, calculates the square coherence coefficient of the frequency domain signal, and uses the square coherence coefficient to dynamically weight and fuse the physical prior model and the data-driven transfer function to generate a composite frequency domain leakage weight. Combining the coherent subtraction of the full complex domain and the division inversion operation of the comprehensive transfer function, the influence of the system common-mode leakage noise is eliminated in the digital domain, and the pure intrinsic noise voltage spectral density equivalent to the physical pin of the device under test is obtained. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the system structure of the present invention; Figure 2This is a flowchart of the method of the present invention; Figure 3 This is a schematic diagram comparing the low-frequency noise spectrum of the conventional method and the adaptive measurement method of the present invention in one embodiment of the present invention. Detailed Implementation

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] See attached document Figure 1 The present invention provides a semiconductor low-frequency noise measurement system adaptable to multiple types of devices, the system comprising a hardware measurement subsystem and a software analysis subsystem.

[0022] The hardware measurement subsystem includes a low-noise power supply and bias module. The low-noise power supply and bias module provides the operating voltage for the measurement system and a continuously adjustable DC bias voltage for the device under test. The low-noise power supply and bias module integrates an admittance feature injection unit. This unit is used to superimpose a high-frequency perturbation sensing signal onto the measurement link outside of a preset low-frequency noise test frequency band.

[0023] The hardware measurement subsystem includes a hierarchical adaptive preamplifier. This hierarchical adaptive preamplifier is connected between the output of the device under test (DUT) and the subsequent data acquisition equipment. The hierarchical adaptive preamplifier employs a decoupled front-to-back stage structure, comprising a first-stage fixed-gain stage and a second-stage topology reconstruction stage connected in series.

[0024] The first-stage fixed-gain stage employs a fixed-parameter topology to amplify the input signal and establish the system's reference noise level. The second-stage topology reconstruction stage contains a controlled analog switch matrix and a passive component array, which together form a variable zero-pole compensation network. This second-stage topology reconstruction stage receives external control commands and adjusts the frequency response characteristics of the physical hardware link by switching the controlled analog switch matrix to change the parameters of the passive component array connected to the circuit.

[0025] The hardware measurement subsystem includes a dual-path device adapter. The dual-path device adapter is housed within an electromagnetically shielded enclosure. It provides physical connection fixtures compatible with various semiconductor device package types. Internally, the adapter contains symmetrically arranged test and reference channels. The test channels connect to the device under test (DUT) and are used to extract mixed signals from the load. The reference channel is set to an unloaded state and is used to extract common-mode leakage signals within the system.

[0026] The hardware measurement subsystem includes a multi-channel synchronous acquisition module. The input of the multi-channel synchronous acquisition module is connected to the output of a hierarchical adaptive preamplifier. The multi-channel synchronous acquisition module includes a multiplexer and an A / D converter. The multi-channel synchronous acquisition module is used to synchronously receive analog noise signals corresponding to the test channel and the reference channel, and convert the analog noise signals into a time-domain aligned digital sequence.

[0027] The software analysis subsystem includes a software analysis and control module. This module establishes communication connections with various modules in the hardware measurement subsystem. It sends timing control commands to the low-noise power supply and bias module, the hierarchical adaptive preamplifier, and the multi-channel synchronous acquisition module. The software analysis and control module receives the digital sequence output from the multi-channel synchronous acquisition module, performs equivalent impedance calculation, transfer function reconstruction, and coherence cancellation operations, and outputs the equivalent noise voltage spectral density sequence at the input of the device under test.

[0028] See attached document Figure 2 This invention provides a semiconductor low-frequency noise measurement method adaptable to multiple types of devices, comprising the following steps: S100, depending on the type of device under test, applies an initial DC bias through a low-noise power supply and bias module to bring the device under test into the steady-state operating region; initializes the hierarchical adaptive preamplifier, locks the second-stage topology reconstruction stage to the full bandwidth passband state, and establishes a measurement reference; S200, outside the target measurement frequency band, controls the admittance feature injection unit to inject high-frequency perturbation signals into the measurement link; the software analysis and control module collects feedback responses and calculates the total equivalent input impedance composed of device dynamic resistance, adapter contact resistance and cable parasitic capacitance. S300 quantifies the physical pole offset of the first-stage fixed-gain stage due to impedance mismatch based on the total equivalent input impedance; sends control commands to the second-stage topology reconstruction stage to switch the controlled analog switch matrix to the corresponding variable zero-pole compensation network and generate controlled zeros in the physical link. S400 controls a multi-channel synchronous acquisition module to synchronously acquire physically compensated test channel signals and reference channel signals in the time domain. The test channel signals contain inherent noise and mixed interference of the device under test, while the reference channel signals contain interference signals leaked from bias sources and parasitic paths. The S500 uses the total equivalent input impedance to update the common-mode noise leakage transfer function model, calculates the leakage weight of the reference channel signal in the test channel, and uses a frequency domain coherent subtraction algorithm to remove the common-mode background interference that varies with the load from the test channel signal. The S600 combines the hardware parameters of the variable zero-pole compensation network with the results of common-mode background interference stripping to construct a full-link integrated transfer function. The full-link integrated transfer function is used to perform gain normalization compensation on the processed signal data, and outputs the equivalent noise voltage spectral density sequence at the input of the device under test.

[0029] The above steps will be described in detail below with reference to specific embodiments and accompanying drawings.

[0030] When performing the above-described adaptive measurement method for low-frequency semiconductor noise, step S100 includes the following sub-steps: S101 connects the device under test to the dual-path device adapter and performs physical connection identification.

[0031] In this embodiment, the pins of the device under test (DUT) are inserted into the test fixture inside the dual-path device adapter. Preferably, the test fixture is equipped with zero insertion / removal force sockets and a gold-plated probe array to minimize the attenuation effect of parasitic contact resistance on weak noise signals. The signal output and ground terminals of the DUT are physically connected to the signal input terminal of the test channel and the system reference ground, respectively. After the test channel is physically connected, the reference channel input terminal inside the dual-path device adapter remains floating, providing an open-circuit reference for impedance matching.

[0032] Based on the aforementioned physical architecture, the software analysis and control module reads the preset device configuration file and parses the package type and pin polarity parameters of the device under test. To avoid identification errors caused by judging a single parameter, the system combines the preset file with the preliminary port current and voltage scan results to perform multi-dimensional cross-verification of the device type. For the specific test procedure of determining the device type using the preliminary current and voltage scan, those skilled in the art can use conventional source table parameter test circuit structures; the hardware topology and data extraction logic are well-known technologies in the field and will not be elaborated upon here.

[0033] S102 applies a DC bias voltage through a low-noise power supply and bias module to establish the steady-state operating region of the device under test (DUT). The software analysis and control module sends a digital bias control word to the low-noise power supply and bias module based on the parameters in the device configuration file. The high-precision digital-to-analog converter circuit inside the low-noise power supply and bias module receives the digital bias control word and converts it into an initial analog voltage. The initial analog voltage undergoes out-of-band attenuation through a multi-stage RC low-pass filter network to filter out broadband thermal noise and power supply reference ripple, outputting a DC bias voltage. This DC bias voltage is applied to each working electrode of the DUT, causing the DUT to enter the expected saturation or linear region DC operating state, and waiting for the device to reach thermal equilibrium. During this process, the system continuously monitors the leakage current fluctuation rate at the electrode ports. When the current fluctuation variance for multiple consecutive sampling periods is lower than a preset safety threshold, thermal equilibrium is considered established, thus avoiding transient measurement errors caused by device temperature drift.

[0034] S103 initializes the hierarchical adaptive preamplifier, locking the second-stage topology reconstruction stage to full-bandwidth passband. After the DC operating point of the device under test stabilizes, the software analysis and control module generates an initialization switch command sequence. This sequence consists of a serial binary data stream containing channel address bits and on / off enable bits. The software analysis and control module sends the initialization switch command sequence to the controlled analog switch matrix inside the second-stage topology reconstruction stage via a digital isolation interface. The controlled analog switch matrix receives the command sequence and performs hard-wired logic switching, disconnecting all frequency compensation capacitor branches in the internal passive component array, causing the operational amplifier's feedback loop to exhibit a purely resistive proportional voltage divider characteristic. Based on the ideal closed-loop gain principle of the operational amplifier, when the feedback loop contains only purely resistive components and parasitic capacitance is ignored, its frequency response can be considered constant within the target low-frequency bandwidth. After completing the above configuration, the initial synthesis transfer function formula of the hierarchical adaptive preamplifier is as follows: ; in, This is the initial synthesis transfer function of the hierarchical adaptive preamplifier in the full bandwidth passband state; Operating frequency; This is the inherent voltage amplification factor of the first fixed-gain stage; This represents the reference voltage amplification factor of the second-stage topology reconstruction stage in resistive feedback mode. It should be noted that... and The value of is determined by the ratio of the fixed bias resistor network inside the hardware circuit. Under this full bandwidth passband condition, both are real constants that do not change with frequency. The technical purpose of this synthesized transfer function is to provide an absolutely flat physical gain reference without frequency response distortion for subsequent high-frequency perturbation injection and impedance sensing stages.

[0035] After completing the circuit topology switch, the control level of the controlled analog switch matrix is ​​latched, keeping it silent during subsequent low-frequency noise acquisition cycles. This latching operation ensures that the second-stage topology reconstruction stage exhibits a flat amplitude-frequency response within the target measurement frequency band, and effectively prevents charge injection noise and clock feedthrough effects caused by frequent on / off switching of analog switching devices from interfering with the weak analog signal link, thus establishing a hardware measurement benchmark for accurate low-frequency noise extraction.

[0036] After establishing the aforementioned hardware measurement benchmarks and locking the amplifier topology, the system enters a high-frequency excitation phase aimed at extracting the equivalent impedance characteristics of the physical link without loss. In this embodiment, the specific implementation process includes the following sub-steps: S201, determine the injection frequency of the high-frequency perturbation sensing signal and construct the injection physical path of the perturbation signal in the measurement link. The software analysis and control module determines the operating frequency of the high-frequency perturbation sensing signal according to the preset frequency band isolation principle. Based on the full-bandwidth passband reference established by the hierarchical adaptive preamplifier, the system needs to actively acquire the equivalent composite impedance of the device under test and its physical link. To avoid interference from the probe signal used for impedance sensing with the inherent low-frequency noise spectrum distribution of the device under test, the frequency of the high-frequency perturbation sensing signal must be strictly outside the target measurement frequency band. As a preferred embodiment, the target measurement frequency band of this invention is 1Hz to 100kHz, and the software analysis and control module sets the high-frequency perturbation sensing signal to a continuous sine wave of a fixed frequency. The formula for selecting the frequency of the high-frequency perturbation sensing signal is as follows: ; in, The center frequency of the high-frequency perturbation sensing signal; The highest cutoff frequency of the target measurement band; This represents the frequency band isolation coefficient.

[0037] To ensure thorough frequency band isolation under multi-parameter operating conditions and prevent high-frequency attenuation, the frequency band isolation coefficient... The value of combines the gain-bandwidth product of the operational amplifier with the low-pass cutoff effect of the estimated parasitic capacitance of the device under test, and is usually limited to . Within the real number interval. The technical purpose of this formula is to clarify the frequency domain boundary between the sensed signal and the weak noise signal to be measured from a mathematical and physical perspective, and to ensure the spectral purity of the subsequent low-frequency noise extraction without changing the DC steady-state operating region of the device.

[0038] After determining the center frequency, the system instructs the admittance characteristic injection unit inside the low-noise power supply and bias module to start oscillation. The high-frequency oscillator inside the admittance characteristic injection unit generates a high-frequency perturbation sensing signal corresponding to the frequency. This high-frequency perturbation sensing signal is losslessly superimposed onto the loop of the DC bias voltage output in step S102 through the AC coupling isolation network configured inside the low-noise power supply and bias module. For the calculation of the DC blocking capacitor parameters in the AC coupling isolation network and the selection of the high-frequency blocking inductor in the DC loop, those skilled in the art can use conventional AC / DC coupling bias topologies; their circuit selection and RF impedance matching design are well-known techniques in the field and will not be elaborated upon here.

[0039] A hybrid bias excitation with a high-frequency perturbation sensing signal is transmitted via a low-noise coaxial shielded cable to a dual-path device adapter located inside an electromagnetically shielded box. The hybrid bias excitation flows through the fixture probe array of the test channel and is directly applied to the corresponding signal working electrode of the device under test (DUT). Based on the constructed injection path, the high-frequency perturbation sensing signal penetrates the internal semiconductor channel of the DUT and the external parasitic capacitive structure of the test channel, exciting a response voltage signal carrying full-link impedance characteristics. This response voltage signal is then synchronously fed into the input of a hierarchical adaptive preamplifier, completing the entire execution process from the generation of cross-band characteristic signals in the underlying hardware to the injection into the physical test link.

[0040] S202 controls the multi-channel synchronous acquisition module to digitize the initially amplified response voltage signal and uses the software analysis and control module to perform orthogonal synchronous detection to extract the feedback amplitude and phase of the high-frequency perturbation sensing signal. The response voltage signal, after primary amplification by the first fixed-gain stage and the second topology reconstruction stage, is input to the multi-channel synchronous acquisition module. The high-speed analog-to-digital converter inside the multi-channel synchronous acquisition module discretizes the response voltage signal at a sampling rate much higher than the center frequency to generate a digital response sequence. For the anti-aliasing front-end design and discretization quantization mechanism in the analog-to-digital conversion process, those skilled in the art can use a conventional oversampling converter architecture. Its circuit selection and data buffering logic are well-known technologies in the field and will not be described in detail here.

[0041] Based on the lock-in amplification and correlation detection principles in weak signal detection, after acquiring the digital response sequence, the software analysis and control module generates two local reference sequences in the digital domain that are strictly in sync with the center frequency and orthogonal in phase. To ensure the phase accuracy of the mixing demodulation and the alignment of the multi-source data, the sampling trigger clock of the multi-channel synchronous acquisition module and the emission clock of the admittance feature injection unit share the same high-precision temperature-controlled crystal oscillator, thereby achieving tight time alignment of the input and output data sequences at the physical level.

[0042] The system performs point-by-point multiplication of the digital response sequence with both the local in-phase reference sequence and the local quadrature reference sequence. This nonlinear mixing operation shifts the perturbation characteristics located at the center frequency to the baseband DC position, while simultaneously generating high-frequency components at the second harmonic. Furthermore, the software analysis and control module invokes the internally configured finite-length unit impulse response digital low-pass filter to truncate and smooth the multiplied discrete data, filtering out harmonic spurious signals and low-frequency noise background within the target measurement frequency band, outputting stable in-phase and quadrature DC components. The quadrature synchronous detection and amplitude / phase calculation formulas are as follows: ; ; ; ; in, This is the in-phase DC output extracted after low-pass filtering; The orthogonal DC output is extracted after low-pass filtering. This represents the total number of discrete sampling points extracted within a single detection cycle. The index number of the sampling point in the discrete sequence; The instantaneous amplitude of the digital response sequence output by the multi-channel synchronous acquisition module; The center frequency of the high-frequency perturbation sensing signal; This refers to the discrete sampling period of the multi-channel synchronous acquisition module; The feedback amplitude of the extracted high-frequency perturbation signal; The feedback phase of the extracted high-frequency perturbation signal; It is a minimal constant factor.

[0043] It should be noted that the technical purpose of the orthogonal synchronous detection and amplitude-phase calculation formula is to utilize the correlation detection principle to achieve extremely narrow-band extraction of a specific high-frequency single spectral component in a strong background noise environment. Its equivalent noise bandwidth is limited only by the integration time, i.e., the total number of discrete sampling points. A minimal constant factor is introduced into the feedback phase calculation formula. As a denominator compensation term, it is designed to prevent the in-phase DC quantity from approaching zero due to orthogonal phase reversal of the input signal. This minimal constant factor is typically set to one-hundredth of the system's smallest effective quantization unit, thus avoiding arithmetic overflow errors in the underlying divider without affecting the phase calculation accuracy, and ensuring the system's robustness under extreme parasitic impedance conditions. Based on the aforementioned synchronous detection processing, the software analysis and control module accurately extracts the amplitude and phase response characteristics of the measured physical link in a specific overfrequency band, providing reliable digital parameters for subsequent inversion calculations of the equivalent composite impedance and the quantitative location of the system's physical poles.

[0044] In S203, the software analysis and control module invokes its internally configured impedance inversion algorithm. Utilizing the feedback amplitude and phase of the high-frequency perturbation signal, it calculates the total equivalent input impedance, comprised of the dynamic resistance of the device under test, the adapter contact resistance, and the cable parasitic capacitance. The signal generator within the admittance feature injection unit couples the high-frequency perturbation signal to the test link through a fixed-value internal reference resistor. This internal reference resistor, together with the external physical test link, forms a complex voltage divider network. Based on the principle of complex domain AC voltage dividers and Kirchhoff's voltage law, and considering that the graded adaptive preamplifier is in full bandwidth passband mode, the software analysis and control module performs inverse gain stripping on the detection results acquired by the multi-channel synchronous acquisition module and converts them to the physical input of the preamplifier.

[0045] Subsequently, the current conservation equation at the input node is established. Based on the equivalent circuit model, the software analysis and control module performs complex number operations, and the formula for calculating the total equivalent input impedance is as follows: ; in, The total equivalent composite input impedance is calculated; The internal reference resistance value of the admittance feature injection cell; The feedback amplitude of the high-frequency perturbation signal; The initial known excitation amplitude when the high-frequency perturbation signal occurs; This is the inherent voltage amplification factor of the first fixed-gain stage; This is the reference voltage amplification factor of the second-stage topology reconstruction stage in resistive feedback mode; It is a natural constant; The imaginary unit; The feedback phase of the high-frequency perturbation signal extracted in step S202; It is a minimal compensation constant.

[0046] The technical purpose of this total equivalent input impedance calculation formula is to restore the true complex voltage division ratio at the input of the test link by separating amplitude-phase conversion and hardware gain constant. A minimal compensation constant is introduced. As a denominator correction term, its value is based on the small voltage ratio corresponding to the quantization noise floor of the analog-to-digital converter. This term is used to prevent arithmetic overflow anomalies caused by the voltage division ratio approaching 1 when the test link is in an extremely high impedance open-circuit state, thus ensuring the system operation stability of the impedance inversion algorithm when any unloaded or extremely high impedance devices are connected.

[0047] Since the impedance characteristics in low-frequency physical environments typically exhibit a parallel RC effect, the total equivalent input impedance can be physically equivalent to a series branch of the dynamic resistance of the device under test and the contact resistance of the adapter, connected in parallel with the parasitic capacitance of the cable to form an admittance network. The software analysis and control module further calculates the complex reciprocal of the total equivalent input impedance to obtain the total admittance. By separating the real and imaginary parts of the total admittance, the independent physical parasitic parameters are accurately calculated. The physical parameter decomposition formulas are as follows: ; ; in, The equivalent series resistance is formed by the combination of the dynamic resistance of the device under test and the contact resistance of the adapter. To test the parasitic capacitance formed by the combined effect of the channel cable and the physical fixture; Mathematical operations that extract the real part of a complex number; Mathematical operations that extract the imaginary part of a complex number; Pi is a constant. The center frequency of the high-frequency perturbation sensing signal determined in step S201; This is a correction term for the minimum conductivity constant.

[0048] The technical purpose of the above physical parameter decomposition formula is to map macroscopic complex impedance to specific circuit parasitic element values. The equivalent series resistance objectively reflects the dynamic conduction characteristics of the device under test under the current DC bias and the contact loss of the physical fixture; while the parasitic capacitance quantifies the capacitive load effect introduced by long shielded cable transmission. An additional minimum conductance constant correction term is introduced. The technical consideration is that when the test link exhibits extremely capacitive operating conditions, the real part of the total admittance approaches zero, and this correction term can effectively prevent this. The risk of division-by-zero overflow in the calculations is mitigated to ensure the mathematical completeness of the physical parameter decomposition logic. The system evaluates the parasitic operating conditions under the current real physical connection state based on the quantized separation of the aforementioned multi-source impedance parameters, rather than solely relying on the ideal nominal values ​​provided in the device specifications. This high-precision impedance characteristic sensing result provides a complete data foundation and physical basis for subsequent quantification of system physical pole offsets and the implementation of controlled zero-point reconstruction at the hardware level.

[0049] In this embodiment, the system enters the dynamic correction phase of the physical link frequency response characteristics. The specific implementation process includes the following sub-steps: S301 uses the physical parasitic parameters separated from the total equivalent input impedance to quantify the physical pole offset caused by impedance mismatch in the first-stage fixed-gain stage. Based on network analysis theory at the operational amplifier input, the first-stage fixed-gain stage inherently possesses input resistance and capacitance. When the device under test (DUT) is connected to the test channel, the aforementioned separated equivalent series resistance and parasitic capacitance form a parallel coupling network with the amplifier's inherent input impedance. This parallel coupling network constitutes a typical first-order RC low-pass filter in the AC model, causing a pole on the target frequency axis that dynamically changes with external parasitic parameters to appear in the originally flat amplification path. To offset the high-frequency attenuation caused by this pole, the software analysis and control module needs to accurately calculate the actual physical pole frequency under the current physical conditions. The formula for the actual physical pole frequency is as follows: ; in, This refers to the actual physical pole frequency caused by impedance matching; The equivalent series resistance obtained from the decomposition in step S203; This is the inherent input resistance of the first fixed-gain stage; The parasitic capacitance formed by the test channel cable obtained in step S203 and the physical fixture; This is the inherent input capacitance of the first-stage fixed-gain stage; Pi is a constant. It is the minimum resistance compensation constant; This is the minimum capacitance compensation constant.

[0050] The technical purpose of the aforementioned formula for the actual physical pole frequency is to transform discrete parasitic element parameters into a quantitative description of frequency domain attenuation characteristics. This pole represents the turning point where the system's amplitude-frequency response begins to decrease at a slope of 20 dB per decade. To ensure consistency of physical dimensions and completeness of mathematical calculations, a minimal resistance compensation constant is used. The dimensionless constant is ohm squared. The unit of measurement is farad, and the values ​​of both are limited to the least significant bit threshold of the system's double-precision floating-point arithmetic precision (e.g., 10^-5). -12 The two compensation constants are based on the fact that when the test system is connected to extremely low impedance devices or faces an extremely low capacitive reactance wiring environment, the product term in the denominator may approach zero, thereby triggering an arithmetic overflow anomaly in the underlying divider. Introducing these constants ensures the completeness of the calculation.

[0051] For obtaining the inherent input resistance of the operational amplifier With inherent input capacitance The parameter extraction method can be found in the device datasheet or by using a conventional open-circuit AC impedance tester. The calibration process and data extraction logic are well-known technologies in the field and will not be described in detail here.

[0052] Furthermore, the software analysis and control module calculates the relative offset of the poles on the frequency axis based on the actual physical pole frequencies. As a preferred method, the system pre-stores the ideal physical pole frequencies of the reference channel under open-circuit no-load conditions. By comparing the frequency difference between the actual load condition and the ideal open-circuit condition, the system performs a quantitative evaluation of the physical pole offset. The formula for the physical pole offset is as follows: ; ; in, This is the physical pole offset of the first-stage fixed-gain stage due to impedance mismatch. This represents the ideal physical pole frequency of the system under open-circuit no-load conditions. The technical purpose of this physical pole offset formula is to provide a relative scale for measuring the degree of frequency response distortion of the system. By extracting the difference, the system can isolate dynamic influence variables purely introduced by external physical interfaces and the device under test from multi-dimensional frequency response data. The system incorporates multi-dimensional judgment logic based on thresholds when outputting this offset result. Specifically, the system does not rely solely on the transient extremum of a single frequency point, but rather combines the steady-state leakage current fluctuation rate under the current bias state with the calculated... The absolute values ​​were jointly analyzed.

[0053] when When the absolute value is less than a preset tolerance threshold (typically set to 5% to 10% of the highest cutoff frequency of the target measurement band), the system determines that the current parasitic effect is insufficient to cause significant distortion of the noise power spectrum within the target frequency band, thus suspending subsequent frequency compensation operations to avoid introducing redundant thermal noise. Conversely, when the offset exceeds the tolerance threshold, the system confirms the mismatch and uses this physical pole offset as a direct mathematical driving parameter for generating hardware switching action commands and zeros between the reconstruction stage. This determination mechanism avoids one-sided compensation relying solely on a single frequency extremum, improving the physical targeting of the adaptive reconstruction process.

[0054] S302, the software analysis and control module generates the target zero frequency based on the actual physical pole frequencies and executes the optimization mapping logic for the discrete passive component array using an internally preset hardware database. Based on the zero-pole cancellation principle in classical control theory, in order to cancel the additional low-pass poles caused by impedance mismatch in the first-stage fixed-gain stage in the complex frequency domain, the physical link needs to introduce a compensation zero that completely coincides with its frequency in the second-stage topology reconstruction stage. Since the passive component array configured inside the second-stage topology reconstruction stage consists of a finite number of discrete resistor and discrete capacitor branches, the software analysis and control module cannot generate infinitely continuous frequency values ​​and must instead find the optimal matching combination within the physical boundaries through an optimization algorithm. The discrete hardware optimization mapping calculation formula is as follows: ; ; in, To traverse to the th Zero-pole frequency matching error value for a certain discrete switch combination; For parameter variables; This refers to the actual physical pole frequency caused by impedance matching; The index number of the valid connection topology in the passive component array; For the first The equivalent resistance value of the feedback loop under a certain switch combination; For the first The equivalent capacitance value of the feedback loop under a certain switch combination; Pi is a constant. It is the minimum background capacitance compensation constant; The globally optimal switch combination index number that minimizes the matching error value; Mathematical operations representing the indexes of independent variables that minimize the objective function.

[0055] The technical purpose of the aforementioned discrete hardware optimization mapping calculation formula is to accurately quantify the theoretical zero-point frequency requirement in the continuous domain into the specific physical switching states of the underlying hardware array. A minimal background capacitance compensation constant is introduced into the denominator. The physical consideration is that when a certain switch combination contains only pure resistors and no physical capacitors are connected, The value is zero. This compensation constant effectively prevents arithmetic overflow errors caused by the denominator of division approaching zero. Its value is typically set between 1pF and 5pF to equivalently characterize the inherent parasitic capacitance of printed circuit board traces. The system outputs the globally optimal switch combination index number by traversing all physical connection combinations in the hardware database and based on the principle of minimizing the absolute value of the error.

[0056] S303, the software analysis and control module, converts the globally optimal switch combination index number into serial control commands and drives the controlled analog switch matrix to complete physical actions based on strict low-noise timing specifications. The system will then calculate... It is mapped to a multi-bit wide binary control word and encapsulated into a complete communication frame with additional start bits, parity bits, and stop bits.

[0057] As a preferred approach, to prevent transient high-frequency transitions of digital control signals from coupling to weak analog signal amplification links via spatial radiation or ground return, the software analysis and control module asynchronously sends control commands to the second-level topology reconstruction stage inside the electromagnetic shielding box via a digital isolation barrier constructed using optocouplers or magnetic isolation chips. For the specific selection of the digital isolation interface and the serial communication mechanism, those skilled in the art can use conventional embedded hardware communication architectures, which will not be elaborated upon here.

[0058] After receiving and verifying the serial instruction, the shift register inside the controlled analog switch matrix initiates the array reconfiguration process. To ensure tight time alignment and operational synchronization of the multi-source module control, the system utilizes a unified global hardware timer to precisely schedule the switching action sequence. To address the stringent requirements of measuring extremely low-frequency, weak noise, the system enforces a delayed switching timing control logic of disconnecting before turning on during hardware topology switching.

[0059] Specifically, the controlled analog switch matrix forcibly disconnects all currently closed passive component array branches using one system clock cycle, followed by a preset hardware dead time. This hardware dead time is used to release residual charge in the previously connected capacitors, preventing transient surge currents caused by short circuits between different branches. After the hardware dead time ends, the control logic closes the corresponding optimal resistor and capacitor branches based on the bit state of the binary control word. After the physical switch action is completely completed and the control level is latched, the software analysis and control module forces the measurement link into a silent waiting period. The duration of the silent waiting period is determined by the charging and discharging time constant determined by the integrated resistance and integrated capacitance after system reconstruction, typically five to seven times this time constant, to ensure that the amplifier bias current and node voltage fully recover to the new DC steady state, thus providing a clock-free, feedthrough-free physical environment for subsequent high-purity dual-path signal synchronous acquisition.

[0060] S304 constructs an equivalent circuit model of a variable zero-pole compensation network based on the closed state of the controlled analog switch matrix, and generates controlled zeros in the physical link to cancel parasitic low-pass poles. Based on feedback control theory and active filter principles, when the globally optimal switch combination is connected to the second-stage topology reconstruction stage, the passive network surrounding its internal operational amplifier changes from the initial pure resistive proportional voltage divider mode to a complex frequency-varying feedback mode. The variable zero-pole compensation network is topologically represented by a frequency-dependent impedance branch composed of the optimal equivalent resistance and optimal equivalent capacitance. This impedance branch alters the propagation path of the amplifier's closed-loop gain, causing the second-stage topology reconstruction stage to spontaneously generate an amplitude compensation response that increases with frequency in the complex frequency domain, mathematically corresponding to a controlled physical zero located in the left half-plane of the real axis. The formula for calculating the controlled zero frequency is as follows: ; in, This refers to the controlled zero frequency actually generated in the physical link by switching the array of passive components; Pi is a constant. The optimal equivalent resistance value connected to the feedback loop under the global optimal switch combination index number; The optimal equivalent capacitance value for the feedback loop under the globally optimal switch combination index number; It is the minimum background capacitance compensation constant.

[0061] The technical purpose of this controlled zero-point frequency calculation formula is to explicitly verify the actual physical characteristics after the underlying hardware reconstruction. By introducing a controlled zero, the system aims to make the controlled zero-point frequency... Within the allowable hardware discrete quantization error range, the actual physical pole frequency obtained by quantization in step S302 is approximated to the greatest extent possible. .

[0062] To quantitatively evaluate the effect of the controlled zero on the overall system frequency response correction, the software analysis and control module, combined with the attenuation characteristics of the first-stage fixed-gain stage, reconstructs the inter-stage synthetic transfer function under the current operating conditions. Under the equivalent state of neglecting high-frequency parasitic poles and assuming a sufficiently wide inherent bandwidth of the operational amplifier, the frequency domain distortion caused by external parasitic effects in the physical link can be corrected due to the phase lead and gain boost effect generated by the controlled zero. The reconstructed inter-stage synthetic transfer function formula is as follows: ; in, To complete the inter-stage synthesis transfer function composed of the first and second stages after hardware adaptive reconfiguration; For frequency variables; This is the inherent voltage amplification factor of the first fixed-gain stage; This is the reference voltage amplification factor of the second-stage topology reconstruction stage in resistive feedback mode; The imaginary unit; This refers to the controlled zero frequency actually generated in the physical link by switching the array of passive components; This refers to the actual physical pole frequency caused by impedance matching; It is the minimum damping correction factor.

[0063] The technical objective of this reconstructed interstage synthetic transfer function formula is to establish a mathematical mapping relationship that describes the overall dynamic frequency response compensation. The imaginary term in the numerator characterizes the differential compensation effect brought about by the controlled zeros, while the imaginary term in the denominator characterizes the integral hysteresis effect introduced by the parasitic parameters of the physical interface. An additional minimal damping correction factor is introduced. The technical consideration is that when the operating frequency Extremely close to or equivalent to the frequency of actual physical poles Furthermore, when the system is under extremely high impedance or specific resonant conditions, the complex modulus of the denominator may approach zero. Minimal damping correction factor. Defined as a dimensionless constant, its value range is usually limited to 10. -6 Up to 10 -4 Between these points, the correction term can effectively prevent arithmetic division by zero overflow of the transfer function at singular points, ensuring the absolute convergence and numerical computation stability of subsequent algorithms when calling the transfer function to perform frequency domain operations.

[0064] Based on the above equivalent circuit principle and zero-pole cancellation mechanism, the system physically cancels the bandwidth compression caused by the impedance variation of the external device under test, and pushes the weak low-frequency noise signal under test to the subsequent dual-path signal synchronous acquisition stage without amplitude and phase distortion. From the root of hardware signal conditioning, it ensures the high fidelity and wide bandwidth adaptability of the background noise spectrum extraction.

[0065] After completing the hardware adaptive reconstruction and resting physical environment, the system switches to a digital mapping process for dual-path simulation features. In this embodiment, the specific implementation process includes the following sub-steps: S401 clarifies the physical sources of the mixed signal in the test channel and the leakage interference signal in the reference channel under the dual-path architecture, and constructs an isolation mechanism for their transmission. The signal input of the test channel is physically directly connected to the device under test (DUT). The analog signal it carries originates from the intrinsic low-frequency noise generated by the random fluctuations of charge carriers within the DUT. It is also inevitably superimposed with common-mode background noise introduced by the power supply network and electromagnetic interference introduced by external environmental radiation. These components together constitute the mixed signal of the test channel. The signal input of the reference channel maintains an impedance-matched open-circuit reference state, without any active noise sources connected. The analog signal it carries only contains common-mode background noise and spatial electromagnetic interference from the same physical environment, i.e., the leakage interference signal of the reference channel.

[0066] As a preferred approach, to avoid spatial crosstalk between high-amplitude mixed signals and weak leakage interference signals, the dual-path device adapter strictly adheres to symmetrical physical wiring rules. Both the test and reference channels use independent low-noise coaxial cables with PTFE as the dielectric layer for signal guidance, and the physical wiring spacing within the electromagnetic shielding box is forcibly set to be more than five times the cable's outer diameter. This physical isolation mechanism cuts off the parasitic capacitive coupling path between channels at the root of the spatial electromagnetic field distribution, ensuring the absolute independence of the two signals in terms of their physical origin and a high degree of homogeneity with the components of the external interference environment.

[0067] The S402, driving the multi-channel synchronous acquisition module, executes synchronized triggering logic for strict time-domain alignment of two analog signals at the hardware level based on a unified clock distribution network. Due to the physical mechanism of coherent detection of weak signals across multiple channels, any tiny sampling time deviation between channels will be converted into a phase error that increases linearly with frequency in the frequency domain, leading to the complete failure of subsequent common-mode noise stripping algorithms. To ensure absolute alignment of multi-source data, the multi-channel synchronous acquisition module abandons the software polling triggering mechanism with uncertain delays and instead adopts a pure hardware global synchronization architecture. The software analysis and control module configures the underlying global trigger control word to activate a high-precision oven-controlled crystal oscillator. The reference clock signal output by this crystal oscillator is synchronously fanned out to the independent analog-to-digital conversion cores of the test and reference channels with picosecond-level time skew accuracy via an internal clock distribution network of equal length and impedance matching. The time deviation constraint formula for hardware synchronization alignment between channels is as follows: ; in, This refers to the overall hardware synchronization time deviation between the test channel and the reference channel; To test the absolute physical time at which the analog-to-digital converter kernel receives the edge of the hardware-triggered clock; The reference channel analog-to-digital conversion kernel receives the absolute physical time at the edge of the hardware-triggered clock. Allocate clock edge jitter time to the clock network due to thermal noise; The highest cutoff frequency of the target measurement band; This is the phase tolerance coefficient.

[0068] The technical purpose of this time deviation constraint formula is to quantitatively constrain the timing allocation accuracy of the underlying hardware using explicit mathematical limits. (Phase tolerance coefficient) Defined as a dimensionless real factor, its value is typically strictly limited to the range of 100 to 360. This parameter is determined to force the inter-channel phase measurement error at the highest frequency point to be within 1 to 3.6 degrees, thereby ensuring that the time-domain physical states of the two signals maintain a high degree of synchronization and phase-locking even under the worst high-frequency boundary conditions, providing a fundamental timing guarantee for coherent cancellation in the frequency domain. It should be noted that the highest cutoff frequency of the target measurement band... The denominator of the constraint formula is always a real number that is greater than zero in terms of physical properties, and the system has set an effective low-pass bandwidth lower limit during initial configuration. Therefore, there is no arithmetic risk of division by zero overflow in the underlying operation.

[0069] S403 performs the high-resolution analog-to-digital conversion process and establishes an efficient reading mechanism for the digital sequence based on direct memory access and hardware buffer streams. Based on the Nyquist sampling theorem and the anti-aliasing filtering requirements for broadband white noise, the multi-channel synchronous acquisition module is internally configured with two sets of high-resolution oversampling analog-to-digital converters with strictly symmetrical architectures. In this embodiment, the analog front-end circuit of the multi-channel synchronous acquisition module is equipped with a hardware-based low-pass anti-aliasing filter to filter out high-frequency out-of-band noise above the Nyquist frequency before analog-to-digital conversion. The low-pass anti-aliasing filter has an inherent complex transfer function.

[0070] After the analog front-end low-pass anti-aliasing filter removes out-of-band high-frequency spurious components, the two analog signals are synchronously discretized by their respective independent conversion kernels at a rate much higher than the highest cutoff frequency. The formula for the dual-path synchronous observation matrix of the discrete data output by the multi-channel synchronous acquisition module is as follows: ; in, This is a dual-path synchronous observation matrix generated by the multi-channel synchronous acquisition module within a single data reading cycle. For the test channel The instantaneous digital voltage amplitude corresponding to each discrete sampling point; For reference channel number The instantaneous digital voltage amplitude corresponding to each discrete sampling point; The total number of discrete sampling points set within a single reading cycle; This is the index number of the sampling point in the discrete sequence, and its value ranges from 1 to... An increasing positive integer.

[0071] The technical purpose of this dual-path synchronous observation matrix formula is to normalize continuous physical simulation parameters into discrete, structured data suitable for batch invocation and parallel computation by the underlying computer architecture. In this matrix model, two data elements within the same matrix row represent dual-path conditions captured at the same absolute physical moment, directly solidifying the time alignment attribute of the data from a mathematical perspective. Here, the total number of discrete sampling points... The choice of directly determines the minimum frequency resolution for subsequent spectral analysis, and its value is usually set to 2. 16 Up to 2 24 The integer power of the real number not only fits the underlying optimization logic of the Fast Fourier Transform algorithm based on radix-2 time decimation, but also ensures the complete capture of extremely low frequency noise features over a long integration time.

[0072] To prevent singularity anomalies caused by matrix full-rank corruption when subsequent algorithms call the synchronous observation matrix to perform autocorrelation or inversion operations, the system continuously monitors the Pearson correlation coefficient of the two discrete vectors. Once detected... Sequence and When the correlation of the sequence approaches 1 (which usually indicates severe crosstalk or pin-level shorting between physical channels), the system will immediately suspend direct memory access transfers and throw a hardware isolation failure alarm, thereby ensuring the effective physical independence of the acquired data.

[0073] After confirming data validity, to prevent CPU congestion and data overflow losses caused by high-speed continuous data streams, the system deeply integrates direct memory access technology into the discrete digital sequence reading mechanism. For the specific interaction with the underlying hardware, the sequence generated by analog-to-digital conversion is first pushed into the module's internal first-in-first-out (FIFO) data buffer queue. The software analysis and control module deploys multi-dimensional burst transmission judgment logic: the system monitors the hardware buffer queue's half-full interrupt flag in parallel, and whether the currently accumulated data length has fully covered the row count requirement of the dual-path synchronous observation matrix. Only when all the above data preparation states meet the design requirements will the system pull down the chip select signal and trigger the block movement operation of the direct memory access controller, so as to completely map the dual-path synchronous observation matrix to the pre-allocated memory area of ​​the host computer, thereby providing a high-throughput, low-latency, high-quality underlying data source for subsequent dynamic modeling operations of common-mode noise leakage transfer function.

[0074] Based on the successful acquisition and lossless mapping of the dual-path synchronous observation matrix to the pre-allocated memory region of the host computer, the system formally enters the algorithm stripping and data cleaning stage for common-mode background interference. In this embodiment, the specific implementation process includes the following sub-steps: In step S501, the software analysis and control module defines a physical model of the common-mode noise leakage transfer function based on the electromagnetic field coupling mechanism of the dual-path physical architecture, and establishes the core mathematical mapping relationship between this transfer function and the total equivalent input impedance of the test channel. Based on the theory of weak signal anti-interference, the alternating electromagnetic field radiation of the external environment and the weak ground loop current generated by the low-noise power supply can be physically equivalent to an equivalent common-mode displacement current source acting simultaneously on the test channel and the reference channel. Since the spatial symmetry and geometric consistency of the two physical transmission paths have been constrained at the hardware routing level in step S401, the common-mode displacement current injected into the nodes of the two channels maintains a high degree of homogeneity and equivalence in both the time and frequency domains.

[0075] To construct an accurate frequency domain compensation reference and avoid overcompensation or undercompensation distortion caused by directly subtracting the two signals in the time domain, the software analysis and control module must reconstruct the frequency-varying impedance boundary under the current operating conditions based on the actual physical pole characteristics. The formulas for calculating the frequency-varying network impedance of the test node and the reference node are as follows: ; ; in, The integrated input impedance of the physical nodes of the test channel varies with the target frequency; The integrated input impedance of the physical node of the reference channel varies with the target frequency; For frequency variables; and These are the equivalent series resistance and parasitic capacitance, respectively. and These are the inherent input resistance and inherent input capacitance of the first fixed-gain stage, respectively; The reference channel's background parasitic capacitance in the open-circuit state; The imaginary unit; Pi is a constant.

[0076] The technical purpose of the aforementioned frequency-varying network impedance calculation formula is to extend the static parasitic parameters in the low-frequency band to a dynamic complex impedance spectrum covering the entire measurement frequency band. This formula integrates the inherent parameters of the hardware amplifier with the real-time connection characteristics of the device under test, truly reflecting the voltage division characteristics of the measurement node under the AC small-signal model. Based on the impedance voltage division law and the principle of displacement current conservation, the software analysis and control module further derives the physical prior model of the common-mode noise leakage transfer function under theoretical conditions. The physical prior transfer function formula is as follows: ; in, This is a physical prior model of the common-mode noise leakage transfer function derived from the circuit physical topology. It is the minimum constant for impedance singularity compensation.

[0077] The technical significance of this physical a priori transfer function formula lies in its explicit quantification of the mathematical proportion and phase deflection relationship between the leakage of the pure background interference signal captured by the reference channel to the weak signal domain of the test channel. Essentially, This represents the differential-mode voltage mapping coefficient generated by spatially co-originating electromagnetic interference in two physical links with different boundary impedance characteristics.

[0078] As a preferred method, in order to prevent damage under extremely high frequency or specific external short-circuit conditions, The complex modulus decays drastically, even approaching zero, causing arithmetic overflow in the underlying complex divider. Therefore, an impedance singularity compensation minimum constant is forcibly introduced into the denominator of the formula. The physical dimension of this constant is ohms, and its value is strictly limited to 10⁻⁶. -6 Up to 10 -5 Within the real number range, the extremely small volume resistance of the copper layer on the printed circuit board is equivalently characterized to ensure the absolute convergence of the transfer function in the full frequency domain.

[0079] After establishing the mathematical relationship between the transfer function and the total equivalent input impedance, the system is provided with a solid physical causal constraint for subsequent dynamic pure digital model operations. This physical prior model not only serves as the initial convergence anchor point for subsequent data-driven adaptive filtering algorithms, but also as the core physical boundary basis for multi-dimensional judgments, effectively preventing traditional pure statistical signal stripping algorithms from easily falling into local optima or erroneous correlation fitting when faced with strong shot noise masking from devices.

[0080] The S502 software analysis and control module performs a windowed discrete Fourier transform on the dual-path synchronous observation matrix and calculates the pure data-driven transfer function of the leakage signal from the reference channel to the test channel based on cross-power spectrum estimation theory. Based on frequency domain statistical algorithms in random weak signal processing theory, since the intrinsic low-frequency noise generated by semiconductor devices manifests as irregular thermal fluctuations or shot pulses in the time domain, directly extracting common-mode interference features in the time domain is easily masked by the device's own high-energy-band white noise. To accurately isolate co-source interference components with definite phase relationships across the entire measurement frequency band, the system must map the time series to the frequency domain to examine the energy distribution and correlation of the two signals at different frequency bands.

[0081] As a preferred approach, the system pre-applies a Blackman-Harris sidelobe suppression window to the discrete sequences in the dual-path synchronous observation matrix to prevent spectral energy leakage caused by aperiodic truncation. Subsequently, the system uses a Fast Fourier Transform algorithm to convert the time-domain data into a frequency-domain complex sequence, and employs an improved Welch average periodogram method to calculate the power spectral density at each frequency point. The formulas for calculating the power spectral density and the pure data-driven transfer function are as follows: ; ; ; in, For the reference channel signal in frequency variable The self-power spectral density at the location; For the reference channel and test channel signals in frequency variation Cross-power spectral density at; This represents the total number of overlapping data blocks in the Welch periodogram method. For reference channel number Data blocks in frequency variables Complex spectral values ​​at; For parameter variables; This is the complex conjugate of the spectrum value of the complex number. For the test channel number Data blocks in frequency variables Complex spectral values ​​at; The transfer function is driven by common-mode noise leakage data calculated purely from real-time acquired data. It is the minimum threshold constant for the power spectral density.

[0082] The technical purpose of the above calculation formula is to suppress independent random background noise with zero mean in two signals by utilizing autocorrelation and cross-correlation operations in the complex frequency domain, thereby quantifying the amplitude and phase characteristics of common-mode interference hidden in a complex background. A minimum threshold constant for power spectral density is introduced. The underlying engineering consideration is that when the target operating environment reaches an extremely high level of electromagnetic shielding, such that the reference channel does not capture any effective interference energy in a specific high-frequency band, The calculated value will approach floating-point zero. This constant It is strictly set to 1.5 times the equivalent power of the quantization noise floor of the analog-to-digital conversion system. As a denominator compensation term, it can forcibly avoid arithmetic anomalies caused by the division by zero operation of the underlying divider, and ensure the mathematical integrity of the data-driven algorithm under extremely pure working conditions.

[0083] S503, combining the inherent physical characteristics of the system with real-time statistical data, constructs a composite frequency domain leakage weight based on adaptive weighting of the coherence coefficient. Considering the complexity of actual test environments, if strong random telegraph noise suddenly occurs within the test channel or a single electrostatic discharge event is encountered, the data-driven transfer function... The amplitude and phase estimation will suffer from severe distortion and abrupt changes. To avoid the one-sided judgment relying on a single statistical extreme value, the system introduces a multi-dimensional fusion mechanism, which integrates the physical prior model derived in step S501. As a safety anchor, the correlation between the two frequency domain signals is calculated, and the two sets of transfer functions—physical prior and data-driven—are dynamically weighted and fused. The formula for calculating the composite frequency domain leakage weight is as follows: ; ; in, For frequency variables The squared coherence coefficient at the location; To test the channel signal in frequency variation The self-power spectral density at the location; To ultimately determine the composite frequency domain leakage weights used for common-mode noise stripping.

[0084] The technical purpose of this composite frequency domain leakage weight calculation formula is to establish a highly robust dynamic error prevention boundary. The denominator of the formula reuses the minimum threshold constant again. This ensures that the correlation coefficient calculation safely converges to zero when there is no significant signal energy in either channel. (Square coherence coefficient) It is a dimensionless real factor whose theoretical value range is strictly closed within the interval [0, 1]. This coefficient characterizes the proportion of energy in the test channel spectral components that can be explained by the reference channel spectral components through a linear system. The physical causality of the system performing weighted judgment based on this parameter is as follows: when When the value approaches 1, it indicates that the test channel data in the current frequency band is dominated by strong external common-mode interference. At this time, the system assigns a data-driven transfer function. Extremely high trust weights are used to accurately track real-time dynamic variations in the environmental electromagnetic field; conversely, when When the value approaches 0, it indicates that the test channel is filled with weak intrinsic noise of the device or has encountered sudden non-common-mode abnormal interference. At this time, the system adaptively and smoothly transitions to a fully reliable physical prior model. It forces the scaling constraints to be executed based on the objective voltage division law of the underlying hardware parasitic impedance.

[0085] The S504 software analysis and control module, based on a complex weighted model, performs coherent subtraction operations block-by-block in the frequency domain to reconstruct the pure intrinsic noise sequence of the device under test. Based on the principle of frequency domain superposition of linear systems, the mixed signal spectrum captured by the test channel is mathematically and physically equivalent to the linear sum of the device's intrinsic noise spectrum and the external common-mode leakage spectrum. Since the composite frequency domain leakage weight has been rigorously mapped to a complex frequency domain variable containing precise amplitude attenuation and phase deflection information, the system can use this weight to perform vector modulation on the complex spectrum of the reference channel, thereby synthesizing an equivalent common-mode interference floor mode injected into the test channel. The system recovers the true physical fluctuation information of the device by stripping this synthesized floor mode from the total spectrum of the test channel. The formula for frequency domain coherent subtraction spectrum reconstruction is as follows: ; ; in, The first after common-mode interference stripping Data blocks in frequency variables The complex spectrum of pure intrinsic noise at that location; For parameter variables; After common-mode interference stripping is completed in the digital domain, the target frequency point The test channel's digital domain pure power spectral density; The total number of overlapping data blocks as defined above.

[0086] The technical purpose of this frequency-domain coherent subtraction spectral reconstruction formula is to completely decouple the weak intrinsic physical characteristics of the device under test from strong electromagnetic background interference. The core physical basis for forcibly using complex subtraction instead of scalar amplitude subtraction in the formula is that when spatial common-mode noise enters the dual-path measurement node through parasitic parameter coupling, phase hysteresis of varying degrees inevitably occurs due to the asymmetry of the impedance boundary. Performing only amplitude cancellation will cause constructive interference of residual noise at specific frequencies, leading to spectral artifacts and energy backflow. By performing coherent subtraction in the fully complex domain, including both real and imaginary parts, the system strictly compensates for phase deviation while canceling the amplitude of the common-source interference.

[0087] As a preferred method, in order to ensure the reconstructed power spectral density Statistical confidence intervals and smoothness, total number of overlapping data blocks It is typically set to a positive integer not less than 64 and not greater than 512. This range satisfies the statistical lower limit requirement for random signal variance compression, preventing spectral spikes caused by single burst pulses, while also avoiding low-frequency distortions due to excessive averaging. The characteristic slope is distorted by excessive smoothing. This occurs because the formula only involves multiplication, subtraction, and operations with positive integers. The mean operation for a constant denominator completely avoids the risk of division overflow from the underlying algorithm logic.

[0088] The S505 software analysis and control module outputs a clean power spectral density sequence in the digital domain and pre-establishes a multi-dimensional frequency domain fitting logic and physical parameter extraction framework. Since the signal is still constrained by the underlying hardware's system frequency response, the system does not directly perform the final parameter calculation. Instead, it establishes a hybrid physical noise regression analysis model in a full-band logarithmic coordinate system. To comprehensively cover the complex microscopic carrier fluctuation phenomena within semiconductor devices, the system constructs the following target mapping formula: ; in, The equivalent intrinsic power spectral density of the target physical end to be fitted; The flicker noise figure is used to characterize the surface state defect density of a device. A frequency index characterizing the distribution of defect energy levels; and The first The amplitude coefficient and characteristic corner frequency of generation-composite noise (gr noise) induced by a deep level trap; This represents the total number of independent trap energy levels detected inside the device. This is to characterize the white noise background level of the channel hot carriers. This pre-defined framework paves the way for the subsequent accurate extraction of comprehensive quantitative indicators reflecting various underlying lattice defects of the device after eliminating external environmental interference.

[0089] The system acquires the target signal of the test channel after eliminating external electromagnetic radiation and environmental substrate interference. However, this signal is still at the output node of the analog-to-digital converter in a physical dimension, and its amplitude and phase characteristics are superimposed with the physical amplification link gain, hardware parasitic filtering effects, and system response deviations introduced by the anti-aliasing digital filter. To obtain the absolute intrinsic parameters that truly reflect the physical fluctuations of charge carriers inside the device under test, the system enters the full-link inverse gain normalization and data solidification stage. In this embodiment, the specific implementation process includes the following sub-steps: The S601 software analysis and control module, combining real-time hardware parameters of the variable zero-pole compensation network with front-end interference stripping results, reconstructs the end-to-end integrated transfer function covering the entire test physical node to the digital conversion end. Based on the theory of linear time-invariant systems, the dynamic response of complex test links to weak broadband random signals can be equivalently mapped by complex multiplication of the transfer functions of each independent cascaded submodule. Since the inter-stage integrated transfer function, including microscopic parasitic effects, has been adaptively reconstructed to address impedance boundary abrupt changes caused by the dynamic connection of the device under test, the system needs to cascade and fuse this dynamic function with the static analog anti-aliasing filter and the transfer response of the analog-to-digital conversion stage at the back end. The formula for reconstructing the end-to-end integrated transfer function is as follows: ; in, A comprehensive transfer function covering the entire link from the physical acquisition end of weak signals to the digital sequence output end; For frequency variables; To complete the inter-stage synthesis transfer function composed of the first and second stages after hardware adaptive reconfiguration; To simulate the inherent complex transfer function of the front-end low-pass anti-aliasing filter; This is the equivalent discretized voltage gain constant of the analog-to-digital converter kernel.

[0090] The technical purpose of this end-to-end integrated transfer function reconstruction formula is to integrate the amplification factors and phase-frequency distortion characteristics scattered across various cascaded nodes in the analog hardware link into a single mathematical mapping scale. This is achieved through the fusion of dynamic... Compared to static system base parameters, this model can track in real time the overall system bandwidth variation caused by each component replacement or operating condition drift. This is useful for obtaining the inherent complex transfer function of the anti-aliasing filter. and analog-to-digital conversion gain The specific parameters can be calibrated to factory standards using a high-precision network analyzer and stored in the system's non-volatile memory by those skilled in the art. The extraction logic is a well-known technology in the field and will not be elaborated here.

[0091] S602, based on the reconstructed end-to-end integrated transfer function, performs gain normalization compensation on the processed frequency domain power spectral density data. Based on the principle of random signal analysis, when a stationary random physical process traverses a linear system, its output power spectral density is equal to the input power spectral density multiplied by the square of the complex modulus of the system transfer function. To inversely invert the calculated power spectral density from the analog-to-digital converter's perspective to the absolute noise power spectrum equivalent to the physical pins of the device under test, the system must perform point-by-point division compensation in the frequency domain. The gain normalization compensation formula is as follows: ; in, The equivalent intrinsic power spectral density at the input terminal after full-link gain normalization compensation is equivalent to the physical input terminal of the device under test. The test channel digital domain pure power spectral density obtained in step S504; This is the end-to-end integrated transfer function; This is the minimum constant for compensating for the null trap of the transfer function.

[0092] The technical meaning of the above gain normalization compensation formula is that it eliminates the measurement interference of the test system's own hardware characteristics on weak noise signals from the mathematical and physical root, and restores the dimensions of the measured signal to the true physical fluctuation amplitude (such as mean square volts per hertz).

[0093] Considering the complex modulus of the overall transfer function of the entire link in the extreme high-frequency cutoff region or near a specific resonant frequency, The filter's steep descent characteristic may cause drastic attenuation, even approaching floating-point zero. To completely eliminate the arithmetic risk of overflow in the underlying division operation, a minimum constant for transfer function zero-trap compensation is forcibly introduced into the denominator of the formula. The value of this constant is usually strictly limited to 10. -12 Up to 10 -10 Within the dimensionless range, its numerical value is determined by the smallest resolvable precision of the underlying double-precision floating-point number, ensuring the absolute robustness of the broadband compensation algorithm across the entire frequency band.

[0094] In step S603, the system performs a validity check on the normalized data based on multi-dimensional judgment logic. Then, it calls the physical parameter extraction framework preset in step S505 to calculate the core characterization parameters and maps the power spectral density to voltage spectral density for structured storage and visualization output. To avoid invalid data contaminating the test database due to single transient surges or local divergence in the compensation algorithm, the system introduces multi-dimensional feature constraint judgment logic before data is written to disk.

[0095] Specifically, the system extracts synchronously. The system determines that the current compensation sequence has complete physical interpretability and data validity if and only if the low-frequency flicker noise intensity does not exceed three standard deviations of the upper limit of the statistical benchmark for normal devices in the same batch, and the deviation of the high-frequency white noise asymptotic variance from the theoretical thermal noise floor is less than a preset 15% threshold.

[0096] As a preferred approach, and to directly meet the noise level testing requirements of semiconductor industry standards, the system... Perform point-by-point square root calculation to generate the equivalent noise voltage spectral density sequence at the input (its dimensions are...). After confirming the data's validity, the software analysis and control module calls the underlying file input / output interface to serialize the voltage spectral density sequence into a hierarchical data format. During the data encapsulation process, the system establishes a condition alignment mechanism for multi-source heterogeneous data. The generated structured data file not only encapsulates the core frequency and noise amplitude vector matrices but also deeply couples, at the metadata level, all dimensions of hardware physical state parameters, such as device bias voltage, bias current, ambient temperature at the test moment, and the optimal switching combination index of controlled zeros and poles locked in step S302.

[0097] Based on this structured data file, the system maps the final results to a double logarithmic coordinate system in the host computer's graphical user interface. By rendering smooth, continuous spectral lines, it visually presents the effects of microscopic lattice defects in the device. The output and storage mechanism ensures absolute traceability in the spatiotemporal dimensions of any weak noise extraction experiment from the data source, providing a high-quality, standardized digital support foundation for subsequent wafer-level yield monitoring and reliability degradation modeling of semiconductor process platforms.

[0098] I. Specific Application Examples: Measurement background and initialization: Device under test: A wafer-level NMOS test structure fabricated using a 28nm logic process, connected to a dual-path device adapter via a probe station.

[0099] Operating condition setup: The software control system issues a digital bias word to set the gate-source voltage V. gs =0.8V, drain-source voltage V ds =1.2V. The system monitored that the variance of leakage current fluctuation was less than 0.01% for 5 consecutive seconds, confirming that the device has entered the thermal equilibrium and saturation operating region. The hierarchical adaptive preamplifier is locked into full bandwidth passband state.

[0100] Impedance feature sensing and physical reconstruction: High-frequency excitation: The highest frequency of the target measurement is 100kHz. The system selects a frequency band isolation coefficient k=20 and injects a 2MHz high-frequency perturbation sinusoidal signal into the test link.

[0101] Parameter separation: By separating the real and imaginary parts of the admittance through orthogonal detection, the system quantitatively calculates that the equivalent series resistance formed by the current probe contact and the device channel is 150Ω, and the parasitic capacitance of the coaxial cable is 120pF.

[0102] Pole cancellation: Considering the amplifier's inherent input capacitance of 20pF, the system calculates that the actual physical pole frequency shifts by approximately [value missing]. In the second-stage topology reconstruction stage, the system optimization logic closes the corresponding optimal RC switch combination to generate an equivalent controlled zero frequency, which is then forcibly canceled out with the actual physical pole frequency, thus smoothing the frequency response of the front-end physical link.

[0103] Common-mode stripping and intrinsic noise reconstruction: Synchronous acquisition: The multi-channel acquisition module performs strict time-aligned sampling on the test channel (including device noise and environmental interference) and the reference channel (including environmental interference only) at an oversampling rate of 1MHz.

[0104] Coherent subtraction: The system calculates the composite frequency domain leakage weight. In the laboratory environment, there is a 50Hz power frequency and its higher harmonics (150Hz, 250Hz), as well as a 45kHz spike interference radiated from a nearby switching power supply. In the pure digital domain, the system uses a complex subtraction algorithm to eliminate these highly spatially correlated common-mode spikes, outputting a clean digital domain power spectral density.

[0105] Gain normalization and parameter fixation: Inverted physical quantities: The system imports the end-to-end integrated transfer function and performs division compensation in the frequency domain to eliminate the slight phase frequency distortion of the underlying analog-to-digital converter and filter. Subsequently, a square root operation is performed to convert the dimensions to the true input equivalent noise voltage spectral density. ).

[0106] Parameter extraction: By calling the multi-dimensional physical noise fitting model, the system successfully extracted: The flicker noise slope index is 1.02 (indicating perfect performance). feature).

[0107] A distinct generation-composite (gr) noise Lorentz bulge plateau was captured at 8 kHz.

[0108] In the 50kHz to 100kHz frequency band, 12 were accurately fitted. The theoretical thermal noise background level.

[0109] II. Experimental Verification and Effect Comparison To highlight the beneficial effects of the present invention, the following comparative experiment was designed: Control group (traditional measurement method): A traditional single-channel preamplifier was used with fixed hardware gain, adaptive impedance matching was not enabled, and common-mode leakage stripping was not performed.

[0110] Experimental group (method of the present invention): The dynamic compensation and dual-path coherent subtraction mechanism of the present invention are fully activated.

[0111] like Figure 3As shown in the figure, the horizontal axis represents frequency (Hz), and the vertical axis represents noise voltage spectral density (V / Hz). 1 / 2 In the figure, the thin solid line represents the spectrum curve extracted using the traditional uncompensated measurement method, the thick solid line represents the spectrum curve extracted using the adaptive measurement method of this invention, and the dotted-dash line represents the extracted independent and composite GR noise features.

[0112] Combination Figure 3 The waveform characteristics show that in the low-frequency range (e.g., 50Hz and its harmonic frequencies), the thin solid line spectrum extracted by the traditional method exhibits obvious power frequency interference spikes with amplitudes as high as 10. -5 The magnitude of the noise severely masks the true low-frequency noise signal of the device under test. In contrast, the thick solid line extracted by the method of this invention shows a smooth downward trend in this frequency band, and the peaks of 50Hz and related higher harmonics (150Hz, 250Hz) are completely smoothed out. This comparative phenomenon intuitively demonstrates the effectiveness and high fidelity of the common-mode coherent stripping mechanism in strong electromagnetic interference environments.

[0113] Further observation of the mid-frequency range reveals that traditional methods fail to effectively suppress environmental white noise and random spikes, resulting in chaotic broadband fluctuations in the thin solid line region, making it impossible to identify deep-level defect features within the device. However, the method of this invention, through multi-dimensional data cleaning, clearly reveals the Lorentz bulge plateau characteristic of gr noise near the 8kHz frequency of the thick solid line (the trajectory of this plateau highly coincides with the dotted line in the figure). The successful capture of this feature verifies the high-resolution capability of this invention in characterizing microscopic lattice defects.

[0114] In the high-frequency range (above 20kHz), the thin solid line of the traditional method exhibits significant high-frequency roll-off distortion due to the low-pass filtering effect of the parasitic capacitance of the test system, deviating from the true physical background. In stark contrast, the thick solid line of this invention maintains a flat horizontal distribution across a wide frequency band up to 100kHz, accurately fitting approximately 12 The theoretical thermal noise background is obtained. This result fully confirms that hardware adaptive zero-point reconstruction combined with transfer function normalization compensation successfully eliminates parasitic attenuation of the physical link, ensuring the absolute dimension inversion of weak noise signals across the entire measurement frequency band.

[0115] The above multi-dimensional comparison of graph features not only logically confirms the original design intent of the system architecture, but also directly corresponds to the improvement of the following core performance indicators in terms of physical results: The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A multi-type device adapted semiconductor low frequency noise measurement system, characterized by, It includes a hardware measurement subsystem and a software analysis subsystem; The hardware measurement subsystem includes: A low-noise power supply and bias module is used to connect to the device under test (DUT), provide the DUT with operating voltage and DC bias voltage, and superimpose a high-frequency perturbation sensing signal onto the measurement link; A dual-path device adapter is provided with a symmetrical test channel and a reference channel. The test channel is connected to the device under test and extracts the mixed signal, while the reference channel extracts the common-mode leakage signal. A multi-channel synchronous acquisition module is used to synchronously receive analog noise signals from the test channel and the reference channel and convert them into digital sequences; A graded adaptive preamplifier is used to connect the device under test (DUT) and the multi-channel synchronous acquisition module to amplify the input signal and receive external control commands to adjust the frequency response characteristics of the hardware physical link. The software analysis subsystem includes a software analysis and control module, which establishes a communication connection with the hardware measurement subsystem. The software analysis and control module is used to receive the digital sequence and perform equivalent impedance calculation, transfer function reconstruction and coherence cancellation operation, and output the equivalent noise voltage spectral density sequence of the input terminal of the device under test.

2. The semiconductor low-frequency noise measurement system adaptable to multiple types of devices according to claim 1, characterized in that, The low-noise power supply and bias module integrates an admittance feature injection unit. The hierarchical adaptive preamplifier includes a first fixed-gain stage and a second topology reconstruction stage connected in series; The first fixed-gain stage uses a fixed-parameter topology to perform primary amplification of the input signal; The second-level topology reconfiguration stage is internally equipped with a controlled analog switch matrix and a passive component array, which are used to switch the parameters of the connected passive component array to adjust the frequency response characteristics.

3. The semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 2, characterized in that, The admittance feature injection unit is used to output a continuous sine wave of fixed frequency as the high-frequency perturbation sensing signal, and superimpose it onto the circuit of the DC bias voltage. The multi-channel synchronous acquisition module digitizes the amplified response voltage signal to generate a digital response sequence. The software analysis and control module performs orthogonal synchronous detection on the digital response sequence, extracts the feedback amplitude and feedback phase of the high-frequency perturbation sensing signal, and calls the impedance inversion algorithm to calculate the total equivalent input impedance using the feedback amplitude and feedback phase. The equivalent series resistance and parasitic capacitance are calculated by separating the real and imaginary parts of the total admittance.

4. The semiconductor low-frequency noise measurement system adaptable to multiple types of devices according to claim 3, characterized in that, The software analysis and control module uses the calculated equivalent series resistance and parasitic capacitance to quantify the actual physical pole frequency of the first fixed gain stage caused by impedance mismatch. The software analysis and control module generates the target zero frequency based on the actual physical pole frequency, and executes the optimization mapping logic of the discrete passive component array in conjunction with the internal preset hardware database, and outputs the global optimal switch combination index number. The controlled analog switch matrix receives serial control commands and generates controlled physical zeros in the feedback loop of the second-level topology reconstruction stage according to the global optimal switch combination index number, thereby reconstructing the inter-stage integrated transfer function.

5. A semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 4, characterized in that, When the controlled analog switch matrix performs physical actions, it is forced to adopt a delayed switching timing control logic of disconnecting before turning on. The delay switching timing control logic for disconnecting before connecting is configured with a preset hardware dead time. After the physical switch action is fully completed and the control level is latched, the measurement link is forced into a silent waiting period.

6. A semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 4, characterized in that, The calculation formula for the interstage synthetic transfer function introduces a minimum damping correction factor into the denominator. This minimum damping correction factor is used to prevent the transfer function from overflowing during arithmetic division by zero at singular points.

7. A semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 1, characterized in that, The multi-channel synchronous acquisition module, based on a global trigger control word, executes synchronous trigger logic on the test channel and the reference channel under the condition of satisfying the time deviation constraint of hardware synchronization alignment between channels, and generates a dual-path synchronous observation matrix with strict time domain alignment. The dual-path synchronous observation matrix is ​​fully mapped to the pre-allocated memory area of ​​the host computer through direct memory access technology, via first-in-first-out data cache queue triggered block movement.

8. A semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 7, characterized in that, The software analysis and control module reconstructs the frequency-varying impedance boundary based on the actual physical pole characteristics and derives the physical prior model of the common-mode noise leakage transfer function. The software analysis and control module performs a windowed discrete Fourier transform on the dual-path synchronous observation matrix, calculates the power spectral density using the Welch average periodogram method, and solves for the common-mode noise leakage data-driven transfer function.

9. A semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 8, characterized in that, The software analysis and control module calculates the squared coherence coefficient of the frequency domain signal, and uses the squared coherence coefficient to dynamically weight and fuse the physical prior model and the data-driven transfer function to generate a composite frequency domain leakage weight. Based on the composite frequency domain leakage weight, a coherent subtraction operation involving both real and imaginary parts is performed on each data block in the frequency domain to output the pure power spectral density in the digital domain.

10. A semiconductor low-frequency noise measurement system adaptable to multiple device types according to claim 4, characterized in that, The software analysis and control module cascades and fuses the interstage integrated transfer function of the hierarchical adaptive preamplifier, the inherent complex transfer function of the low-pass anti-aliasing filter, and the equivalent discretized voltage gain constant of the analog-to-digital converter kernel to reconstruct the full-link integrated transfer function. Combining the full-link integrated transfer function, a point-by-point division compensation operation is performed in the frequency domain to inversely transform the digital domain pure power spectral density into an equivalent intrinsic power spectral density at the input terminal of the physical pin of the device under test. Then, a point-by-point square root operation is performed on the equivalent intrinsic power spectral density at the input terminal to generate the equivalent noise voltage spectral density sequence at the input terminal.

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