Chip defect processing method, device, equipment and readable storage medium
By assigning logical identifiers to the chip's computing core and establishing mapping relationships, the problem of inconsistent logical addresses caused by chip manufacturing defects was solved, resulting in a significant improvement in chip yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SIENGINE TECH CO LTD
- Filing Date
- 2026-06-03
- Publication Date
- 2026-07-03
AI Technical Summary
In existing technologies, chip manufacturing defects cause inconsistent external logic addresses for chips with malfunctioning computing cores in different locations, thus limiting the improvement of chip yield.
By assigning logical identifiers to multiple computing cores and establishing a mapping relationship between physical identifiers and logical identifiers, the physical identifiers of computing cores with manufacturing defects are mapped to preset logical identifiers, and the computing cores corresponding to those logical identifiers are disabled, thereby achieving a unified logical view.
It achieves a unified logical view from the perspective of system software, significantly improving chip yield from 30% to 65%, a yield increase of 35%, which is 31 times higher than traditional methods.
Smart Images
Figure CN122332192A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a chip defect processing method, apparatus, device, and readable storage medium. Background Technology
[0002] With the continuous development of semiconductor technology, chip integration is becoming increasingly higher, especially in ultra-large-scale AI computing chips, which integrate a large number of computing cores. However, during the chip manufacturing process, manufacturing defects often cause the core computing functions of the chip to fail.
[0003] In traditional technical solutions, for chips with manufacturing defects, the usual method is to disable the failed computational cores to ensure chip functionality. However, traditional methods cannot achieve functional consistency across chips with failed computational cores in different locations by disabling the failed cores. For example, if chip A's first computational core fails, disabling the first core; if chip B's fifth computational core fails, disabling the fifth core, this results in inconsistent external logical addresses between the different chips. Because a unified logical view from the system software perspective cannot be achieved, some defective chips that can be repaired by disabling failed computational cores may be discarded due to software compatibility issues, resulting in limited improvement in chip yield. Summary of the Invention
[0004] This invention provides a chip defect handling method, apparatus, device, and readable storage medium to solve the technical problem that after processing chips using existing traditional chip defect handling methods, the logic addresses of chips with core failures calculated at different locations are inconsistent, which limits the improvement of chip yield.
[0005] Firstly, a chip defect handling method is provided, applicable to chips comprising multiple computing cores, comprising the following steps: Obtain the physical identifiers of multiple computing cores and assign logical identifiers to them; Identify the physical identifier of the computing core with manufacturing defects; A mapping relationship between physical identifiers and logical identifiers is established. Based on the mapping relationship, the physical identifiers of computing cores with manufacturing defects are mapped to preset logical identifiers, and the physical identifiers of computing cores without manufacturing defects are mapped to other logical identifiers besides the preset logical identifiers; wherein, the preset logical identifiers remain fixed. Disable the computing core corresponding to the preset logical identifier.
[0006] In some embodiments, multiple computing cores are distributed in a multi-level structure, which includes a first level, a second level, and a third level; the first level includes multiple computing groups, the second level includes multiple computing partitions under each computing group, and the third level includes multiple computing cores under each partition. The step of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to the multiple computing cores includes: The physical identifier includes the physical index of the computing core in the first level, the second level, and the third level; The logical identifier includes the logical index of the computing core in the first level, the second level, and the third level.
[0007] In some embodiments, mapping the physical identifier of a computing core with manufacturing defects to a preset logical identifier according to the mapping relationship includes: The preset logical identifier is the logical identifier corresponding to the last logical index position of each of the first, second, and third levels.
[0008] In some embodiments, mapping the physical identifier of a manufacturing-defect-free computing core to a logical identifier other than a preset logical identifier includes: The physical identifiers of the computing cores without manufacturing defects are mapped sequentially and non-repeatedly to other logical identifiers besides the preset logical identifiers in a preset order.
[0009] In some embodiments, disabling the computing core corresponding to the preset logical identifier includes: Turn off the clock signal of the computing core corresponding to the preset logic identifier; And / or, cut off the power supply to the computing core corresponding to the preset logic identifier; And / or, block instructions sent to the computing core corresponding to a preset logical identifier.
[0010] In some embodiments, multiple computing cores are distributed in a single-level structure. The step of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to them includes: The physical identifier includes the physical index of the computing core at a single level; The logical identifier includes the logical index of the computing core in a single level.
[0011] In some embodiments, multiple computing cores are distributed in a two-tier structure, the two-tier structure including a first tier and a second tier; the first tier includes multiple computing partitions, and the second tier includes multiple computing cores under each partition; obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to the multiple computing cores includes: The physical identifier includes the physical index of the computing core in the first level and the second level; The logical identifier includes the logical index of the computing core in the first level and the second level.
[0012] Secondly, a chip defect processing apparatus is provided, comprising: The acquisition unit is used to acquire the physical identifiers of multiple computing cores and assign logical identifiers to the multiple computing cores. The determination unit is used to identify the physical identifier of a computing core that has a manufacturing defect; A mapping unit is used to establish a mapping relationship between physical identifiers and logical identifiers. Based on the mapping relationship, the physical identifier of a computing core with manufacturing defects is mapped to a preset logical identifier, and the physical identifier of a computing core without manufacturing defects is mapped to other logical identifiers besides the preset logical identifiers; wherein, the preset logical identifiers remain fixed. The disable unit is used to disable the computing core corresponding to a preset logical identifier.
[0013] Thirdly, a computer device is provided, comprising: a memory and a processor, wherein the memory stores at least one instruction, the at least one instruction being loaded and executed by the processor to implement the aforementioned chip defect handling method.
[0014] Fourthly, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, which, when executed by a computer, cause the computer to perform the aforementioned chip defect handling method.
[0015] The beneficial effects of the technical solution provided by this invention include: This invention provides a chip defect handling method, apparatus, device, and readable storage medium. The chip defect handling method maps physical identifiers of different physical defect locations to the same preset logical identifier. From the system software perspective, all defective chips uniformly view the computational cores of logical identifiers other than the preset logical identifier as defect-free computational cores. That is, chips with failed computational cores at different locations have the same external logical address, achieving a unified logical view from the system software perspective and significantly improving chip yield. Practical applications show that when the initial chip yield is 30%, using traditional chip defect handling methods can improve the yield to 31.1%, an increase of 1.1%; while using the chip defect handling method of this invention, the chip yield can be improved to 65%, an increase of 35%, and the percentage improvement is 31 times that of the traditional method. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A flowchart of a chip defect handling method provided in an embodiment of the present invention; Figure 2 Implementation provided for the embodiments of the present invention Figure 1 A schematic diagram of step S300; Figure 3 Implementation provided for the embodiments of the present invention Figure 1 Another schematic diagram of step S300; Figure 4 This is a schematic diagram of a chip defect processing device provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] This invention provides a chip defect handling method that can solve the technical problem that after processing chips using existing traditional chip defect handling methods, the logic addresses of chips with core failures at different locations are inconsistent, which limits the improvement of chip yield.
[0020] like Figure 1 As shown, this embodiment of the invention provides a chip defect handling method, which can be applied to very large-scale chips, especially AI computing chips. The method includes the following steps: Step S100: Obtain the physical identifiers of multiple computing cores and assign logical identifiers to the multiple computing cores. Specifically, in this embodiment of the invention, the chip includes multiple computing cores. Each computing core has a unique physical identifier (Physical ID, or PID) at the hardware physical layer, which is usually determined by the hardware connection address. Simultaneously, to provide a unified view at the system software layer, a logical identifier (Logical ID, or LID) is assigned to each computing core.
[0021] Step S200: Determine the physical identifier of the computing core with manufacturing defects. After chip manufacturing is completed, the chip is tested using testing equipment to determine which computing cores have manufacturing defects. Assuming the physical identifier of the computing core with manufacturing defects is PID*, this defect information can be stored in the chip's internal memory, such as non-volatile memory.
[0022] Step S300: Establish a mapping relationship between physical identifiers and logical identifiers. Based on the mapping relationship, map the physical identifier of the computing core with manufacturing defects to a preset logical identifier, and map the physical identifier of the computing core without manufacturing defects to other logical identifiers besides the preset logical identifiers; wherein, the preset logical identifiers remain fixed.
[0023] Specifically, in this embodiment of the invention, regardless of the physical location of the physical identifier of a computing core with manufacturing defects, it is mapped to the same preset logical identifier. Preferably, the preset logical identifier can be the last logical identifier in the logical address space. For computing cores without manufacturing defects, they are mapped sequentially and non-repeatingly to other logical identifiers besides the preset logical identifier according to a preset order. This mapping method achieves the function of different physical identifiers but the same logical identifier, so even if computing cores with manufacturing defects in different chips are located in different positions, they will ultimately be mapped to the same logical identifier.
[0024] Step S400: Disable the computing core corresponding to the preset logical identifier. Since the defective computing core has been mapped to the preset logical identifier, disabling the computing core corresponding to the preset logical identifier effectively shields the defective computing core.
[0025] Specifically, the disabling method may include: turning off the clock signal of the computing core corresponding to the preset logical identifier; and / or cutting off the power supply to the computing core corresponding to the preset logical identifier; and / or blocking the instructions sent to the computing core corresponding to the preset logical identifier.
[0026] The chip defect handling method in this embodiment of the invention maps physical identifiers of different physical defect locations to the same preset logical identifier. From the perspective of the system software, all defective chips uniformly see that the computational cores of the logical identifiers other than the preset logical identifier are defect-free computational cores. That is, the external logical addresses of chips with failed computational cores at different locations are consistent, achieving a unified logical view from the perspective of the system software and significantly improving chip yield. Practical application shows that when the initial chip yield is 30%, the chip yield can be improved to 31.1% after using the traditional chip defect handling method, which is a 1.1% improvement; while after using the chip defect handling method in this embodiment of the invention, the chip yield can be improved to 65%, which is a 35% improvement, and the percentage improvement in chip yield is 31 times that of the traditional method.
[0027] In an optional embodiment, multiple computing cores are distributed in a multi-level structure, the multi-level structure including a first level, a second level, and a third level; the first level includes multiple computing groups, the second level includes multiple computing partitions under each computing group, and the third level includes multiple computing cores under each partition; the step of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to the multiple computing cores includes: The physical identifier includes the physical index of the computing core in the first level, the second level, and the third level; The logical identifier includes the logical index of the computing core in the first level, the second level, and the third level.
[0028] For example, suppose the chip has L * N * M There are 10 computing cores, which are divided into 3 levels. The first level has 100 computing cores. L There are computation groups, and each computation group in the second level has... N There are computing partitions, and each computing partition in the third level has... M One computing core.
[0029] The physical identifier includes the physical index of the computing core in the first level, the second level, and the third level, denoted as PID( l , n , m ),in, l Take 0~ L -1, n Take 0~ N -1, m Take 0~ M-1. The logical identifier includes the logical index of the computing core in the first level, the second level, and the third level, denoted as LID( l , n , m ).
[0030] The preset logical identifier is the logical identifier corresponding to the last logical index position of each of the first, second, and third levels. Assume PID*( l *, n *, m The computational core of *) has physical manufacturing defects. The rules for mapping it to preset logical identifiers are as follows: Map the physical index of the computing core with manufacturing defects to a logical index at the first level. L -1, maps the physical index of the computing core with manufacturing defects to a logical index at the second level. N -1, mapping the physical index of the computational core with manufacturing defects to a logical index at the third level. M -1, which is also the core PID for defect calculation*( l *, n *, m *) maps to LID*( L -1, N -1, M -1).
[0031] The physical identifiers of manufacturing-defect-free computing cores are mapped sequentially and non-repeatingly to logical identifiers other than the preset logical identifiers, according to a preset order. For example, healthy physical cores are sequentially filled into logical addresses (0, 0, 0) to (…) in hierarchical order. L -1, N -1, M At position -2), disable the logical identifier LID* ( L -1, N -1, M -1) is the core of the computation, so that all chips can uniformly see, from the system software perspective, except for LID*( L -1, N -1, M The computational cores corresponding to logical identifiers other than -1) are all defect-free computational cores, which can maintain the consistency of computational cores as seen from the perspective of system software.
[0032] Assuming the chip has 32 computing cores: 2 computing clusters, that is... L =2; Each compute cluster has 4 compute partitions, i.e. N=4; Each computing partition has 4 computing core slices, that is M =4. For example... Figure 2 As shown, assuming that the first-level cluster0, second-level partition2, and third-level slice1 (i.e., physically identified as (0, 2, 1)) of the first chip have manufacturing defects, the first-level cluster0 is mapped to the first-level cluster1 of the logic view, the second-level partition2 is mapped to the second-level partition3 of the logic view, and the third-level slice1 is mapped to the third-level slice3 of the logic view (i.e., the preset logical identifier is (1, 3, 3)).
[0033] like Figure 3 As shown, assuming that the first-level cluster0, the second-level partition1, and the third-level slice2 of the second chip have manufacturing defects from the physical perspective, they are also mapped to the first-level cluster1, the second-level partition3, and the third-level slice3 from the logical perspective. That is, the physical identifier of the defect is (0, 1, 2), which is also mapped to the preset logical identifier (1, 3, 3).
[0034] Let's assume the chip has 32 computing cores: 2 computing clusters, that is... L =2; Each compute cluster has 4 compute partitions, i.e. N =4; Each computing partition has 4 computing core slices, that is M =4. As shown in Table 1 below, the chip's registers store the physical identifiers (0, 2, 1) of the failed computing core slices. According to the test results of the automated test equipment ATE, the physical locations of the failed computing core slices may be different for different chips. When the chip is running, it will read these physical identifier information and map the physical identifiers of each computing core slice according to the following rules.
[0035] The logical identifier of a failed computing core is fixed as LID(cluster1, partition3, slice3), and it is mapped according to the following rules: The first step is to map the computing group containing the failed computing core to cluster1; The second step is to map the computing partition where the failed computing core is located to partition3; The third step is to map the slice containing the failed computing core to (cluster 1, partition3, slice3). The fourth step involves mapping the physical identifiers of the remaining unfailed computing cores to the remaining logical identifiers in a sequential and non-repeating manner. All physical identifiers from (cluster0, partition0, slice0) to (cluster1, partition3, slice2) are then mapped.
[0036] Table 1
[0037] In an optional embodiment, the multiple computing cores are distributed in a single-level structure. The step of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to them includes: The physical identifier includes the physical index of the computing core at a single level; The logical identifier includes the logical index of the computing core in a single level.
[0038] The mapping rule also applies to mapping the physical identifier of a defect to a fixed preset logical identifier (such as the last logical index), and disabling the computing core corresponding to that preset logical identifier.
[0039] In an optional embodiment, multiple computing cores are distributed in a two-tier structure, the two-tier structure including a first tier and a second tier; the first tier includes multiple computing partitions, and the second tier includes multiple computing cores under each partition; the step of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to the multiple computing cores includes: The physical identifier includes the physical index of the computing core in the first level and the second level; The logical identifier includes the logical index of the computing core in the first level and the second level.
[0040] The mapping rules also follow the principle of mapping the physical identifier of a defect to a fixed, preset logical identifier.
[0041] like Figure 4 As shown, this embodiment of the invention also provides a chip defect processing device, including: an acquisition unit, a determination unit, a mapping unit, and a disabling unit.
[0042] The acquisition unit is used to acquire the physical identifiers of multiple computing cores and assign logical identifiers to the multiple computing cores.
[0043] The determining unit is used to determine the physical identifier of a computing core that has a manufacturing defect.
[0044] The mapping unit is used to establish a mapping relationship between physical identifiers and logical identifiers. According to the mapping relationship, the physical identifier of the computing core with manufacturing defects is mapped to a preset logical identifier, and the physical identifier of the computing core without manufacturing defects is mapped to other logical identifiers besides the preset logical identifier; wherein, the preset logical identifier remains fixed.
[0045] The disabling unit is used to disable the computing core corresponding to the preset logical identifier.
[0046] This invention also provides a computer device, including: a memory, a processor, and a network interface connected via a system bus, wherein the memory stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement all or part of the steps of the aforementioned chip defect handling method.
[0047] The network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0048] A processor can be a CPU, or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor, or any conventional processor. The processor is the control center of a computer device, connecting all parts of the computer device through various interfaces and lines.
[0049] Memory can be used to store computer programs and / or modules. The processor implements various functions of the computer device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory can mainly include a program storage area and a data storage area. The program storage area can store the operating system, application programs required for at least one function (such as video playback, image playback, etc.), etc.; the data storage area can store data created using the memory (such as video data, image data, etc.). Furthermore, memory can include high-speed random access memory, and can also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital (SD) cards, flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.
[0050] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements all or part of the steps of the aforementioned chip defect handling method.
[0051] The embodiments of the present invention can implement all or part of the aforementioned processes, or they can be accomplished by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various methods described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.
[0052] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, servers, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.
[0053] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.
[0054] The serial numbers in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0055] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0056] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.
Claims
1. A chip defect handling method applied to a chip comprising a plurality of computing cores, characterized in that, Includes the following steps: Obtain the physical identifiers of multiple computing cores and assign logical identifiers to them; Identify the physical identifier of the computing core with manufacturing defects; A mapping relationship between physical identifiers and logical identifiers is established. Based on the mapping relationship, the physical identifiers of computing cores with manufacturing defects are mapped to preset logical identifiers, and the physical identifiers of computing cores without manufacturing defects are mapped to other logical identifiers besides the preset logical identifiers; wherein, the preset logical identifiers remain fixed. Disable the computing core corresponding to the preset logical identifier.
2. The chip defect handling method of claim 1, wherein Multiple computing cores are distributed in a multi-level structure, which includes a first level, a second level, and a third level. The first level includes multiple computing groups, the second level includes multiple computing partitions under each computing group, and the third level includes multiple computing cores under each partition. The process of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to them includes: The physical identifier includes the physical index of the computing core in the first level, the second level, and the third level; The logical identifier includes the logical index of the computing core in the first level, the second level, and the third level.
3. The chip defect handling method according to claim 2, characterized in that, The step of mapping the physical identifier of a computing core with manufacturing defects to a preset logical identifier according to the mapping relationship includes: The preset logical identifier is the logical identifier corresponding to the last logical index position of each of the first, second, and third levels.
4. The chip defect handling method according to claim 3, characterized in that, The mapping of the physical identifier of the manufacturing-defect-free computing core to a logical identifier other than a preset logical identifier includes: The physical identifiers of the computing cores without manufacturing defects are mapped sequentially and non-repeatedly to other logical identifiers besides the preset logical identifiers in a preset order.
5. The chip defect handling method according to claim 1, characterized in that, The computational core corresponding to the disabled preset logical identifier includes: Turn off the clock signal of the computing core corresponding to the preset logic identifier; And / or, cut off the power supply to the computing core corresponding to the preset logic identifier; And / or, block instructions sent to the computing core corresponding to a preset logical identifier.
6. The chip defect handling method according to claim 1, characterized in that, Multiple computing cores are distributed in a single-level structure. The process of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to them includes: The physical identifier includes the physical index of the computing core at a single level; The logical identifier includes the logical index of the computing core in a single level.
7. The chip defect handling method according to claim 1, characterized in that, Multiple computing cores are distributed in a two-tier structure, comprising a first tier and a second tier. The first tier includes multiple computing partitions, and the second tier includes multiple computing cores within each partition. The process of obtaining the physical identifiers of the multiple computing cores and assigning logical identifiers to them includes: The physical identifier includes the physical index of the computing core in the first level and the second level; The logical identifier includes the logical index of the computing core in the first level and the second level.
8. A chip defect processing device, characterized in that, include: The acquisition unit is used to acquire the physical identifiers of multiple computing cores and assign logical identifiers to the multiple computing cores. The determination unit is used to identify the physical identifier of a computing core that has a manufacturing defect; A mapping unit is used to establish a mapping relationship between physical identifiers and logical identifiers. Based on the mapping relationship, the physical identifier of a computing core with manufacturing defects is mapped to a preset logical identifier, and the physical identifier of a computing core without manufacturing defects is mapped to other logical identifiers besides the preset logical identifiers; wherein, the preset logical identifiers remain fixed. The disable unit is used to disable the computing core corresponding to a preset logical identifier.
9. A computer device, characterized in that, include: A memory and a processor, wherein the memory stores at least one instruction, which is loaded and executed by the processor to implement the chip defect handling method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions that, when executed by a computer, cause the computer to perform the chip defect handling method according to any one of claims 1 to 7.