Dma controller verification method

Abstract

A DMA controller verification method is disclosed, comprising: constructing a hierarchical coverage model of functional characteristics based on the functional characteristics of the DMA controller, wherein the hierarchical coverage model of functional characteristics includes multiple levels corresponding to different functional dimensions of the DMA controller, and each level includes one or more coverage points corresponding to one or more functional characteristics under the corresponding functional dimension; generating a functional characteristic cross-combination matrix based on the hierarchical coverage model of functional characteristics, wherein the functional characteristic cross-combination matrix of functional characteristics includes multiple cross-combinations of coverage points selected from at least two different levels of the hierarchical coverage model of functional characteristics, and each cross-combination represents a corresponding functional characteristic cross-combination of the DMA controller; and generating a coverage monitoring configuration based on the functional characteristic cross-combination matrix of functional characteristics for monitoring the number of hits of the functional characteristic cross-combinations represented by various cross-combinations in the functional characteristic cross-combination matrix in random tests of the DMA controller.

Description

Technical Field

[0001] This disclosure relates to the field of chip verification technology, and more specifically to a DMA controller verification method. Background Technology

[0002] Direct Memory Access (DMA) controllers are the core data transfer engine in a chip system, typically featuring the following characteristics: multiple DMA channels can perform data transfer simultaneously; support for various transfer modes such as unicast, broadcast, multicast, and proxy transfer; support for various address modes such as normal address, stride address, and dynamic address; and support for cross-access between Double Data Rate Synchronous Dynamic Random Access Memory (DDR), Local Buffer (LLB), and Global Buffer (GLB).

[0003] Traditional DMA controller verification methods typically employ the following approach: verifying each functional feature individually, writing targeted test cases for typical functional feature cross-combinations, and using random tests to cover the remaining functional feature cross-combinations. As the number of functional features in a DMA controller increases, the number of cross-combinations between these features grows exponentially. For example, 6 DMA channels × 4 transmission directions × 3 address modes × 3 broadcast modes × 2 performance modes = 432 cross-combinations. In this case, the above DMA controller verification method suffers from the following problems: 1) It is impossible to manually cover all functional feature cross-combinations; 2) Random testing cannot guarantee that typical functional feature cross-combinations are covered; 3) There is a lack of a systematic method for planning coverage of functional feature cross-combinations. Summary of the Invention

[0004] The DMA controller verification method according to embodiments of this disclosure includes: constructing a hierarchical coverage model of the DMA controller's functional characteristics based on the DMA controller's functional characteristics, wherein the hierarchical coverage model of the DMA controller's functional characteristics includes multiple levels corresponding to different functional dimensions of the DMA controller, and each level includes one or more coverage points corresponding to one or more functional characteristics under the corresponding functional dimension of the DMA controller; generating a cross-combination matrix of the DMA controller's functional characteristics based on the hierarchical coverage model of the DMA controller's functional characteristics, wherein the cross-combination matrix of the DMA controller's functional characteristics includes multiple cross-combinations of coverage points selected from at least two different levels of the hierarchical coverage model of the DMA controller's functional characteristics, each cross-combination representing a corresponding cross-combination of functional characteristics of the DMA controller, and any cross-combination of functional characteristics of the DMA controller refers to a combination scenario of functional characteristics under at least two different functional dimensions of the DMA controller; and generating a coverage monitoring configuration based on the cross-combination matrix of the DMA controller's functional characteristics, for monitoring the number of times each cross-combination of functional characteristics represented by each cross-combination in the cross-combination matrix of the DMA controller hits in random tests of the DMA controller, wherein hitting any cross-combination of functional characteristics represented by any cross-combination in the cross-combination matrix of the DMA controller means that the cross-combination of functional characteristics is covered at least once in random tests of the DMA controller. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, various aspects of this disclosure are best understood through the following detailed description. It should be noted that, in accordance with standard practice in the art, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0006] Figure 1 A schematic flowchart of a DMA controller verification method according to an embodiment of the present disclosure is shown.

[0007] Figure 2 A schematic block diagram of a computing device that can implement the DMA controller verification method according to embodiments of the present disclosure is shown. Detailed Implementation

[0008] Features and exemplary embodiments of various aspects of this disclosure will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this disclosure by illustrating examples. This disclosure is by no means limited to any specific configuration presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of this disclosure. Well-known structures and techniques are not shown in the accompanying drawings and the following description to avoid unnecessarily obscuring this disclosure.

[0009] Furthermore, the various operations will be described as multiple discrete operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must depend on the order. In particular, these operations do not need to be performed in the order presented.

[0010] The phrases “in an embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly throughout this document. These phrases do not typically refer to the same embodiment; however, they may refer to the same embodiment. Unless the context otherwise requires, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B), or (A and B).”

[0011] In view of one or more problems existing in conventional DMA controller verification methods, a DMA controller verification method according to embodiments of the present disclosure is provided, which can realize the systematic verification of DMA controller.

[0012] Figure 1 A schematic flowchart of a DMA controller verification method according to an embodiment of this disclosure is shown. Figure 1As shown, the DMA controller verification method 100 according to an embodiment of this disclosure includes: S102, constructing a hierarchical coverage model of the DMA controller's functional characteristics based on the DMA controller's functional characteristics, wherein the hierarchical coverage model of the DMA controller's functional characteristics includes multiple levels corresponding to different functional dimensions of the DMA controller, and each level includes one or more coverage points corresponding to one or more functional characteristics under the corresponding functional dimension of the DMA controller; S104, generating a cross-combination matrix of the DMA controller's functional characteristics based on the hierarchical coverage model of the DMA controller's functional characteristics, wherein the cross-combination matrix of the DMA controller's functional characteristics includes coverage points selected from at least two different levels of the hierarchical coverage model of the DMA controller's functional characteristics. Multiple cross combinations, each cross combination representing a corresponding functional characteristic cross combination of the DMA controller, any functional characteristic cross combination of the DMA controller refers to a combination scenario of functional characteristics under at least two different functional dimensions of the DMA controller; and S106, generating a coverage monitoring configuration based on the functional characteristic cross combination matrix of the DMA controller, used to monitor the number of times the various functional characteristic cross combinations represented by various cross combinations in the functional characteristic cross combination matrix of the DMA controller are hit in the random test of the DMA controller, wherein, the functional characteristic cross combination represented by any cross combination in the functional characteristic cross combination matrix of the DMA controller being hit means that the functional characteristic cross combination is covered at least once in the random test of the DMA controller.

[0013] In some embodiments, the DMA controller verification method 100 further includes, for any cross combination in the functional characteristic cross combination matrix of the DMA controller (hereinafter referred to as cross combination CROSS-GP for simplicity): setting a target hit count for the functional characteristic cross combination represented by cross combination CROSS-GP; counting the current hit count of the functional characteristic cross combination represented by cross combination CROSS-GP in real time; and increasing the random constraint weight associated with cross combination CROSS-GP when the current hit count of the functional characteristic cross combination represented by cross combination CROSS-GP is less than the target hit count, so as to increase the generation probability of the functional characteristic cross combination represented by cross combination CROSS-GP in subsequent random tests of the DMA controller.

[0014] In some embodiments, increasing the random constraint weights associated with the cross-combination CROSS-GP includes: determining the coverage gap of the functional cross-combination represented by the cross-combination CROSS-GP based on the target hit count and the current hit count; determining the weight adjustment coefficient associated with the cross-combination CROSS-GP based on the coverage gap of the functional cross-combination represented by the cross-combination CROSS-GP; and determining the random constraint weights associated with the cross-combination CROSS-GP based on the baseline weights and weight adjustment coefficients associated with the cross-combination CROSS-GP.

[0015] For example, assuming the target hit count T and current hit count C of the functional characteristic cross-combination represented by the cross-combination CROSS-GP, then the coverage gap R of the functional characteristic cross-combination represented by CROSS-GP is R = (TC) / T (that is, the coverage gap R of the functional characteristic cross-combination represented by CROSS-GP is the ratio of the difference (TC) between the target hit count T and the current hit count C of the functional characteristic cross-combination represented by CROSS-GP to the target hit count T of the functional characteristic cross-combination represented by CROSS-GP), the weight adjustment coefficient E associated with CROSS-GP is E = K + R (that is, the weight adjustment coefficient E associated with CROSS-GP is the sum of the preset constant K associated with CROSS-GP and the coverage gap R of the functional characteristic cross-combination represented by CROSS-GP, where the preset constant K takes a value greater than or equal to 1), and the random constraint weight W associated with CROSS-GP is W_ref × (K+R) (that is, the stochastic constraint weight W associated with the cross portfolio CROSS-GP is the product of the baseline weight W_ref associated with the cross portfolio CROSS-GP and the weight adjustment coefficient E = (K+R)).

[0016] In some embodiments, the DMA controller verification method 100 further includes the following for the cross-combination CROSS-GP in the cross-combination matrix of the DMA controller's functional characteristics: when the coverage gap of the cross-combination of functional characteristics represented by the cross-combination CROSS-GP exceeds a preset threshold, the functional characteristics corresponding to each coverage point included in the cross-combination CROSS-GP are analyzed, and targeted test cases for the cross-combination of functional characteristics represented by the cross-combination CROSS-GP are generated based on the analysis results. The generated targeted test cases are then added to the regression test set for subsequent random testing of the DMA controller. For example, when the coverage gap R of the cross-combination CROSS-GP exceeds a preset threshold of 0.5, the specific values ​​of each coverage point included in the cross-combination CROSS-GP are analyzed, such as "transmission direction = DDR2GLB, parallel quantity = 2, address mode = interleave". Based on the analysis results, a test case is generated that simultaneously starts two DDR2GLB channels with the source address in the interleaved address space. The generated test case is then saved as an independent file and added to the regression test set.

[0017] In some embodiments, the coverage monitoring configuration for monitoring the number of hits of various functional characteristic cross combinations represented by various cross combinations in the functional characteristic cross combination matrix of the DMA controller in random tests of the DMA controller can be implemented through SystemVerilog covergroup.

[0018] In some embodiments, the functional feature layering coverage model of the DMA controller includes one or more of the following layers: a transmission direction layer, including one or more coverage points corresponding to one or more transmission directions supported by the DMA controller; a parallel quantity layer, including one or more coverage points corresponding to different numbers of simultaneously active DMA channels in the DMA controller; an address mode layer, including one or more coverage points corresponding to one or more address modes supported by the DMA controller; a broadcast mode layer, including one or more coverage points corresponding to one or more broadcast modes supported by the DMA controller; and a performance mode layer, including one or more coverage points corresponding to one or more performance modes supported by the DMA controller.

[0019] In some embodiments, the DMA controller supports one or more of the following transfer directions: transfer direction from DDR to GLB (DDR2GLB), transfer direction from GLB to DDR (GLB2DDR), transfer direction from internal storage device (e.g., GLB, LLB, local memory, etc.) to external interface (SEND), transfer direction from external interface to internal storage device (e.g., GLB, LLB, local memory, etc.) (RCV), and transfer direction from core to core (i.e., data is directly transferred between different processing cores within the same chip without going through DDR, C2C).

[0020] In some embodiments, the DMA controller supports one or more address modes, including non-interleave mode and interleave mode.

[0021] In some embodiments, the DMA controller supports one or more of the following broadcast modes: no broadcast, row broadcast, and core broadcast. Here, no broadcast means that the DMA controller moves data from the source address to a single destination address without any copying or distribution; row broadcast means that the DMA controller simultaneously distributes a copy of data to all processing cores with the same row address in the processing core array within the target chip, where each processing core has uniquely determined (row address, column address) coordinates; core broadcast means that the DMA controller simultaneously distributes a copy of data to all cores or a specific set of cores on the target chip.

[0022] In some embodiments, the DMA controller supports one or more performance modes, including high-performance and low-performance modes. For example, the core characteristics of the high-performance mode of the DMA controller include low latency, high throughput, and preemptive behavior. Specific behaviors in this mode include: continuously occupying the bus or keeping the channel active after initiating a transfer request until the current transfer is completely completed; extremely high response time requirements for requests, disallowing idle cycles; DMA channel requests are typically set to high priority; and when multiple DMA channels request simultaneously, the high-performance channel can preempt the low-performance channel's bus usage. In high-performance mode, the DMA controller consumes more power, which may block other non-DMA bus devices. The core characteristics of the low-performance mode of the DMA controller include low power consumption, high latency tolerance, and time-sharing. Specific behaviors in this mode include: actively releasing the bus during transfers (e.g., inserting several idle cycles after each data transfer / burst length); allowing DMA responses to be temporarily suspended, yielding the bus to the Central Processing Unit (CPU) or other peripherals; and often cooperating with clock gating or power-off to enter a sleep state during non-transfer periods.

[0023] Table 1 below shows an example of a hierarchical overlay model for the functional characteristics of a DMA controller.

[0024] Table 1 In some embodiments, the process of generating the cross-combination matrix of the DMA controller's functional characteristics includes: selecting at least two levels of the DMA controller's hierarchical coverage model of functional characteristics according to a predefined priority list, and performing a Cartesian product operation on the coverage points of the selected levels to obtain a cross-combination list. For example, in the case of the hierarchical coverage model of functional characteristics shown in Table 1: for the cross-combination C1 (L1 × L2) of priority P0, the 5 coverage points of level L1 and the 6 coverage points of level L2 are subjected to a Cartesian product operation to generate 30 cross-combination points; similarly, for the cross-combination C7 (L1 × L2 × L3), 5 × 6 × 2 = 60 cross-combination points are generated; for the full-dimensional cross-combination of priority P2, 5 × 6 × 2 × 3 × 2 = 360 cross-combination points are generated. It should be noted that users can select which priority cross-combinations to enable through a configuration file.

[0025] In summary, in the DMA controller verification method 100 according to the embodiments of this disclosure, by constructing a functional feature hierarchical coverage model and generating a functional feature cross-combination matrix, it can be ensured that typical functional feature cross-combinations are not missed; by generating coverage monitoring configurations and targeted test cases, the amount of manual work required for the testing process can be reduced; by dynamically adjusting the random constraint weights associated with functional feature cross-combinations with low coverage, the hit rate of functional feature cross-combinations with low coverage in the random testing process of the DMA controller can be accelerated to converge; and when the functional features of the DMA controller increase, it is only necessary to expand the corresponding level of the functional feature hierarchical coverage model.

[0026] Figure 2 A schematic block diagram of a computing device that can implement the DMA controller verification method according to embodiments of the present disclosure is shown. Figure 2 As shown, computing device 200 may include bus 202 or other communication mechanism for transmitting information, and one or more hardware processors 204 coupled to bus 202 for processing information. The one or more hardware processors 204 may include, for example, one or more general-purpose microprocessors.

[0027] like Figure 2As shown, in some embodiments, computing device 200 may further include main memory 206 coupled to bus 202. Main memory 206 is used to store information and instructions executed by one or more processors 204, such as random access memory (RAM), cache, and / or other dynamic storage devices. Main memory 206 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by one or more processors 204. When these instructions are stored in storage media accessible to one or more processors 204, they can cause computing device 200 to become a dedicated machine customized to perform the operations specified in the instructions. Storage device 208 may include non-volatile and / or volatile storage media. Non-volatile storage media may include, for example, optical discs or magnetic disks. Volatile storage media may include dynamic memory. Common forms of storage media may include, for example, floppy disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, DRAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, or their networking versions.

[0028] like Figure 2 As shown, in some embodiments, computing device 200 may further include one or more communication interfaces or network interfaces 210 coupled to bus 202. Network interface 210 may provide bidirectional data communication coupling to one or more network links connected to one or more networks. As another example, network interface 210 may be a local area network (LAN) card to provide data communication connectivity to a LAN-compatible (or WAN component communicating with a WAN) network. Wireless links may also be implemented.

[0029] The execution of certain operations can be distributed across processors rather than residing within a single machine, but rather deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0030] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in code modules executed by one or more computer systems or computer processors including computer hardware, and may be fully or partially automated by these code modules. The processes and algorithms may be implemented, partially or fully, in dedicated circuit systems.

[0031] When the functions disclosed herein are implemented as software functional units and sold or used as stand-alone products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium and includes several instructions that cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this application. The storage medium may include a flash drive, portable hard disk drive, ROM, RAM, magnetic disk, optical disk, other media operable to store program code, or any combination thereof.

[0032] Specific embodiments further provide a system including a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor to cause the system to perform operations corresponding to steps in any method of the embodiments disclosed above. Specific embodiments further provide a non-transitory computer-readable storage medium storing instructions executable by one or more processors to cause the one or more processors to perform operations corresponding to steps in any method of the embodiments disclosed above.

[0033] The embodiments disclosed herein can be implemented via a cloud platform, server, or server cluster (collectively referred to below as the "Service System") that interacts with a client. The client can be a terminal device or a client registered by a user at the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can have the platform application installed.

[0034] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Additionally, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and their associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in an order other than that specifically disclosed, or multiple blocks or states may be combined into a single block or state. Example blocks or states may be executed sequentially, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The exemplary systems and components described herein may be configured differently than described. For example, components may be added to, removed from, or rearranged compared to the disclosed example embodiments.

[0035] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. The algorithm may be included in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). This algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly refer to the computer as performing the function but may learn from training data to generate a predictive model of the function.

[0036] The various operations of the exemplary methods described herein can be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute an engine of processor implementation that operates to perform one or more of the operations or functions described herein.

[0037] Similarly, the methods described herein may be implemented at least in part by a processor, wherein one or more specific processors are instances of hardware. For example, at least some operations of the methods may be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors may also be operable to support the execution of relevant operations in a “cloud computing” environment or as the execution of relevant operations in a “Software as a Service” (SaaS) context. For example, at least some operations may be performed by a group of computers (as an example of a machine containing processors), wherein these operations are accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0038] The execution of certain operations can be distributed across processors rather than residing within a single machine, and can be deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0039] Throughout this specification, multiple instances may be implemented as components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of these individual operations may be performed simultaneously, and not necessarily in the order illustrated. Structures and functions presented as separate components in the example configuration may be implemented as composite structures or components. Similarly, structures and functions presented as single components may be implemented as single components. These and other variations, modifications, additions, and improvements fall within the scope of this document.

[0040] As used herein, "or" is inclusive rather than exclusive unless explicitly indicated by the context. Therefore, in this document, "A, B, or C" means "A, B, A and B, A and C, B and C, or A, B, and C" unless explicitly indicated by the context. Furthermore, "and" is combined and separate unless explicitly indicated by the context. Therefore, in this document, "A and B" means "A and B, combined or separate" unless explicitly indicated by the context. Additionally, multiple instances of resources, operations, or structures described herein may be provided as a single instance. Furthermore, the boundaries between various resources, operations, engines, and data storage devices are somewhat arbitrary and specific operations are illustrated within the context of a particular illustrative configuration. Other functional assignments are foreseeable and fall within the scope of various embodiments of this disclosure. Generally, structures and functions presented as individual resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functions presented as single resources may be implemented as single resources. These and other changes, modifications, additions, and improvements fall within the scope of the embodiments of this disclosure as expressed in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

[0041] The terms “comprising” or “including” are used to indicate the presence of a subsequently claimed feature, but do not preclude the addition of other features. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “can,” “may,” and “can” is generally intended to convey that certain embodiments include certain features, components, and / or steps that are not included in other embodiments. Therefore, this conditional language is generally not intended to imply that one or more embodiments require features, components, and / or steps in any way, or that one or more embodiments must include logic for determining whether such features, components, and / or steps are included in or performed in any particular embodiment, with or without user input or prompts.

[0042] Although the general outline of the subject matter has been described with reference to specific exemplary embodiments, various modifications and changes may be made to these embodiments without departing from the broad scope of embodiments of this disclosure. Where more than one embodiment is disclosed, these embodiments of the subject matter may be referred to individually or collectively herein as the term "invention," this is for convenience only and is not intended to automatically limit the scope of this application to any single disclosure or concept.

[0043] The embodiments illustrated herein are described in detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, “implementation” is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and their full scope.

Claims

1. A method of DMA controller verification, the method comprising: include: Based on the functional characteristics of the DMA controller, a hierarchical coverage model of the functional characteristics of the DMA controller is constructed. The hierarchical coverage model of the functional characteristics includes multiple levels corresponding to different functional dimensions of the DMA controller. Each level includes one or more coverage points corresponding to one or more functional characteristics under the corresponding functional dimension of the DMA controller. Based on the functional characteristic hierarchical coverage model, a functional characteristic cross-combination matrix of the DMA controller is generated. This matrix includes multiple cross-combinations of coverage points selected from at least two different levels of the functional characteristic hierarchical coverage model. Each cross-combination represents a corresponding functional characteristic cross-combination of the DMA controller. Any functional characteristic cross-combination of the DMA controller refers to a combination scenario of functional characteristics under at least two different functional dimensions of the DMA controller. A coverage monitoring configuration is generated based on the functional characteristic cross-combination matrix to monitor the number of times each functional characteristic cross-combination represented by various cross-combinations in the functional characteristic cross-combination matrix is ​​hit in the random test of the DMA controller. A hit of any functional characteristic cross-combination represented by any cross-combination in the functional characteristic cross-combination matrix means that the functional characteristic cross-combination is covered at least once in the random test of the DMA controller.

2. The DMA controller verification method of claim 1, wherein, It also includes any cross combination in the cross combination matrix of the aforementioned functional characteristics: Set the target hit count for the functional characteristic cross-combination represented by the cross-combination; The current hit count of the functional characteristic cross combinations represented by the cross combinations is counted in real time. If the current hit count of the functional characteristic cross combination represented by the cross combination is less than the target hit count, the random constraint weight associated with the cross combination is increased to increase the generation probability of the functional characteristic cross combination represented by the cross combination in subsequent random tests of the DMA controller.

3. The DMA controller verification method of claim 2, wherein, Increasing the random constraint weights associated with the cross combination includes: Based on the target hit count and current hit count of the functional characteristic cross combination represented by the cross combination, determine the coverage gap of the functional characteristic cross combination represented by the cross combination; Based on the coverage gap of the functional characteristics represented by the cross-combination, determine the weight adjustment coefficient associated with the cross-combination; and Based on the baseline weights and weight adjustment coefficients associated with the cross combination, the random constraint weights associated with the cross combination are determined.

4. The DMA controller verification method of claim 3, wherein, Also includes: If the coverage gap of the functional feature cross combination represented by the cross combination exceeds a preset threshold, the functional features corresponding to each coverage point included in the cross combination are analyzed, and targeted test cases for the functional feature cross combination represented by the cross combination are generated based on the analysis results. The generated targeted test cases are added to the regression test set for subsequent random testing of the DMA controller.

5. The method of claim 3, wherein, The coverage gap of the functional characteristic cross combination represented by the cross combination is the ratio of the difference between the target hit count and the current hit count of the functional characteristic cross combination represented by the cross combination to the target hit count of the functional characteristic cross combination represented by the cross combination.

6. The method of claim 3, wherein, The weight adjustment coefficient associated with the cross combination is the sum of a preset constant associated with the cross combination and the coverage gap of the functional characteristic cross combination represented by the cross combination, and the random constraint weight associated with the cross combination is the product of the baseline weight associated with the cross combination and the weight adjustment coefficient.

7. The method of claim 1, wherein: The hierarchical coverage model for functional features includes one or more of the following levels: The transmission direction layer includes one or more coverage points corresponding to one or more transmission directions supported by the DMA controller. The parallel quantity layer includes one or more coverage points, each corresponding to a different number of simultaneously active DMA channels in the DMA controller. The address mode layer includes one or more overlays corresponding to one or more address modes supported by the DMA controller. The broadcast mode layer includes one or more overlays corresponding to one or more broadcast modes supported by the DMA controller. as well as The performance mode layer includes one or more overlays corresponding to one or more performance modes supported by the DMA controller.

8. The DMA controller verification method according to claim 7, characterized in that: The DMA controller supports one or more of the following transfer directions: transfer direction from DDR to GLB, transfer direction from GLB to DDR, transfer direction from internal storage device to external interface, transfer direction from external interface to internal storage device, and transfer direction from core to core. The DMA controller supports one or more of the following address modes: non-interleaved mode and interleaved mode; The DMA controller supports one or more of the following broadcast modes: no broadcast, line broadcast, and core broadcast; The DMA controller supports one or more of the following performance modes: high performance mode and low performance mode.

9. A computer-readable storage medium having stored thereon computer- executable instructions, wherein, When executed by a processor, the computer-executable instructions cause the processor to perform the DMA controller verification method according to any one of claims 1 to 8.

10. A computer program product, characterised in that, It includes computer-executable instructions that, when executed by a processor, cause the processor to perform the DMA controller verification method according to any one of claims 1 to 8.

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