A leaky channel controlled dual time constant adaptive neuron circuit
By designing a dual-time-constant adaptive neuron circuit with leakage path control, and utilizing a volatile threshold resistive memristor and an adaptive leakage path control circuit, the problem of the LIF model's difficulty in simulating adaptive mechanisms is solved. This achieves efficient simulation of neuron function and improves network performance, making it suitable for intelligent bionic systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHWEST UNIV
- Filing Date
- 2026-03-11
- Publication Date
- 2026-07-10
AI Technical Summary
Existing LIF neuron models struggle to simulate the adaptive mechanisms of biological neurons, limiting their application in simulating advanced neurodynamic behavior and brain-like computing. They also lack simple circuit schemes to achieve adaptive control of leakage pathways.
A dual-time-constant adaptive neuron circuit with leakage path control was designed. By utilizing a volatile threshold resistive memristor and an adaptive leakage path control circuit, and combining the leakage integral circuit and the adaptive leakage path control circuit, the dual-time-constant variation characteristics of the signal are realized, simulating the self-regulation characteristics of the neuron.
It achieves efficient simulation of neuron function, improves the adaptability of neurons and the performance of LSNN networks, can take into account both short-term and long-term adaptation needs, enhances the tunability and robustness of hardware, and is suitable for intelligent bionic systems.
Smart Images
Figure CN122366548A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of artificial intelligence and integrated circuit technology, and specifically to a dual-time-constant adaptive neuron circuit for leakage path control. Background Technology
[0002] As artificial intelligence continues to advance, traditional computing models based on the von Neumann architecture are gradually revealing their inherent bottlenecks. Due to the separation of computation and storage, this architecture inevitably leads to massive data transfers, resulting in severe "memory walls" and "power walls," which significantly restrict overall computational efficiency. Especially when performing neuromorphic tasks such as pattern recognition, associative memory, and autonomous learning, its performance still lags behind that of the biological brain by several orders of magnitude. In contrast, the human brain possesses highly parallelizable, event-driven, in-memory computing fusion, ultra-low power consumption (approximately 20 watts can support complex cognitive activities), and excellent fault tolerance and plasticity. These characteristics are expected to drive the development of next-generation computing systems and play a crucial role in cutting-edge fields such as edge intelligence, autonomous systems, intelligent sensing, and brain-computer interfaces.
[0003] In the current field of neuromorphic computing, the LIF (Leaky Integrate and Fire) neuron model is widely used due to its extremely simple structure. This model can effectively characterize the basic electrical properties of biological neurons, such as the integration and leakage processes of membrane potential. However, due to its relatively singular function, the LIF model struggles to reproduce the complex adaptive mechanisms in real neural systems. This limits its application in simulating higher-level neurodynamic behaviors, thus failing to fully reflect the dynamic regulatory capabilities of biological neural networks.
[0004] The dynamics of real neurons are far more complex. In the human frontal lobe, for example, over 30% of neurons exhibit adaptive behavior. Research has demonstrated that these neurons are crucial for enhancing neuromorphic computing capabilities, such as information processing and learning efficiency. To achieve adaptive neuron design, corresponding automatic control circuits are needed to constrain the pulse firing frequency. For example, this can be achieved by adaptively suppressing input current through leakage pathways to simulate the self-regulating characteristics of biological neurons. Nevertheless, a simple circuit scheme is currently lacking, which remains a key bottleneck for the further development of neuromorphic computing. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a dual-time-constant adaptive neuron circuit for leakage path control.
[0006] The first aspect of the present invention provides a dual-time-constant adaptive neuron circuit for leakage path control, including a leakage integration circuit and an adaptive leakage path control circuit; The leakage integration circuit is used to accumulate the input signal. When the accumulated input signal reaches the preset emission threshold, it outputs a voltage pulse to the adaptive leakage path control circuit. The adaptive leakage path control circuit is used to drive the control voltage to change according to the voltage pulse output by the leakage integrator circuit, and to adjust the leakage current of the leakage integrator circuit by the change of the control voltage.
[0007] Furthermore, the leakage integration circuit includes a volatile threshold resistive memristor, a film capacitor, a pulse readout resistor, a current-limiting resistor, and an adaptive leakage transistor; wherein one end of the volatile threshold resistive memristor is connected to the current-limiting resistor, and the other end is connected to the pulse readout resistor; the end of the current-limiting resistor away from the volatile threshold resistive memristor is connected to the input signal; and the end of the pulse readout resistor away from the volatile threshold resistive memristor is connected to signal ground. One end of the film capacitor is connected to the connection node between the volatile threshold resistive memristor and the current limiting resistor, and the other end is connected to signal ground.
[0008] Furthermore, the connection node between the volatile threshold resistive memristor and the film capacitor is the film potential node, and the connection node with the pulse readout resistor is the output pulse node; the input signal of the leakage integration circuit is a voltage signal, which is received through the current limiting resistor and transmitted to the film potential node; the output pulse node is connected to the adaptive leakage path control circuit, and the voltage pulse is generated at the output pulse node and output to the adaptive leakage path control circuit. The drain of the adaptive leakage transistor is connected to the membrane potential node, the gate is connected to the adaptive leakage path control circuit, and the source is connected to signal ground. The adaptive leakage transistor changes its on-resistance according to the control voltage applied to the gate by the adaptive leakage path control circuit, thereby changing the leakage current at the membrane potential node.
[0009] Furthermore, in the leakage integration circuit, the voltage signal is charged through the membrane capacitor, thereby raising the potential of the membrane potential node; When the voltage drop across the volatile threshold resistive memristor reaches its own threshold voltage, the volatile threshold resistive memristor switches from a high-resistance state to a low-resistance state, driving the film capacitor to release its accumulated charge, thereby generating a voltage pulse at the output pulse node and reducing the potential of the film potential node. When the voltage drop across the volatile threshold resistive memristor falls below its holding voltage, the volatile threshold resistive memristor switches from a low-resistance state to a high-resistance state, driving the film capacitor to re-accumulate charge.
[0010] Furthermore, in the adaptive leakage transistor, when the voltage difference between the gate and the source is lower than its own threshold voltage, the adaptive leakage transistor is in the off state; when the voltage difference between the gate and the source is higher than its own threshold voltage, the adaptive leakage transistor is in the on state; when the voltage difference between the gate and the source is greater, the on-resistance of the adaptive leakage transistor is smaller, and the leakage current at the membrane potential node is greater.
[0011] Furthermore, the adaptive leakage path control circuit includes an inverter pull-down transistor, a pull-up resistor, a charging switch transistor, a fixed capacitor, a discharging resistor, a capacitor switch transistor, and a switching capacitor; The gate of the inverter pull-down transistor is connected to the voltage pulse output of the leakage integrator circuit, the drain is connected to the pull-up resistor, and the source is connected to signal ground; the end of the pull-up resistor away from the inverter pull-down transistor is connected to the power input. The gate of the charging switch is connected to the connection node of the inverter pull-down transistor and the pull-up resistor, the source is connected to the power input, and the drain is connected to the fixed capacitor; the end of the fixed capacitor away from the charging switch is connected to the signal ground. The discharge resistor is connected in parallel across the fixed capacitor; The gate of the capacitor switch is connected to the connection node of the inverter pull-down transistor and the pull-up resistor, and the source and drain are respectively connected to the connection node of the switching capacitor and the connection node of the charging switch transistor and the fixed capacitor; the end of the switching capacitor away from the capacitor switch transistor is connected to signal ground.
[0012] Furthermore, the connection node between the inverter pull-down transistor and the pull-up resistor is the output pulse inversion node; The connection node between the charging switch and the fixed capacitor is a control voltage node; the control voltage node is connected to the leakage integration circuit and outputs a control voltage to the leakage integration circuit. The inverter pull-down transistor generates an inverted signal based on the voltage pulse signal received at the gate, and outputs the inverted signal to the charging switch transistor and the capacitor switch transistor, thereby changing the potential of the control voltage node and generating different control voltages to be output to the leakage integration circuit.
[0013] Furthermore, the inverter pull-down transistor turns on when it receives a high-level voltage pulse, generating a low-level inverted signal at the output pulse inverting node; the inverter pull-down transistor turns off when it receives a low-level voltage pulse, generating a high-level inverted signal at the output pulse inverting node.
[0014] Furthermore, the charging switch turns on when it receives a low-level inverted signal, causing the power input to charge the fixed capacitor and raise the potential of the control voltage node; the charging switch turns off when it receives a high-level inverted signal, stopping the charging of the fixed capacitor.
[0015] Furthermore, when the capacitor switch receives a low-level inverted signal, it turns off, thereby interrupting the electrical connection between the switching capacitor and the control voltage node, which in turn increases the charge accumulation rate of the fixed capacitor and the potential change rate of the control voltage node. When the capacitor switch receives a high-level inverted signal, it turns on, which makes the electrical connection between the switching capacitor and the control voltage node connected, thereby reducing the charge release rate of the fixed capacitor and the potential change rate of the control voltage node.
[0016] The embodiments of the present invention have the following beneficial effects: The embodiments of the present invention provide a dual-time-constant adaptive neuron circuit with leakage path control. This circuit can efficiently realize neuron function by utilizing the dynamic characteristics of volatile memristors, and efficiently realize frequency adaptive function by introducing an adaptive structure in the leakage circuit. The control signal has dual-time-constant variation characteristics, providing a core functional component for intelligent bionic systems.
[0017] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the basic structure of a dual-time-constant adaptive neuron circuit for leakage path control according to the present invention. Figure 2 The voltage waveforms of each node in the dual-time-constant adaptive neuron circuit for leakage path control according to the present invention are shown. Figure 3 The voltage waveforms at each node of the single-time-constant adaptive neuron circuit after removing the capacitor switch and the capacitor switching are shown. Figure 4 The diagram shows the voltage waveforms of each node in a dual-time-constant adaptive neuron circuit for leakage path control under different input voltages, as described in this invention.
[0020] Figure 5 The diagram shows the voltage waveforms of each node in the dual-time-constant adaptive neuron circuit for leakage path control according to the present invention under adaptive leakage tubes with different width-to-length ratios.
[0021] Figure 6 The diagram shows the voltage waveforms of each node in a dual-time-constant adaptive neuron circuit with leakage path control according to the present invention under different membrane capacitances.
[0022] Figure 7 The diagram shows the voltage waveforms of each node in a dual-time-constant adaptive neuron circuit for leakage path control under different discharge resistors, according to the present invention.
[0023] Figure label: V in For input signal, V dd For power input signal, V mem This refers to the membrane potential. V spike It is a voltage pulse signal. V spike_bar The inverted signal of the voltage pulse signal. V ctrl To control the voltage signal, R 1 represents the pulse readout resistor. R 2 is the discharge resistor. R 3 is the current-limiting resistor. R 4 is a pull-up resistor, and M1 is a capacitor switching transistor. M 2 is an adaptive leakage pipe. M 3 is the charging switch transistor. M 4 is the pull-down diode of the inverter. C 1 represents a film capacitor. C 2 is a fixed capacitor. C 3 is the switching capacitor. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0025] To overcome the aforementioned problem of adaptive implementation without leakage path control, this invention provides a leakage path control dual-time constant adaptive neuron circuit based on volatile memristors. This circuit can efficiently realize neuron function by utilizing the dynamic characteristics of volatile memristors, and efficiently realize frequency adaptive function by introducing an adaptive structure in the leakage circuit. The control signal has dual-time constant variation characteristics, providing a core functional component for intelligent bionic systems.
[0026] like Figure 1 As shown in the figure, the dual-time-constant adaptive neuron circuit for leakage path control provided in this embodiment of the invention mainly consists of two parts: the first part is a leakage integrator circuit, and the second part is an adaptive leakage path control circuit. The leakage integrator circuit is used to process the input signal... V in Accumulation is performed when the accumulated input signal V in Once the preset release threshold is reached, a voltage pulse is output to the adaptive leakage path control circuit. V spike The adaptive leakage path control circuit is used to control the voltage pulses output by the leakage integrator circuit. V spike Drive control voltage V ctrl Changes, and by controlling the voltage V ctrl The change adjusts the leakage current of the leakage integral circuit.
[0027] In this embodiment of the invention, the input stimulus is accumulated through a leakage integrator circuit, and a voltage pulse is emitted when the firing threshold is reached. This pulse is transmitted to the adaptive leakage path control circuit to increase the control voltage, thereby increasing the leakage current of the leakage integrator circuit. This reduces the current used to charge the neuron subsequently, resulting in a lower firing frequency. Simultaneously, the voltage pulse emitted by the neuron also reduces the capacitance in the adaptive leakage path control circuit, thus decreasing the time constant for the control voltage increase. During the period of re-integration after the neuron pulse is emitted, the control voltage slowly decreases through leakage in the RC circuit. During this period, the capacitance in the adaptive leakage path control circuit increases again, thus increasing the time constant for the control voltage decrease.
[0028] The internal structural composition of each part of the present invention is described in detail below: Leakage integration circuit: In this embodiment of the invention, the leakage integration circuit includes a volatile threshold resistive memristor and a film capacitor. C 1. Pulse readout resistor R 1. Current limiting resistor R 3 and adaptive leakage pipe M2; where one end of the volatile threshold resistive memristor is connected to a current-limiting resistor. R 3. Connect the other end to the pulse readout resistor. R 1; Current-limiting resistor R 3. Connect the end furthest from the volatile threshold resistive memristor to the input signal. V in Pulse readout resistor R 1. The end furthest from the volatile threshold resistive memristor is connected to signal ground; film capacitor C One end of 1 is connected to a volatile threshold resistive memristor and a current-limiting resistor. R The first end connects to node 3, and the other end connects to the signal ground.
[0029] The leakage integration circuit of this invention is controlled by a current-limiting resistor. R 3. Receive input voltage signal V in Volatile threshold resistive memristors and film capacitors C The connection node of 1 is the membrane potential. V mem Node, and pulse readout resistor R The connection node 1 is the output pulse node; the input signal of the leakage integrator circuit. V in The signal is a voltage signal, passing through a current-limiting resistor. R 3. Receive and transmit to membrane potential V mem Node; Output pulse node connects to the adaptive leakage path control circuit, voltage pulse V spike It is generated at the output pulse node and output to the adaptive leakage path control circuit; adaptive leakage tube M The drain of 2 is connected to the membrane potential. V mem At the node, the gate is connected to the adaptive leakage path control circuit, and the source is connected to signal ground; the adaptive leakage transistor... M 2. The control voltage applied to the gate according to the adaptive leakage path control circuit V ctrl By changing its own on-resistance, the membrane potential is thus altered. V mem Leakage current at the node.
[0030] Preferably, in the leakage integration circuit, through the film capacitor C 1. Charge accumulation is performed on the voltage signal, thereby increasing the membrane potential. V mem The potential of the node; When the voltage drop across the volatile threshold resistive memristor reaches its threshold voltage, the volatile threshold resistive memristor switches from a high-resistance state to a low-resistance state, driving the film capacitor. C1. It releases the accumulated charge, thereby generating a voltage pulse at the output pulse node. V spike At the same time, it reduces the membrane potential. V mem The potential of the node; When the voltage drop across the volatile threshold resistive memristor falls below its holding voltage, the volatile threshold resistive memristor switches from a low-resistance state to a high-resistance state, driving the film capacitor. C 1. Re-accumulate charge.
[0031] Preferably, in an adaptive leakage pipe M In step 2, when the voltage difference between the gate and source is lower than its own threshold voltage; adaptive leakage transistor M 2. In the off state; when the voltage difference between the gate and source is higher than its own threshold voltage, the adaptive leakage transistor... M 2 is in the on state; the greater the voltage difference between the gate and the source, the more adaptive leakage transistor... M The smaller the on-resistance of 2, the higher the film potential. V mem The larger the leakage current at the node.
[0032] Adaptive Leakage Path: The adaptive leakage path control circuit in this embodiment of the invention includes an inverter pull-down diode. M 4. Pull-up resistor R 4. Charging switch transistor M 3. Fixed capacitor C 2. Discharge resistor R 2. Capacitor switching transistor M 1 and switching capacitor C 3; Inverter pull-down tube M The voltage pulse of the gate connection leakage integrator circuit of 4. V spike The output drain is connected to a pull-up resistor. R 4. Source connected to signal ground; pull-up resistor R 4. Keep away from the inverter pull-down tube M One end of 4 is connected to the power input. V dd ; Charging switch transistor M The gate of 3 is connected to the pull-down diode of the inverter. M 4 with pull-up resistor R 4. Connection node, source connected to power input. V dd Drain connected to a fixed capacitor C 2; Fixed capacitor C 2. Keep away from the charging switch tube M One end of 3 is connected to signal ground; Discharge resistorR 2 in parallel with a fixed capacitor C 2. Both ends; Capacitor switching transistor M The gate of 1 is connected to the pull-down diode of the inverter. M 4 with pull-up resistor R At node 4, the source and drain are connected to switching capacitors respectively. C 3 and charging switch transistor M 3 with fixed capacitor C 2. Connection nodes; switching capacitors C 3. Keep away from capacitor switching transistors M One end of 1 is connected to signal ground.
[0033] In this embodiment of the invention, the inverter pull-down tube M 4 with pull-up resistor R The connection node at point 4 is the output pulse inversion node; Charging switch transistor M 3 with fixed capacitor C The connection node 2 is for control voltage. V ctrl Node; Control voltage V ctrl The node connects to the leakage integrator circuit and outputs a control voltage to the leakage integrator circuit. V ctrl ; Inverter pull-down tube M 4. Based on the voltage pulse received at the gate V spike Signal generates inverted signal V spike_bar Inverted signal V spike_bar Output to charging switch transistor M 3 and capacitor switching transistor M 1. This changes the control voltage. V ctrl The node's potential generates different control voltages. V ctrl Output to the leakage integration circuit.
[0034] Preferably, the inverter pull-down tube M 4. Upon receiving a high-level voltage pulse V spike When the circuit is turned on, a low-level inverted signal is generated at the output pulse inverting node. V spike_bar Inverter pull-down tube M 4. Upon receiving a low-level voltage pulse V spike When the signal is turned off, a high-level inverted signal is generated at the output pulse inverting node. Vspike_bar .
[0035] Preferably, the charging switch transistor M 3. Upon receiving a low-level inverted signal V spike_bar When the circuit is turned on, the power input is activated. V dd For fixed capacitors C 2. Charge, raise the control voltage V ctrl Node potential; charging switch transistor M 3. Upon receiving a high-level inverted signal V spike_bar Turn off at time, stop the fixed capacitor C 2. Charging.
[0036] Preferably, the capacitor switching transistor M 1. Turn off upon receiving a low-level inverted signal, causing the switching capacitor to switch off. C 3 and control voltage V ctrl The electrical connection of the node is interrupted, which in turn causes the fixed capacitor to... C The charge accumulation rate of 2 increases, controlling the voltage. V ctrl The rate of change of the node's potential increases; Capacitor switching transistor M 1. It turns on when it receives a high-level inverted signal, causing the switching capacitor to switch. C 3 and control voltage V ctrl The electrical connection of the node is made conductive, thereby enabling the fixed capacitor to conduct. C The charge release rate of 2 decreases, controlling the voltage. V ctrl The rate of change of potential at the node decreases.
[0037] In this embodiment of the invention, the adaptive leakage path control circuit detects the voltage pulse of the leakage integration circuit. V spike The node output pulls down the NMOS transistor when the leakage integrator circuit delivers a pulse. M 4 conduction grounding makes V spike_bar The node is at a low level, which in turn causes the pull-up PMOS transistor to... M 3 conduction, V ctrl Node potential is input via power supply V dd The charge gradually increases, which causes the NMOS transistor to... M2. Increased conduction level and increased leakage current in the leakage integrator circuit limit the input current of the neuron and reduce the frequency of continuous pulse firing, thereby achieving adaptive behavior; simultaneously, during pulse firing, the NMOS transistor... M 1. Turn off, so that the capacitor C 3. Remove it from the circuit, the time constant of the RC circuit becomes smaller, and it is restored after the pulse is emitted, thereby realizing the behavior of double time constant and double exponential change.
[0038] The following is in conjunction with the appendix Figure 2 The timing diagram of the dual-time-constant adaptive neuron circuit for leakage path control according to the present invention is described below: For a leakage integrator circuit, at the initial moment, V mem When the impedance is 0, the memristor is in a high-resistance state, and at the same time... V ctrl Low level, via M The adaptive leakage path of circuit 2 is turned off, at which point the leakage integrator circuit prepares to accumulate the input. Upon input stimulus... V in Below, neurons begin to leak integrals. C 1. Charge simultaneously C 1. Passed by memristor and R The right-side leakage path, formed by 1, discharges slowly, overall... V mem Increase. When V mem Increase until the voltage drop across the memristor is greater than its threshold voltage. V th The memristor undergoes a resistance change and enters a low-resistance state, resulting in a decrease in the resistance of the leakage path on the right side. C 1. Discharge rapidly, and in V spike A voltage pulse is generated at the node, and at the same time V mem Rapidly decrease. When V mem Reduce until the voltage drop across the memristor is less than its holding voltage. V hold The memristor returns to the high-resistance state, at which point one pulse delivery is completed.
[0039] For the adaptive leakage path control circuit, the first stage is the pulse delivery phase. During the process of the leakage integrator circuit delivering the voltage pulse, when... V spike Node voltage increases until it is greater than M At a turn-on voltage of 4, M 4 conduction and V spike_bar The node is pulled low, which in turn causes the PMOS transistor to...M 3 conduction, V ctrl Node voltage via supply voltage V dd The charge gradually increases. At this point... M 2 of V gs rise, M The increased conductivity of 2, the increased leakage current in the left adaptive leakage path of the leakage integral circuit, and the decreased current of the input neuron result in a slower subsequent charging speed of the neuron and a lower frequency of continuous firing, exhibiting adaptive firing behavior.
[0040] At the same time, during pulse delivery, the NMOS transistor M 1. Turn off, so that the capacitor C 3. Removing it from the circuit reduces the time constant of the RC circuit, meaning that at this point... V ctrl It exhibits a rapid exponential increase. After the pulse output ends, V spike The node goes low. M 4. Re-shut down and make V spike_bar The node is pulled high, causing the PMOS transistor to... M 3. Shutdown V ctrl The node voltage gradually decreases through the RC circuit discharge, at which point it enters the leakage integration phase. Simultaneously, the NMOS transistor... M 1. Re-energizes the capacitor, causing it to... C 3. When it is reintroduced into the circuit, the time constant of the RC circuit increases, that is, at this time... V ctrl The index shows a relatively slow decline.
[0041] If input later V in If it persists, the two stages described above will repeat continuously. However, it should be noted that in the initial stage, due to... V ctrl Smaller, M The left adaptive leakage pathway of neuron 2 has a smaller leakage current, a larger charging current, and a higher firing frequency, which makes... V ctrl The increase will be greater than the decrease, the charging current of the neuron will continue to fluctuate and decrease, and the firing frequency will continue to decrease; when the frequency of the neuron's firing pulses decreases to a certain value, V ctrl The increase will equal the decrease, thus stabilizing the frequency of neuron pulse firing, at which point the circuit enters a stable operating mode.
[0042] The present invention relates to a dual-time-constant adaptive neuron circuit for leak path control. Figure 3 A comparison with single-time-constant adaptive neuron circuits reveals that the overall workflow of a single-time-constant adaptive neuron circuit is consistent with that of a dual-time-constant adaptive neuron circuit, except that... V ctrl There are some differences in the changes. Specifically, compared to the dual-time-constant adaptive neuron circuit... V ctrl The circuit initially exhibits a rapid exponential increase, followed by a slower exponential decrease. Because the capacitance and resistance of the adaptive leakage path control circuit in the single-time-constant adaptive neuron circuit are fixed, the time constant of this RC circuit will remain unchanged. V ctrl It exhibits a single speed change.
[0043] As can be seen, compared to traditional single-time-constant adaptive neuron circuits, the dual-time-constant adaptive neuron circuit of this invention significantly improves the adaptability of neurons and the performance of LSNN networks by introducing a dual-exponential change mechanism. Its fast exponential change portion enables neurons to respond quickly to frequent inputs, while the slow exponential change portion helps maintain memory for a longer period, thus simultaneously addressing both short-term and long-term adaptive needs. Furthermore, the dual-time-constant design makes it more flexible in handling tasks at different time scales and eliminates the need for strict time constant matching, enhancing the hardware's adjustability and robustness.
[0044] The volatile threshold resistive switching memristor upon which this invention is based can be a Mott memristor based on Mott phase transition, a diffuse memristor based on a metal conductive filament, or an OTS memristor based on chalcogenides, etc. Preferably, the Mott memristor can be based on VO2 or NbO. x Devices using E-Motte insulator materials, diffused memristors can be devices based on active metals such as Ag and Cu, while OTS memristors can be chalcogenide devices based on chalcogen elements such as Se and Te.
[0045] Specifically, taking the VO2 MOT memristor as an example, Figures 4 to 7 The present invention provides a leakage path control dual-time-constant adaptive neuron circuit based on a VO2 volatile threshold resistive Mott memristor under different input voltages. V in Different width-to-length ratios M 2. Different capacitors C 1 and different resistors R Waveform diagram of operation under step 2.
[0046] right Figure 4 The top image shows the waveform with the original parameters, and the bottom left image shows the waveform with smaller parameters. Vin The waveform at that time, the lower right is larger. V in The waveform at that time. It can be observed that when the input voltage increases, the charging current of the neuron at the initial moment increases and the firing frequency is higher, but correspondingly, V ctrl The rate of increase is also faster; and after stabilization, V ctrl The voltage will become higher than before, resulting in more leakage current in the adaptive leakage path, thereby limiting the larger input current caused by a larger input voltage. At the same time, the firing frequency of the stabilized neuron will also be higher.
[0047] right Figure 5 The top image shows the waveform with the original parameters, and the bottom left image shows the waveform with the original parameters. M The waveform with a small width-to-length ratio is shown in the lower right corner. M The waveform when the width-to-length ratio of 2 is large. It can be observed that... M 2. When the aspect ratio increases, the conductivity under the same conditions increases, meaning the leakage current of the adaptive leakage path increases. Therefore, initially, the charging current of the neuron decreases, and the firing frequency decreases. V ctrl The rate of increase also slowed down; and after stabilizing, V ctrl It will become lower than before to accommodate the larger leakage current and smaller neuronal input current caused by the larger aspect ratio. At the same time, the frequency of neuronal pulse firing will also be lower after stabilization.
[0048] right Figure 6 The top image shows the waveform with the original parameters, and the bottom left image shows the waveform with the original parameters. C The waveform at a shorter time (1 hour), lower right is... C The waveform when 1 is larger. It can be observed that... C When 1 increases, it will directly increase the RC time constant of the leakage integrator circuit, which will slow down the speed at which the neuron reaches the threshold voltage. This will significantly reduce the pulse firing frequency of the neuron at each stage.
[0049] right Figure 7 The top image shows the waveform with the original parameters, and the bottom left image shows the waveform with smaller parameters. R The waveform at time 2, with the larger value in the lower right corner. R The waveform at time 2. It can be observed that, due to... R The change in the number 2 will increase the RC time constant of the adaptive leakage path control section, which in turn will lead to V ctrl The overall rate of change has slowed down; while V ctrlIt is also a key control signal that limits the input current of neurons. A slower rate of change in this signal will cause the input current of neurons to recover more slowly after the pulse ends, thereby reducing the pulse firing frequency.
[0050] It is important to note that, in order to V ctrl This allows the phenomenon to be maintained and accumulated across multiple pulses, resulting in an effective and stable adaptive phenomenon. This requires... V ctrl Become relative V mem The "slow variable" refers to ensuring that the time constant of the adaptive leakage path control circuit is much larger than that of the leakage integral circuit. This demonstrates that the invention can achieve its purpose under various parameter conditions, showcasing its adjustability, adaptability, and robustness.
[0051] In summary, this invention proposes a novel dual-time-constant adaptive neuron circuit for leakage path control in neuromorphic computing. It utilizes a volatile threshold-resistance memristor as the core device of the leakage integrator circuit to simulate neuron firing behavior. An additional leakage branch controlled by a transistor is introduced in the leakage portion. When the neuron fires a pulse, the auxiliary circuit inverts the high and low levels of the pulse signal and transmits it to the simple-designed and low-hardware-overhead adaptive leakage path control circuit. This controls the transistor to increase its conduction level, thereby increasing the leakage current of the leakage integrator circuit, limiting the neuron's input current, and reducing its continuous firing frequency, thus achieving adaptive behavior. Simultaneously, using only an additional transistor and capacitor, it achieves the goal of decreasing the capacitance during pulse input and increasing it after pulse termination, thereby changing the time constant of the RC circuit, thus realizing dual-time-constant and dual-threshold changes. Compared to traditional single-time-constant adaptive neuron circuits, this invention significantly improves the adaptability of neurons and the performance of LSNN networks. It can simultaneously meet both short-term and long-term adaptation needs, enhance the adjustability and robustness of hardware, and is conducive to integration into large-scale edge computing systems, such as intelligent human-computer interaction systems. It can also achieve efficient computing in these resource-constrained application scenarios, showing great development potential.
[0052] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0053] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.
[0054] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.
[0055] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.
Claims
1. A dual-time-constant adaptive neuron circuit for leakage path control, characterized in that, Including leakage integration circuit and adaptive leakage path control circuit; The leakage integration circuit is used to accumulate the input signal. When the accumulated input signal reaches the preset emission threshold, it outputs a voltage pulse to the adaptive leakage path control circuit. The adaptive leakage path control circuit is used to drive the control voltage to change according to the voltage pulse output by the leakage integrator circuit, and to adjust the leakage current of the leakage integrator circuit by the change of the control voltage.
2. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 1, characterized in that, The leakage integration circuit includes a volatile threshold-resistance memristor, a film capacitor, a pulse readout resistor, a current-limiting resistor, and an adaptive leakage transistor. One end of the volatile threshold-resistance memristor is connected to the current-limiting resistor, and the other end is connected to the pulse readout resistor. The end of the current-limiting resistor furthest from the volatile threshold-resistance memristor is connected to the input signal. The end of the pulse readout resistor furthest from the volatile threshold-resistance memristor is connected to signal ground. One end of the film capacitor is connected to the connection node between the volatile threshold resistive memristor and the current limiting resistor, and the other end is connected to signal ground.
3. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 2, characterized in that, The connection node between the volatile threshold resistive memristor and the membrane capacitor is the membrane potential node, and the connection node between the memristor and the pulse readout resistor is the output pulse node; the input signal of the leakage integration circuit is a voltage signal, which is received and transmitted to the membrane potential node through the current limiting resistor. The output pulse node is connected to the adaptive leakage path control circuit. A voltage pulse is generated at the output pulse node and output to the adaptive leakage path control circuit. The drain of the adaptive leakage transistor is connected to the membrane potential node, the gate is connected to the adaptive leakage path control circuit, and the source is connected to signal ground. The adaptive leakage transistor changes its on-resistance according to the control voltage applied to the gate by the adaptive leakage path control circuit, thereby changing the leakage current at the membrane potential node.
4. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 3, characterized in that, In the leakage integration circuit, the voltage signal is charged through the membrane capacitor, thereby raising the potential of the membrane potential node; When the voltage drop across the volatile threshold resistive memristor reaches its own threshold voltage, the volatile threshold resistive memristor switches from a high-resistance state to a low-resistance state, driving the film capacitor to release its accumulated charge, thereby generating a voltage pulse at the output pulse node and reducing the potential of the film potential node. When the voltage drop across the volatile threshold resistive memristor falls below its holding voltage, the volatile threshold resistive memristor switches from a low-resistance state to a high-resistance state, driving the film capacitor to re-accumulate charge.
5. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 3, characterized in that, In the adaptive leakage transistor, when the voltage difference between the gate and the source is lower than its own threshold voltage, the adaptive leakage transistor is in the off state; when the voltage difference between the gate and the source is higher than its own threshold voltage, the adaptive leakage transistor is in the on state; when the voltage difference between the gate and the source is greater, the on-resistance of the adaptive leakage transistor is smaller, and the leakage current at the membrane potential node is greater.
6. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 1, characterized in that, The adaptive leakage path control circuit includes an inverter pull-down transistor, a pull-up resistor, a charging switch transistor, a fixed capacitor, a discharging resistor, a capacitor switch transistor, and a switching capacitor. The gate of the inverter pull-down transistor is connected to the voltage pulse output of the leakage integrator circuit, the drain is connected to the pull-up resistor, and the source is connected to signal ground; the end of the pull-up resistor away from the inverter pull-down transistor is connected to the power input. The gate of the charging switch is connected to the connection node of the inverter pull-down transistor and the pull-up resistor, the source is connected to the power input, and the drain is connected to the fixed capacitor; the end of the fixed capacitor away from the charging switch is connected to the signal ground. The discharge resistor is connected in parallel across the fixed capacitor; The gate of the capacitor switch is connected to the connection node of the inverter pull-down transistor and the pull-up resistor, and the source and drain are respectively connected to the connection node of the switching capacitor and the connection node of the charging switch transistor and the fixed capacitor; the end of the switching capacitor away from the capacitor switch transistor is connected to signal ground.
7. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 6, characterized in that, The connection point between the inverter pull-down transistor and the pull-up resistor is the output pulse inversion node; The connection node between the charging switch and the fixed capacitor is a control voltage node; the control voltage node is connected to the leakage integration circuit and outputs a control voltage to the leakage integration circuit. The inverter pull-down transistor generates an inverted signal based on the voltage pulse signal received at the gate, and outputs the inverted signal to the charging switch transistor and the capacitor switch transistor, thereby changing the potential of the control voltage node and generating different control voltages to be output to the leakage integration circuit.
8. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 7, characterized in that, The inverter pull-down transistor turns on when it receives a high-level voltage pulse, generating a low-level inverted signal at the output pulse inversion node; the inverter pull-down transistor turns off when it receives a low-level voltage pulse, generating a high-level inverted signal at the output pulse inversion node.
9. The dual-time-constant adaptive neuron circuit for leakage path control according to claim 7, characterized in that, The charging switch turns on when it receives a low-level inverted signal, causing the power input to charge the fixed capacitor and raise the potential of the control voltage node; the charging switch turns off when it receives a high-level inverted signal, stopping the charging of the fixed capacitor.
10. A dual-time-constant adaptive neuron circuit for leakage path control according to claim 7, characterized in that, When the capacitor switch receives a low-level inverted signal, it turns off, thereby interrupting the electrical connection between the switching capacitor and the control voltage node, which in turn increases the charge accumulation rate of the fixed capacitor and the potential change rate of the control voltage node. When the capacitor switch receives a high-level inverted signal, it turns on, which makes the electrical connection between the switching capacitor and the control voltage node connected, thereby reducing the charge release rate of the fixed capacitor and the potential change rate of the control voltage node.