A method for manufacturing a wafer level package product by stacking a photoresist layer

Abstract

The application discloses a kind of through superimposed photoresist layer the method for manufacturing wafer level packaging product, and the application belongs to wafer level packaging field, including step one: preparation glass wafer, release layer and sputtering layer are coated on the glass wafer top;Step two: the first heavy wiring layer is formed on the sputtering layer top;Step three: metal seed layer is set on the first heavy wiring layer top;Step four: photoresist is coated on the first heavy wiring layer top to form photoresist one;Step five: the photoresist one is carried out alignment exposure operation to photoresist one by mask one;Step six: photoresist one is developed to form opening structure one.The application utilizes the way of high tackiness wet film photoresist to manufacture silicon through hole bump, can solve the technical problem of silicon through hole bump preparation in advanced packaging field, effectively improve the product quality and production yield of chip, suitable for advanced packaging silicon through hole bump whole process preparation link.

Description

Technical Field

[0001] This invention belongs to the field of wafer-level packaging technology, specifically a method for fabricating wafer-level packaged products by stacking photoresist layers. Background Technology

[0002] In a fan-out multi-chip package structure, it typically includes a chip, a front redistribution layer, a back redistribution layer, through-hole vias (TMVs), and molding compound. The front of the chip is connected to the front redistribution layer, and the back of the chip is connected to the back redistribution layer. Multiple through-hole vias connect the upper and lower redistribution layers, and the upper and lower redistribution layers are connected by electroplated copper pillars (called TMVBumps) to enable the circuitry between the upper and lower redistribution layers. The electroplated copper pillars are high, generally requiring a height of 200~300um. This type of bump requires a high photoresist thickness, which poses challenges to the thickness of the photoresist coating, exposure, and development.

[0003] Even the highest viscosity wet film photoresist currently available in the industry is difficult to achieve the required thickness through a single coating. Existing technologies attempt to use a step-by-step electroplating scheme with two coatings, two exposures, and two developments. However, in this scheme, the second photoresist coating must be carried out on the substrate where the first photoresist layer is retained. The coating uniformity, alignment accuracy, and contour control of the development window are extremely difficult. This can easily lead to poor bonding between the two photoresist layers, window position displacement, or development residue. Consequently, it affects the complete coverage and interface bonding strength of the secondary electroplated bump and the primary electroplated bump, ultimately reducing the structural reliability and electrical performance of the TMV bump. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, this invention provides a method for fabricating wafer-level packaged products by stacking photoresist layers. This method effectively solves the problem that the electroplated copper pillars in the current Fan-out multi-chip packaging on the market need to be adapted to high-thickness photoresist due to the 200-300um height requirement, which poses a severe challenge to the photoresist coating, exposure, and development processes.

[0005] The technical solution adopted by the present invention is as follows: The present invention proposes a method for fabricating wafer-level packaged products by superimposing photoresist layers, including step one: preparing a glass wafer, and coating a release layer and a sputtering layer on the glass wafer;

[0006] Step 2: A first redistribution layer is formed above the sputtered layer;

[0007] Step 3: Deposit a metal seed layer above the first rewiring layer;

[0008] Step 4: Apply photoresist over the first redistribution layer to form photoresist layer 1;

[0009] Step 5: Perform an alignment and exposure operation on the photoresist layer using a photomask pair;

[0010] Step 6: Develop the photoresist layer to form the opening structure.

[0011] Step 7: Perform an electroplating operation on the first redistribution layer to form a bump, the bump being higher than the photoresist layer.

[0012] Step 8: Apply photoresist over the first photoresist layer and the first bump to form the second photoresist layer;

[0013] Step 9: Perform alignment and exposure operations on the photoresist layer 2 using mask 2;

[0014] Step 10: Develop the second photoresist layer to form the second opening structure, which exposes the first protrusion.

[0015] Step 11: Perform an electroplating operation on the first protrusion to form a second protrusion, the second protrusion being larger in size than the first protrusion;

[0016] Step 12: Remove the first photoresist layer and the second photoresist layer, and etch away the metal seed layer to form the molded through-hole bump.

[0017] Preferably, step thirteen: a chip is mounted above the first redistribution layer, and a copper pillar is provided above the chip;

[0018] Step Fourteen: Moldulate the chip and the molded through-hole bumps to form a molding layer;

[0019] Step 15: Grind the molding compound to expose bump two and the copper pillar;

[0020] Step 16: A second wiring layer is formed above the copper pillar and the second protrusion.

[0021] Preferably, the size of the second opening structure is larger than the size of the first opening structure, such that the second protrusion completely covers the first protrusion.

[0022] Preferably, the size of the second opening structure is 10 micrometers larger than the size of the first opening structure.

[0023] Preferably, the height of the first bump exceeds the height of the first photoresist layer, and the surface of the first bump is mushroom-shaped.

[0024] Preferably, the thickness of the first photoresist layer or the second photoresist layer is in the range of 100-140 micrometers.

[0025] Preferably, the height of the second rewiring layer is the difference between the target height of the molded through-hole bump and the height of the first rewiring layer.

[0026] Preferably, both the first wiring layer and the second wiring layer are composite structures comprising a metal wiring layer and a dielectric layer.

[0027] Preferably, after step seven, plasma cleaning is performed on the surfaces of the photoresist layer one and the bump one.

[0028] Furthermore, a release layer is disposed above the glass wafer, a sputtering layer is disposed above the release layer, and a first redistribution layer is disposed above the sputtering layer;

[0029] A molded through-hole protrusion is provided above the first redistribution layer;

[0030] The molded through-hole protrusion includes protrusion one, and protrusion two is provided above protrusion one;

[0031] The size of the second protrusion is larger than the size of the first protrusion.

[0032] Furthermore, a copper pillar is provided above the chip, and a second wiring layer is provided above the copper pillar and the molded through-hole bump. A molding layer is provided between the first wiring layer and the second wiring layer.

[0033] The beneficial effects achieved by the present invention using the above structure are as follows:

[0034] (1) This solution proposes a method for fabricating wafer-level packaged products by stacking photoresist layers. It adopts a step-by-step molding method of two photoresist coatings and two electroplatings. By retaining the first photoresist layer as the substrate for the second coating, it not only simplifies the process flow and avoids damage to the structure caused by repeated photoresist peeling, but also utilizes the "mushroom-shaped" structure of the first electroplating bumps that protrudes beyond the photoresist surface to provide self-alignment guidance for the second photolithography, which greatly improves the pattern accuracy and development yield of the second windowing.

[0035] (2) The size of the second opening structure is designed to be larger than that of the first opening structure, so that the second protrusion formed on the second opening structure completely covers the first protrusion formed on the first opening structure, thus eliminating the risk of splicing gaps and interface contamination between the two protrusion layers. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of step one of the methods for fabricating wafer-level packaged products by stacking photoresist layers according to the present invention;

[0037] Figure 2 This is a schematic diagram of step two of the method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0038] Figure 3 This is a schematic diagram of step three of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0039] Figure 4 This is a schematic diagram of step four of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0040] Figure 5 This is a schematic diagram of step five of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0041] Figure 6 This is a schematic diagram of step six of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0042] Figure 7 This is a schematic diagram of step seven of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0043] Figure 8 This is a schematic diagram of step eight of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0044] Figure 9 This is a schematic diagram of step nine of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0045] Figure 10 This is a schematic diagram of step ten of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0046] Figure 11 This is a schematic diagram of step eleven of a method for fabricating wafer-level packaged products by stacking photoresist layers according to the present invention;

[0047] Figure 12 This is a schematic diagram of step 12 of a method for fabricating wafer-level packaged products by stacking photoresist layers proposed in this invention;

[0048] Figure 13 This is a schematic diagram of step thirteen of a method for fabricating wafer-level packaged products by stacking photoresist layers according to the present invention;

[0049] Figure 14 This is a schematic diagram of step fourteen of a method for fabricating wafer-level packaged products by stacking photoresist layers according to the present invention;

[0050] Figure 15 This is a schematic diagram of step fifteen of a method for fabricating wafer-level packaged products by stacking photoresist layers according to the present invention;

[0051] Figure 16 This is a schematic diagram of step sixteen of a method for fabricating wafer-level packaged products by stacking photoresist layers, as proposed in this invention.

[0052] The components are as follows: 1. Glass wafer; 2. Release layer; 3. Sputtering layer; 31. Metal seed layer; 4. First redistribution layer; 5. Photoresist layer one; 6. Photoresist layer two; 7. Bump one; 8. Bump two; 9. Chip; 10. Molding layer; 11. Copper pillar; 12. Second redistribution layer; 13. Metal wiring layer; 14. Dielectric layer; 15. Molded via bump; 16. Mask one; 17. Mask two; 18. Opening structure one; 19. Opening structure two.

[0053] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0054] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0055] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0056] like Figures 1-16 As shown, this invention proposes a method for fabricating wafer-level packaged products by stacking photoresist layers, such as... Figure 1 As shown, the process includes step one: preparing a glass wafer 1, which serves as the substrate. A release layer 2 is coated on the surface of the glass wafer 1. The thickness of the release layer 2 can range from 0.3 to 0.7 μm to facilitate precise separation of the glass wafer 1 from the packaging structure, avoiding damage to the packaging structure during the separation process and ensuring product yield. Simultaneously, the release layer 2 can fill minor imperfections on the surface of the glass wafer, providing a flat substrate for the deposition of the composite sputtering layer. Subsequently, a sputtering layer 3 is deposited above the release layer 2, including but not limited to deposition via magnetron sputtering. The sputtering layer 3 can be a composite layer of titanium and copper, with the titanium layer having a thickness of 0.09 to 0.11 μm and the copper layer a thickness of 0.36 to 0.44 μm. The titanium layer is the lower layer, and the copper layer is the upper layer. The purpose of the sputtering layer 3 is to protect the release layer 2 beneath it.

[0057] like Figure 2As shown, step two involves fabricating a first wiring layer 4, comprising multiple dielectric layers 14 and multiple metal wiring layers 13, above the sputtered layer 3. The multiple dielectric layers 14 possess excellent insulation and temperature resistance, effectively isolating the metal wiring layers and preventing short circuits. Simultaneously, the flexible nature of the dielectric layers 14 buffers thermal and mechanical stresses in subsequent processes, reducing the risk of structural cracking. The multiple metal wiring layers 13 precisely achieve electrical interconnection between the chip 9 and external circuits, shortening signal transmission paths, reducing signal delay and loss, and improving the electrical performance of the packaged product. The first wiring layer 4, as the core interconnection structure, can adapt to high-density wiring requirements, providing a stable electrical and structural foundation for subsequent chip mounting and bump fabrication, ensuring the overall interconnect reliability of the packaged structure.

[0058] like Figure 3 As shown, step three: The metal seed layer 31 serves as the seed layer for subsequent electroplating operations. A metal seed layer 31 is uniformly deposited on the surface of the first redistribution layer 4 and in the pre-defined bump preparation area using a physical vapor deposition (PVD) process, such as magnetron sputtering. The metal seed layer 31 can be a composite layer of titanium and copper layers, where the titanium layer thickness can be 0.09~0.11μm and the copper layer thickness can be 0.36~0.44μm. The lower layer is the titanium layer, and the upper layer is the copper layer. The purpose of the metal seed layer 31 is to serve as the seed layer for subsequent electroplating operations, providing a uniform and continuous current path for the subsequent electroplating process. This ensures that metal ions are uniformly deposited within the photoresist window area, avoiding defects such as voids, burrs, or inconsistent heights in bumps 7 and 8 due to uneven current distribution.

[0059] Step 4: Coat photoresist over the first interconnect layer 4 to form photoresist layer 5. This can be achieved through a double coating process to form photoresist layer 5 on the surface of the first interconnect layer 4. The thickness of photoresist layer 5 is 100-140μm, which is precisely matched with the height of the target molded via bump 15. This provides sufficient space for the first bump electroplating and allows for the compensation of minor errors in subsequent processes by reserving a 10-micron margin. This ensures that the bump 7 achieves the preset support and positioning effect after molding. Photoresist layer 5 also serves as a patterning mask for the first electroplating. Its uniformity and thickness stability directly determine the accuracy of the electroplating window, laying the foundation for the quality of subsequent bump molding.

[0060] like Figure 4As shown, step four involves precisely aligning and exposing the photoresist layer 5 using mask 16. This ensures that the position of the electroplated window is precisely aligned with the target interconnect point of the first redistribution layer 4, preventing misalignment that could lead to poor contact between the subsequent bumps and the redistribution layer, thus guaranteeing the reliability of the electrical interconnects. Precise exposure defines the window shape, providing clear guidance for subsequent electroplating. Simultaneously, precise control of the exposure range avoids overexposure or underexposure affecting window accuracy, ensuring consistency in the size and position of each window during mass production and improving process stability.

[0061] like Figure 5 As shown, step five involves developing the exposed photoresist layer 5 to remove the photoresist from the exposed areas while preserving the photoresist in the unexposed areas. This process creates a neatly shaped, precisely sized opening structure 18 within the photoresist layer 5, ensuring that the opening structure 18 accurately exposes the target interconnect points of the first wiring layer 4. This provides a guarantee for the strong bonding between the bumps 7 and the wiring layer. The development process effectively removes residual photoresist impurities, preventing defects such as bumps, bubbles, and delamination during electroplating. It also controls the degree of development, avoiding over-development that enlarges the opening size or under-development that leaves residual photoresist, further improving the opening accuracy and surface cleanliness.

[0062] like Figure 6 As shown, step six: electroplating is performed in the developing window area. During the electroplating process, metal ions are uniformly deposited in the window area to form a height-controllable bump 7. Its design, which extends beyond the surface of the photoresist layer 5, can achieve precise support and positioning for the subsequent bump 8, ensuring that the bump 8 can accurately cover the bump 7 and avoid displacement or misalignment.

[0063] Among them, the surface of bump 7 has a mushroom-shaped structure, which can increase the contact area between bump 7 and bump 8, improve the bonding strength of the two bumps, and prevent bumps from falling off or breaking in subsequent processes. At the same time, bump 7 is in direct contact with the first redistribution layer 4, which can achieve a firm electrical connection between the two, laying the foundation for the overall electrical conduction of the subsequent molded through-hole bump 15.

[0064] like Figure 7 As shown, step seven involves plasma cleaning of the surfaces of photoresist layer 5 and bump 7 using oxygen (O2) and nitrogen (N2) plasma. The purpose is to remove residual electroplating solutions from the surfaces of photoresist layer 5 and bump 7. The etching depth of oxygen (O2) and nitrogen (N2) is 0.3 μm, which slightly roughens the surface, increases the contact area between photoresist layer 6 and the substrate, significantly improves the adhesion of photoresist layer 6, and prevents defects such as peeling or lifting of photoresist layer 6 during subsequent exposure, development, and electroplating processes. Simultaneously, plasma treatment does not damage the structure and conductivity of bump 7, nor does it compromise the integrity of photoresist layer 5, ensuring the smooth progress of subsequent processes.

[0065] like Figure 8 As shown, step eight: While retaining photoresist layer 5, directly coat photoresist layer 6. The thickness of photoresist layer 6 ranges from 100-140 μm, simplifying the process and avoiding structural damage and positioning deviations caused by removing photoresist layer 1, while achieving seamless connection between the two photoresist layers. The high-viscosity wet film photoresist can form a strong bond with the plasma-treated surfaces of photoresist layer 5 and bump 7, further enhancing interlayer adhesion. The consistent thickness of photoresist layer 6 with photoresist layer 5 ensures that bump 8, after electroplating, works in conjunction with bump 7 to achieve the target height of the molded through-hole bump 15. The 10 μm margin compensates for accumulated errors during the two electroplating processes, ensuring the final overall dimensional accuracy of the bump. As a second electroplating mask, the high viscosity of photoresist layer 6 prevents photoresist deformation and detachment during electroplating, ensuring stable masking performance.

[0066] like Figure 9 As shown, in step nine: Mask 2 17 performs alignment exposure on photoresist layer 2 6. The exposure energy is reduced by 100 mJ / cm² compared to the first exposure. This is suitable for the thickness and viscosity of photoresist layer 2 6, avoiding overexposure and blurred edges due to excessive exposure energy, or insufficient exposure due to insufficient energy, thus ensuring exposure accuracy. The 10 μm increase in the window size of mask 2 17 allows for precise complete coverage of bump 2 8 over bump 1 7, preventing incomplete bump connection due to alignment deviation. It also increases the contact area between the two bump layers, improving bonding strength and electrical conductivity stability. Precise alignment exposure ensures accurate alignment between the window of photoresist layer 2 6 and bump 1 7, providing guidance for precise electroplating of bump 2 8 and guaranteeing the synergistic molding effect of the two bump layers.

[0067] like Figure 10 As shown, step ten: developing the exposed photoresist layer 2 6 precisely removes the exposed area of ​​the photoresist layer 2 6, forming a neatly shaped and precisely sized opening structure 2 19 in the photoresist layer 2 6. This ensures that the opening structure 2 19 precisely exposes the top of the bump 1 7, and the size of the opening structure 2 19 is larger than the size of the opening structure 1 18, ensuring complete coverage of the bump 2 8. In some preferred embodiments, the size of the opening structure 2 19 is 10 μm larger than the size of the opening structure 1 18. During the development process, photoresist residue and surface impurities can be effectively removed, preventing impurities from affecting the electroplating quality of the bump 2 8. At the same time, the development speed and degree are controlled to avoid damaging the photoresist layer 1 5 and the bump 1 7, ensuring the connection accuracy of the two photoresist windows and laying the foundation for the subsequent overall forming of the bump.

[0068] like Figure 11As shown, step eleven involves electroplating in the developing window area. The electroplating height is the difference between the height of the target molded via bump 15 and the height of the first electroplating, ensuring that bump 2 8 completely covers the portion of bump 1 7 that extends beyond photoresist layer 5. This further enhances the bonding strength between the two bump layers, forming a complete and robust molded via bump 15 profile, avoiding defects such as poor conductivity and structural fragility caused by gaps. During electroplating, metal ions are uniformly deposited, resulting in a smooth and dense bump surface with excellent conductivity and mechanical strength, providing reliable protection for the electrical interconnection and mechanical support of the subsequent packaging structure.

[0069] like Figure 12 As shown, step 12 involves removing photoresist layer 5 and photoresist layer 6 using a desmearing process without damaging the structure of the molded via bump 15 and the first redistribution layer 4. This ensures the bump surface is clean and free of residual impurities, guaranteeing the conductivity of the bump and the subsequent bonding effect. UBM etching precisely removes excess metal seed layer 31 from the bump surface, ensuring the height and shape of the molded via bump 15 meet preset standards. It also optimizes the surface flatness of the bump, preventing surface burrs and protrusions from affecting subsequent molding and wiring layer fabrication. The final molded via bump 15 formed in this step enables precise electrical interconnection between the first redistribution layer 4 and the subsequent second redistribution layer 12, while also possessing good mechanical support capabilities.

[0070] like Figure 13 As shown, step thirteen: Chip 9 is mounted at a preset position on the first wiring layer 4. Copper pillars 11 have already been installed on chip 9. During mounting, ensure precise alignment between chip 9 and the preset interconnect points on the first wiring layer 4 to achieve a strong electrical connection and ensure efficient signal transmission from chip 9. The mounting pressure and precision can be controlled during the mounting process to avoid damage to chip 9 or poor interconnection caused by mounting misalignment. Simultaneously, a tight bond is formed between chip 9 and the wiring layer, reducing signal transmission loss and improving the electrical performance of the packaged product. Precise mounting provides structural stability for subsequent processes such as molding and polishing, preventing chip 9 from shifting or detaching in subsequent processes.

[0071] like Figure 14 As shown, step fourteen: A molding layer 10 is formed above the chip 9 and the molded via bump 15 through a molding process to achieve all-round encapsulation of the chip 9, the molded via bump 15, and the first redistribution layer 4, providing good mechanical protection, buffering mechanical impacts and vibrations in subsequent processes, and preventing chip 9 from breaking or bumps from fracturing. Simultaneously, the molding layer 10 effectively isolates external moisture, dust, impurities, etc., preventing chip 9 and bumps from failing due to environmental corrosion, improving the environmental adaptability and lifespan of the packaged product. The molding layer 10 also has a certain degree of insulation, further isolating conductive structures, preventing short circuits, and ensuring the stability of the product's electrical performance.

[0072] like Figure 15 As shown, step fifteen involves grinding and thinning the molding layer 10 to expose the top of the molded via bump 15 and the copper pillar 11 above the chip 9. This makes the surface of the molding layer 10 flat, precisely exposing the top of the molded via bump 15 and the copper pillar 11 above the chip 9 without damaging their structure. This ensures that the subsequent second wiring layer 12 can form a precise and secure connection with both. The flat grinding surface avoids defects such as uneven thickness and poor contact during the subsequent wiring layer fabrication process, ensuring the precise molding of the second wiring layer 12. Simultaneously, grinding and thinning enables a thinner and lighter packaged product design, adapting to the application requirements of miniaturized and high-density packaging.

[0073] like Figure 16 As shown, step sixteen: A second wiring layer 12, comprising multiple dielectric layers 14 and multiple metal wiring layers 13, is fabricated above the copper pillar 11 and the molded via bump 15. This enables top-level electrical interconnection of the packaged product, connecting the chip 9 to external package pins, completing the closed-loop electrical path of the entire package structure, and ensuring efficient and stable signal transmission. This further shortens the signal transmission path, reduces signal delay and loss, and improves the electrical performance of the packaged product. The second wiring layer 12 forms a strong bond with the copper pillar 11 and the molded via bump 15, ensuring interconnect reliability. Simultaneously, it works synergistically with the first wiring layer 4 to give the entire package structure excellent structural stability and electrical performance, meeting the requirements of high-precision electronic devices, and ultimately completing the fabrication of the wafer-level package structure.

[0074] This invention discloses a structure for fabricating wafer-level packaged products by stacking photoresist layers. A release layer 2 is disposed on top of a glass wafer 1, and a sputtering layer 3 is disposed on top of the release layer 2. The release layer 2 and the sputtering layer 3 provide basic support and conductivity for the overall structure. A first wiring layer 4 is disposed on top of the sputtering layer 3. A chip 9 and a molded via bump 15 are disposed on top of the first wiring layer 4. A copper pillar 11 is disposed on top of the chip 9. A second wiring layer 12 is disposed on top of the copper pillar 11 and the molded via bump 15. A molding compound 10 is disposed between the first wiring layer 4 and the second wiring layer 12. The first wiring layer 4 and the second wiring layer 12 form a complete electrical interconnection path. The molded via bump 15 enables precise connection between the two wiring layers. The molding compound 10 ensures structural stability and environmental adaptability. The chip 9 is connected to the second wiring layer 12 through the copper pillar 11. The overall structure has the advantages of high density, high reliability, and thinness, which can meet the packaging requirements of high-precision electronic devices.

[0075] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0076] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0077] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for fabricating wafer-level packaged products by stacking photoresist layers, characterized in that: include: Step 1: Prepare a glass wafer (1), and coat a release layer (2) and a sputtering layer (3) on the glass wafer (1); Step 2: A first redistribution layer (4) is formed above the sputtered layer (3); Step 3: Set a metal seed layer (31) above the first redistribution layer (4); Step 4: Apply photoresist over the first redistribution layer (4) to form a photoresist layer (5); Step 5: Perform alignment and exposure operation on the photoresist layer 1 (5) through mask 1 (16); Step 6: Develop the photoresist layer (5) to form an opening structure (18). Step 7: Perform an electroplating operation on the first redistribution layer (4) to form a bump (7), the bump (7) being higher than the photoresist layer (5); Step 8: Apply photoresist over the first photoresist layer (5) and the first bump (7) to form the second photoresist layer (6); Step 9: Perform alignment and exposure operation on the photoresist layer 2 (6) through mask 2 (17); Step 10: Develop the second photoresist layer (6) to form the second opening structure (19), which exposes the first bump (7). Step 11: Perform an electroplating operation on the first protrusion (7) to form the second protrusion (8), the size of the second protrusion (8) being larger than the size of the first protrusion (7); Step 12: Remove the first photoresist layer (5) and the second photoresist layer (6), and etch away the metal seed layer (31) to form the molded through-hole bump (15).

2. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: include: Step 13: Attach a chip (9) above the first redistribution layer (4), and a copper pillar (11) is provided above the chip (9). Step 14: The chip (9) and the molded through-hole bumps (15) are encapsulated to form an encapsulation layer (10). Step 15: Grind the molding compound (10) to expose the second bump (8) and the copper pillar (11); Step 16: A second wiring layer (12) is formed above the copper pillar (11) and the second protrusion (8).

3. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: The size of the second opening structure (19) is larger than the size of the first opening structure (18), so that the second protrusion (8) completely covers the first protrusion (7).

4. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: The size of the second opening structure (19) is 10 micrometers larger than the size of the first opening structure (18).

5. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: The height of the first bump (7) exceeds the height of the first photoresist layer (5), and the surface of the first bump (7) is mushroom-shaped.

6. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: The thickness of the first photoresist layer (5) or the second photoresist layer (6) is in the range of 100-140 micrometers.

7. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 2, characterized in that: The height of the second rewiring layer (12) is the difference between the target height of the molded through-hole bump (15) and the height of the first rewiring layer (4).

8. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: Both the first wiring layer (4) and the second wiring layer (12) are composite structures containing a metal wiring layer (13) and a dielectric layer (14).

9. The method for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: After step seven, plasma cleaning is performed on the surfaces of the photoresist layer one (5) and the bump one (7).

10. A structure for fabricating wafer-level packaged products by stacking photoresist layers according to any one of claims 1 to 9, characterized in that: A release layer (2) is disposed above the glass wafer (1), a sputtering layer (3) is disposed above the release layer (2), and a first redistribution layer (4) is disposed above the sputtering layer (3). A molded through-hole protrusion (15) is provided above the first redistribution layer (4); The molded through hole protrusion (15) includes protrusion one (7), and protrusion two (8) is provided above protrusion one (7); The size of the second protrusion (8) is larger than the size of the first protrusion (7).

11. The structure for fabricating wafer-level packaged products by stacking photoresist layers according to claim 1, characterized in that: A copper pillar (11) is provided above the chip (9), and a second wiring layer (12) is provided above the copper pillar (11) and the molded through hole bump (15). A molding layer (10) is provided between the first wiring layer (4) and the second wiring layer (12).

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